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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是121-130 订阅

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Probabilistic arithmetic and energy efficient embedded signal processing

Probabilistic arithmetic and energy efficient embedded signa...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： George, J. Marr, B. Akgul, B.E.S. Palem, K.V. CREST School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA 30332-0250 United States

ISBN: (纸本)1595935436

Probabilistic arithmetic, where the ith output bit of addition and multiplication is correct with a probability pi, is shown to be a vehicle for realizing extremely energy-efficient, embedded computing. Specifically, probabilistic adders and multipliers, realized using elements such as gates that are in turn probabilistic, are shown to form a natural basis for primitives in the signal processing (dsp) domain. In this paper, we show that probabilistic arithmetic can be used to compute the fft in an extremely energy-efficient manner, yielding energy savings of over 5.6X in the context of the widely used synthetic aperture radar (sar) application [1]. Our results are derived using novel probabilistic cmos (pcmos) technology, characterized and applied in the past to realize ultra-efficient architectures for probabilistic applications [2, 3, 4]. When applied to the dsp domain, the resulting error in the output of a probabilistic arithmetic primitive, such as an adder for example, manifests as degradation in the signal-to-noise ratio (snr) of the sar image that is reconstructed through the fft algorithm. In return for this degradation that is enabled by our probabilistic arithmetic primitives - degradation visually indistinguishable from an image reconstructed using conventional deterministic approaches-significant energy savings and performance gains are shown to be possible per unit of snr degradation. These savings stem from a novel method of voltage scaling, which we refer to as biased voltage scaling (or bivos), that is the major technical innovation on which our probabilistic designs are based. Copyright 2006 ACM.

关键词： Probabilistic logics

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A prototype network embedded in textile fabric 2

A prototype network embedded in textile fabric

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Mackenzie, Kenneth Hudson, Eric Maule, Drew Jayaraman, Sundaresan Park, Sungmee College of Computing Georgia Institute of Technology AtlantaGA30332 United States School of Textile and Fiber Engineering Georgia Institute of Technology AtlantaGA30332 United States

ISBN: (纸本)1581133995

A digital network between active components or "buttons" atop an e-textile fabric must handle the inexact placement of wires in the fabric both for signal distribution and for power distribution. We approach the problem of signal distribution by making the pin logic of the buttons reconfigurable and by providing enough local state to allow an external agent to discover and to reconfigure the buttons into a working network. We describe a prototype system of a 2x2 array of FPGAand- microcontroller buttons atop a fabric with 0.100"-pitch wiring including architecture decisions, circuits and software algorithms. Copyright 2001 ACM.

关键词： Textiles

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Dynamic coprocessor management for FPGA-enhanced compute platforms

Dynamic coprocessor management for FPGA-enhanced compute pla...

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Huang, Chen Vahid, Frank Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems Univ. of California Irvine United States

ISBN: (纸本)9781605584690

Various commercial programmable compute platforms have their processor architecture enhanced with field-programmable gate arrays (FPGAs). In a common usage scenario, an application loads custom processors into the FPGA to speed up application execution compared to processor-only execution. Transient applications, changing application workloads, and limited FPGA capacity have led to a new problem of operating-system-controlled dynamic management of the loading of coprocessors into the FPGAs for best overall performance or energy. We define the Dynamic Coprocessor Management problem and provide a mapping to an online optimization problem known as Metrical Task systems. We introduce a robust heuristic, called the fading cumulative benefit (FCBenefit) heuristic, that outperforms other heuristics, including a previously developed one for MTS. For two distinct application sets, we generate numerous workloads and show that the FCBenefit heuristic provides best results across all considered workloads. In our simulations, the heuristic's results were within 9% of the offline optimal for performance, and within 3% for energy. The heuristic may be applicable to a wide variety of dynamic architecture management problems. Copyright 2008 ACM.

关键词： Field programmable gate arrays (FPGA)

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Platform-dependent code generation for embedded real-time software

Platform-dependent code generation for embedded real-time so...

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2013 international conference on compilers, architecture and synthesis for embedded systems, cases 2013

作者： Kim, BaekGyu Phan, Linh T. X. Sokolsky, Oleg Lee, Lnsup University of Pennsylvania United States

ISBN: (纸本)9781479914005

Code generation for embedded systems is challenging, since the generated code (e.g., C code) is expected to run on a heterogeneous set of target platforms with different characteristics, such as hardware/software architectures and programming interfaces. We propose a code generation framework that provides the flexibility to generate different source code that is executable on each target platform. In our framework, the platform-dependent characteristics of a target platform are explicitly specified by an Architectural Analysis Description Language (AADL) model and a code snippet repository. The AADL model captures hardware/software architectural aspects of the platform, such as periodic/aperiodic threads and their interactions with sensors and actuators. The code snippet repository contains platform-dependent code snippets that are categorized according to the functions required to implement the components of the AADL model. These two elements of the platform capability are then used by the code generation algorithm to generate platform-dependent code for the given platform. We demonstrate the applicability of our framework using a case study of code generation for two infusion pump systems. © 2013 IEEE.

关键词： embedded systems

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Self-powered wearable sensor platforms for wellness

Self-powered wearable sensor platforms for wellness

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international conference on compilers, architecture and synthesis for embedded systems, cases 2015

作者： Misra, Veena Calhoun, Ben Bhansali, Shekhar Lach, John Datta, Suman Ozturk, Mehmet Bozkurt, Alper Oralkan, Omer Strohmaier, Jason Department of ECE North Carolina State Univ. United States Department of ECE University of Virginia United States Department of ECE Florida International University United States Department of EE Pennsylvania State University United States Department of ECE Bilkent University Ankara Turkey

ISBN: (纸本)9781467383202

Health care continues to be one of the biggest challenges facing our society. Factors such as lifestyle choices, genetics, aging, stress and environmental exposures play a critical role in determining health outcomes. Wearable technologies that can enable continuous/long-term personal health monitoring and personal environmental monitoring can empower users to make better lifestyle decisions and improve health outcomes. While wearable devices promise a compelling future of achieving wellness, current wearable products are not addressing the needs of the health space. To achieve this future, key challenges in wearable systems such as battery life, form factor, sensor functionality, configurability and data analysis will have to be carefully addressed to ensure user adoption and effectively manage health. © 2015 IEEE.

关键词： Energy harvesting

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Challenges for embedded Multicore architecture

Challenges for Embedded Multicore Architecture

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6th embedded systems Week (ESWEEK)

作者： Carro, Luigi Gaydadjiev, Georgi N. Univ Fed Rio Grande do Sul Inst Informat Av Bento Goncalves 9500Bloco 4 Porto Alegre RS Brazil Delft Univ Technol Fac Elect Engn Math & Comp Sci NL-2628 CD Delft Netherlands

In this tutorial we discuss the impact of multicore architectures for embedded devices at different levels, ranging from heterogeneous/homogeneous ISAs to the organization and software development.

ISBN: (纸本)9781605589039

In this tutorial we discuss the impact of multicore architectures for embedded devices at different levels, ranging from heterogeneous/homogeneous ISAs to the organization and software development.

关键词： architectures embedded architectures Multicore architectures Computer organization

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Exploiting residue number system for power-efficient digital signal processing in embedded processors

Exploiting residue number system for power-efficient digital...

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embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Chokshi, Rooju Berezowski, Krzysztof S. Shrivastava, Aviral Piestrak, Stanislaw J. Microsoft Corporation Redmond WA United States Computer Science and Engineering Arizona State University Tempe AZ United States TIMA Laboratory 38031 Grenoble France LICM University of Metz 57070 Metz France

ISBN: (纸本)9781605586267

2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propagation. Residue Number System (RNS) breaks free of these bonds by decomposing a number into parts and performing arithmetic operations in parallel, significantly reducing the breadth of carry propagation. Consequently, RNS arithmetic has been proposed as a solution to improve the power-efficiency of arithmetic hardware. However, limitations of the expressiveness of RNS in terms of arithmetic operations together with overheads related to interaction with 2's complement arithmetic make programmable processor design that takes advantage of these benefits challenging. In this paper we meet this challenge by multi-tier synergistic co-design of architecture, micro-architecture, hardware components, as well as compilation techniques. Our experiments not only demonstrate simultaneous improvement of up to 30% in performance and 57% reduction in functional unit power consumption, but also that most of these benefits can be exploited with automatically generated code. Copyright 2009 ACM.

关键词： Digital signal processing

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Work-in-Progress: DAPHNE - An Automotive Benchmark Suite for Parallel Programming Models on embedded Heterogeneous Platforms

Work-in-Progress: DAPHNE - An Automotive Benchmark Suite for...

引用

embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Sommer, Lukas Stock, Florian Solis-Vasquez, Leonardo Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany

ISBN: (纸本)9781450369244

Due to the ever-increasing computational demand of automotive applications, and in particular autonomous driving capabilities, the automotive industry and its suppliers are starting to adopt parallel and heterogeneous embedded computing platforms. However, C and C++, the currently dominating programming languages in this industry, do not provide sufficient mechanisms to fully exploit such platforms. As a result, vendors have begun to employ true parallel programming models such as OpenMP, CUDA or OpenCL. In this work, we report on a benchmark suite developed specifically to investigate the applicability of established parallel programming models to automotive workloads on heterogeneous platforms.

关键词： Automotive industry

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An architecture for embedded software integration using reusable components

An architecture for embedded software integration using reus...

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Wang, Shige Shin, Kang G. Real-Time Computing Laboratory Dept. of Elec. Eng./Computer Science University of Michigan 1301 Beal Avenue Ann Arbor MI 48109-2122 United States

ISBN: (纸本)1581133383

The state-of-art approaches to embedded real-time software development are very costly. The high development cost can be reduced significantly by using model-based integration of reusable components (models and/or software modules). To this end, we propose an architecture that supports integration of software components and their behaviors, and reconfiguration of component behavior at executable-code-level. In this architecture, components are designed and used as building blocks for integration, each of which is modeled with event-based external interfaces, a control logic driver, and service protocols. The behavior of each component is specified as a Finite State Machine (FSM), and the integrated behavior is modeled as a Nested Finite State Machine (NFSM). These behavior specifications can be packed into a Control Plan program, and loaded to a runtime system for execution or to a verification tool for analysis. With this architecture, embedded software can be constructed by selecting and then connecting (as needed) components in an asset library, specifying their behaviors and mapping them to an execution platform. Integration of heterogeneous implementations and vendor neutrality are also supported. Our evaluation based on machine tool control software development using this architecture has shown that it can reduce development and maintenance costs significantly, and provide high degrees of reusability and reconfigurability.

关键词： embedded systems

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Developing embedded multi-threaded applications with CATAPULTS, a domain-specific language for generating thread schedulers

Developing embedded multi-threaded applications with CATAPUL...

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Roper, Matthew D. Olsson, Ronald A. Department of Computer Science University of California Davis Davis CA 95616-8562 United States

ISBN: (纸本)159593149X

This paper describes CATAPULTS, a domain-specific language for creating and testing application-specific user level thread schedulers. Using a domain-specific language to write thread schedulers provides three advantages. First, it modularizes the thread scheduler, making it easy to plug in and experiment with different schedulers. Second, using a domain-specific language for scheduling code helps prevent several of the common programming mistakes that are easy to make when programming in low-level C or assembly. Finally, the CATAPULTS translator has multiple backends that generate code for different languages and libraries. This makes it easy to prototype an embedded application on a regular PC, and then develop the final version on the embedded hardware;the CATAPULTS translator will take care of generating the appropriate code for both the PC proto-type and the final embedded version of the program. Using our implementation of CATAPULTS for Z-World's embedded Rabbit processors, we obtained a performance gain of about 12.6% at the expense of about 12.7% increase in code size for a fairly typical embedded application. Copyright 2005 ACM.

关键词： Formal languages

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