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embedded system and application aware design of deregulated energy delivery systems

Embedded system and application aware design of deregulated ...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Xuejing He Robert P. Dick Russ Joseph University of Michigan Northwestern University

Voltage regulation circuity can be removed from embedded systems, commonly saving 30% of the printed circuit board area. Most unregulated systems suffer from performance degradation or premature failure as battery voltage decreases. Researchers have described a technique called power deregulation, in which performance is preserved by activating processor cores as battery voltage decreases. Unfortunately, the operating lifespans of such systems may be limited due to mismatches between the battery discharge profiles and the voltage-performance characteristics of processors. This paper provides a technique for codesign of power deregulated systems in which battery, processor, and workload characteristics are jointly considered. This technique extends lifespans of deregulated embedded systems. We also describe new battery and system performance and power models, some of which are based on a recently commercialized silver-zinc battery technology that is well suited to power deregulated systems. These models support lifetime simulation of regulated and deregulated embedded systems. If it is possible to find an appropriate match between embedded system and battery characteristics, the proposed design technique results in lifetimes similar to those of regulated systems and eliminates the need for bulky power regulation components.

关键词： Resistance Regulators Electrical resistance measurement

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Exploiting cache conflicts to reduce radiation sensitivity of operating systems on embedded systems

Exploiting cache conflicts to reduce radiation sensitivity o...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Thiago Santini Paolo Rech Luigi Carro Flávio Rech Wagner PPGC Institute of Informatics Federal University of Rio Grande do Sul

In this paper, we investigate how the presence of a general purpose operating system influences the reliability of modern embedded systems-on-Chips (SoCs). We analytically study the difference in the reliability of SoCs when executing the application bare to the metal and on top of the Linux kernel. Our analysis demonstrates that Linux presence barely affects the Silent Data Corruption rate while it greatly increases the system Functional Interruption (FI) rate (up to 7.48 times) if no preventive measures are taken. Furthermore, we analytically show that cache conflicts between the operating system and application can significantly reduce the Linux-induced FI rate increase. To support our analysis, a total of four representative embedded applications were individually executed bare to the metal and on top of Linux on a 28nm ARM-based SoC exposed to an accelerated neutron beam. Our experimental results demonstrate that, by carefully tuning cache conflicts, it is possible to successfully limit the Linux-induced FI rate increase to 3.85 times. The proposed solution is general and readily applied to a broad set of applications and embedded systems.

关键词： Gold Ions Concurrent computing Reliability

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Optimization of multi-channel BCH error decoding for common cases

Optimization of multi-channel BCH error decoding for common ...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Russ Dill Aviral Shrivastava Hyunok Oh Arizona State University Hanyang University

This paper proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. We break the BCH decoding process into its three basic blocks: syndrome calculation, the error locator polynomial generation, and the roots of the error locator polynomial computation. While an existing multi-channel BCH decoder consists of several single-channel BCH decoders operating in parallel, this paper utilizes a pooled group of shared decoding blocks. By considering the frequency of errors, the proposed pooled group approach requires fewer hardware blocks than in a traditional multi-channel configuration with a negligible impact on performance. Combined with a specialized root finding unit for blocks with only 1 error, our scheme reduces hardware area by 47%-71% and dynamic power by 44%-59% with 2% performance degradation in typical NAND flash systems. With a constant hardware area, the proposed scheme can improve throughput by 3x-5x or NAND flash lifetime by 1.4x-4.5x.

关键词： Force Error correction codes Polynomials Throughput Clocks

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Does customizing inexactness help over simplistic precision (bit-width) reduction? A case study

Does customizing inexactness help over simplistic precision ...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Ashutosh Ingole Biswaroop Maiti John Augustine Krishna Palem Dept. of Computer Science and Engineering IIT Madras Dept. of Computer Science Rice University

In the last two decades, energy has become a crucial resource whose consumption must be minimized while designing computing systems. This has affected every aspect of computing ranging from large scale supercomputers and data centers to small scale (but high volume) embedded systems comprising filters, digital signal processors (DSPs), and accelerators. Energy constraints play a particularly crucial role in battery operated devices (cell phones, wearables) and other energy constrained systems like unmanned aerial vehicles and sensor networks. In this backdrop of efforts to improve energy efficiency, a very interesting technique aimed at trading error for energy gains emerged over a decade ago. Typical computing systems are engineered to be exact. Energy gains have been achieved while compromising soft constraints like running time. This new technique called inexact computing or approximate computing aims push the envelope to achieve energy gains at the cost of an increased inexactness or error in the system. This radical shift has often yielded surprisingly significant energy gains with little to no side effects because many algorithms and applications (like DSP applications, big data applications, large scale numerical models) are inherently tolerant to error.

关键词： Probabilistic logic Kalman filters embedded systems Computer science Computational modeling Computer architecture Context

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Energy-interference-free system and toolchain support for energy-harvesting devices

Energy-interference-free system and toolchain support for en...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Alexei Colin Alanson P. Sample Brandon Lucia Carnegie Mellon University Disney Research Pittsburgh

Energy-harvesting computers eschew tethered power and batteries by harvesting energy from their environment. The devices gather energy into a storage element until they have enough energy to power a computing device. Once powered, the device functions until its energy is depleted, when it browns out and gathers more energy. Software on such computing devices executes intermittently, as power is available. An intermittent program execution may be interrupted by a power failure at any point and with each interruption, the volatile state of the device (e.g., register file, RAM) is erased, and its non-volatile state (e.g., FRAM) is retained. Recent work [3] defined and characterized the intermittent execution model, in which a program's execution spans periods of execution perforated by power failures. Our position is that designers of system and toolchain support for energy-harvesting devices should treat energy-interference-freedom and intermittence as first-class design concerns in future systems, methodologies, and techniques. From this position, we discuss the design of an energy-interference-free platform for monitoring and manipulating the energy and device state of an energy-harvesting device. We see our platform as an essential step toward a toolchain for energy-harvesting devices that supports debugging, testing, and analysis of realistic, intermittent executions.

关键词： Debugging Monitoring Computer bugs Energy states Nonvolatile memory Energy storage embedded systems

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NUVA: Architectural support for runtime verification of parametric specifications over multicores

NUVA: Architectural support for runtime verification of para...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Ahmed Nassar Fadi J. Kurdahi Wael Elsharkasy Center for Embedded and Cyber-physical Systems University of California Irvine CA USA

Runtime Verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification methods. To address the substantial performance and power overhead of pure software RV frameworks, this paper introduces NUVA, which stands for nonuniform verification architecture, a distributed automata-based RV architecture for parametric specifications in the form of parameterized finite-state automata, with a case study over a cache-coherent nonuniform-memory-access (ccNUMA) multiprocessor. The core of NUVA is a coherent distributed automata transactional memory (ATM) that efficiently maintains states of a dynamic population of automata checkers organized into a rooted dynamic directed acyclic graph (DAG) concurrently shared among all processor nodes. A cycle-accurate model of a ccNUMA multiprocessor confirms that performance slowdown is 1~3% and NoC message traffic increases by 10~15% at parametric event density 1 of 0.025 EPI for two compute-intensive scientific benchmarks having irregular concurrent data structures. The detailed architecture and implementation metrics in TSMC 40nm CMOS technology are presented. NUVA can be dimensioned to incur average total power overhead of less than 140mW and area overhead of 4mm 2 for a quad-core multiprocessor chip, at operating frequency of 250MHz. It is also estimated to incur 1.9~2.6% area overhead and 0.5~1% power overhead when integrated with Intel's family of high-end desktop and mobile quad-core processors operating at 1.6~3.2GHz. Our silicon implementation achieves average performance 2 of 1.5 MEPS/mW. For a processor core with 5 MIPS/mW, this corresponds to a 3.2% drop in energy efficiency at parametric event density of 0.01 EPI.

关键词： Monitoring Automata Runtime Hardware Computer bugs Cost accounting Semantics

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Approximation-aware Multi-Level Cells STT-RAM cache architecture

Approximation-aware Multi-Level Cells STT-RAM cache architec...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Felipe Sampaio Muhammad Shafique Bruno Zatt Sergio Bampi Jörg Henkel Câmpus Farroupilha Federal Institute of Rio Grande do Sul (IFRS) Brazil Informatics Institute PPGC Federal University of Rio Grande do Sul (UFRGS) Brazil Chair for Embedded Systems (CES) Karlsruhe Institute of Technoloay (KIT) Germany GACl. PPGC. CDTec. Federal University of Pelotas (UFPel) Brazil

Current manycore processors exhibit large on-chip last-level caches that may reach sizes of 32MB - 128MB and incur high power/energy consumption. The emerging Multi-Level Cells (MLC) STT-RAM memory technology improves the capacity and energy efficiency issues of large-sized memory banks. However, MLC STT-RAM incurs non-negligible protection overhead to ensure reliable operations when compared to the Single-Level Cells (SLC) STT-RAM. In this paper, we propose an approximation-aware MLC STT-RAM cache architecture, which is partially-protected to restrict the reliability overhead and in turn leverages variable resilience characteristics of different applications for adaptively curtailing the protection overhead under a given error tolerance level. It thereby improves the energy-efficiency of the cache while meeting the reliability requirements. Our cache architecture is equipped with a latency-aware hardware module for double-error correction. To achieve high energy efficiency, approximation-aware read and write policies are proposed that perform approximate storage management while tolerating some errors bounded within the user-provided tolerance level. The architecture also facilitates runtime control on the quality of applications' results. We perform a case study on the next-generation advanced video encoding that exhibit memory-intensive functional blocks with varying resilience properties and support for parallelism. Experimental results demonstrate that our approximation-aware MLC STT-RAM based cache architecture can improve the energy efficiency compared to state-of-the-art fully-protected caches (7%-19%, on average), while incurring minimal quality penalties in the output (-0.219% to -0.426%, on average). Furthermore, our architecture supports complete error protection coverage for all cache data when processing non-resilient application. The hardware overhead to implement our approximation-aware management negligibly affects the energy efficiency (0.15%-1.3%

关键词： Approximation methods Reliability Memory management Random access memory Magnetic tunneling Resilience

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Automated ISA Branch Coverage Analysis and Test Case Generation for Retargetable Instruction Set Simulators

Automated ISA Branch Coverage Analysis and Test Case Generat...

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Wagstaff, Harry Spink, Tom Franke, Bjoern Univ Edinburgh Edinburgh EH8 9YL Midlothian Scotland

ISBN: (纸本)9781450330503

Processor design tools integrate in their workflows generators for instruction set simulators (ISS) from architecture descriptions. However, it is difficult to validate the correctness of these simulators. ISA coverage analysis is insufficient to isolate modelling faults, which might only be exposed in corner cases. We present a novel ISA branch coverage analysis, which considers every possible execution path within an instruction and, on demand, generates new test cases to cover the missing paths. We have applied this analysis to industry standard EEMBC and SPEC CPU2006 benchmarks and show that for an ARM V5T model neither of these benchmark suites provides a sufficient ISA coverage to exercise every path through each instruction of the whole instruction set.

关键词： fault tolerant computing instruction sets program diagnostics program testing ARM V5T model EEMBC benchmark ISA branch coverage analysis ISS SPEC CPU2006 benchmark instruction execution path modelling fault isolation processor design tools retargetable instruction set simulators test case generation Benchmark testing Context Generators Registers Semantics Vectors instruction sets CASING INSPECTION analysis programme Benchmark testing Fault tolerant computing program testing Registers dynamos international space stations European Union Institute for Security Studies Semantics Coverage execution path

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A System-level Simulation Framework for Evaluating Task Migration in MPSoCs

A System-level Simulation Framework for Evaluating Task Migr...

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Quan, Wei Pimentel, Andy D. Univ Amsterdam Inst Informat NL-1012 WX Amsterdam Netherlands Natl Univ Def Technol Sch Comp Sci Hunan Peoples R China

ISBN: (纸本)9781450330503

Task migration is the transfer of the execution of a process (task) from one processing element to another. It originates from the massive deployment of distributed systems in the parallel computing field to enable dynamic load distribution, fault resilience and to enhance data access locality. With the development of MultiProcessor System-on-Chip (MPSoC) architectures, the topic of task migration has recently regained research interest in the embedded systems domain. In this paper, we present a high-level simulation framework to study task migration for MPSoC systems. With this framework, different migration methodologies on different underlying hardware systems can be easily and rapidly modeled, simulated and evaluated during the early stages of design. By using this high-level simulation framework, a designer can study the migration impact on the overall performance of the system by exploring different task migration mechanisms (determining what and how to migrate) or using different migration policies (determining when to migrate which tasks whereto) in a specific task migration mechanism. Using a number of experiments, we demonstrate the capabilities of our simulation framework.

关键词： embedded systems MPSoC task migration simulation

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Team Up: Cooperative Memory Management in embedded systems

Team Up: Cooperative Memory Management in Embedded Systems

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Stilkerich, Isabella Taffner, Philip Erhardt, Christoph Dietrich, Christian Wawersich, Christian Stilkerich, Michael Univ Erlangen Nurnberg D-91054 Erlangen Germany

ISBN: (纸本)9781450330503

The use of a managed, type-safe languages such as Java in real-time and embedded systems can offer productivity and, in particular, safety and dependability benefits over the dominating unsafe languages at reasonable costs. A JVM that has dynamic memory-management needs to provide an implicit memory-management strategy, that is, for example, a garbage collector (GC) or stack allocation provided by the escape analysis of the JVM's compiler: Explicit management of dynamically allocated memory (i.e., by use of functions such as C's malloc () and free ()) is vulnerable to programming errors such as neglected or false memory release operations causing memory leaks or dangling pointers. Such operations have the potential to break the soundness of the type system and are therefore usually not available for strongly typed languages. Type-safe languages in combination with static analyses - which respect hardware as well as system-specific information - can efficiently be employed to provide a runtime system including memory management (MM) that is specifically suited to an embedded application on a particular hardware device. In the context of this paper, we present novel memory-management strategy we implemented in our KESO JVM. It is a latency-aware garbage-collection algorithm called LAGC. Also, we introduce the static analyses that can assist LAGC. The application developers have to ensure that there is enough time for the GCs to run. Hardware characteristics such as soft-error proneness of the hardware or the memory layout can also be taken into consideration as demanded by the system configuration. This is achieved by integrating the GCs in the design process of the whole system just as any other user application, which is the reason why this approach is called cooperative memory management. The suggested strategies require reasonably low overhead.

关键词： Memory Management Garbage Collection Design Languages

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