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A high-level model of embedded flash energy consumption

A high-level model of embedded flash energy consumption

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Pallister, James Eder, Kerstin Hollis, Simon J. Bennett, Jeremy Univ Bristol Bristol BS8 1TH Avon England Embecosm Lymington Hants England

ISBN: (纸本)9781450330503

The alignment of code in the flash memory of deeply embedded SoCs can have a large impact on the total energy consumption of a computation. We investigate the effect of code alignment in six SoCs and find that a large proportion of this energy (up to 15% of total SoC energy consumption) can be saved by changes to the alignment. A flexible model is created to predict the read-access energy consumption of flash memory on deeply embedded SoCs, where code is executed in place. This model uses the instruction level memory accesses performed by the processor to calculate the flash energy consumption of a sequence of instructions. We derive the model parameters for five SoCs and validate them. The error is as low as 5%, with a 11% average normalized RMS deviation overall. The scope for using this model to optimize code alignment is explored across a range of benchmarks and SoCs. Analysis shows that over 30% of loops can be better aligned. This can significantly reduce energy while increasing code size by less than 4%. We conclude that this effect has potential as an effective optimization, saving significant energy in deeply embedded SoCs.

关键词： embedded systems energy consumption flash memories system-on-chip RMS deviation code alignment deeply embedded SoC embedded flash energy consumption energy proportion flash memory instruction level memory access root mean square deviation Ash Energy consumption Memory management Nonvolatile memory Optimization Random access memory System-on-chip system-on-chip flash memories energy consumption Root mean square deviation random access machine Store management Nonvolatile memory SYNTHETIC ORGANIC CHEMICALS embedded systems Ashes Codes

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Context-Sensitive Timing Simulation of Binary embedded Software

Context-Sensitive Timing Simulation of Binary Embedded Softw...

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Ottlik, Sebastian Stattelmann, Stefan Viehl, Alexander Rosenstiel, Wolfgang Bringmann, Oliver FZI Res Ctr Informat Technol D-76131 Karlsruhe Germany ABB Corp Res Res Area Software D-68526 Ladenburg Germany Univ Tubingen D-72076 Tubingen Germany

ISBN: (纸本)9781450330503

We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the microarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional simulation.

关键词： Software Timing Simulation Binary Level Simulation Instruction Set Simulation System Level Design Virtual Prototyping

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Message from the cases 2014 program co-chairs

2014 International Conference on Compilers, Architecture and...

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2014 international conference on compilers, architecture and synthesis for embedded systems, cases 2014 2014年

作者： Iyer, Ravi Raghunathan, Anand

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A high-level model of embedded flash energy consumption

A high-level model of embedded flash energy consumption

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： James Pallister Kerstin Eder Simon J. Hollis Jeremy Bennett University of Bristol Embecosm

关键词： Ash Energy consumption System-on-chip Memory management Random access memory Optimization Nonvolatile memory

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Context-sensitive timing simulation of binary embedded software

Context-sensitive timing simulation of binary embedded softw...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Sebastian Ottlik Stefan Stattelmann Alexander Viehl Wolfgang Rosenstiel Oliver Bringmann FZI Research Center for Information Technolog Karlsruhe Germany ABB Corporate Research Research Area Software Wallstadter Straße Ladenburg Germany University of Tübingen Tuebingen Germany

关键词： Context Timing Analytical models Data models Software Databases Context modeling

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Team up: Cooperative memory management in embedded systems

Team up: Cooperative memory management in embedded systems

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Isabella Stilkerich Philip Taffner Christoph Erhardt Christian Dietrich Christian Wawersich Michael Stilkerich Friedrich-Alexander University Erlangen-Nuremberg Germany

The use of a managed, type-safe languages such as Java in realtime and embedded systems can offer productivity and, in particular, safety and dependability benefits over the dominating unsafe languages at reasonable costs. A JVM that has dynamic memory-management needs to provide an implicit memory-management strategy, that is, for example, a garbage collector (GC) or stack allocation provided by the escape analysis of the JVM's compiler: Explicit management of dynamically allocated memory (i.e., by use of functions such as C's malloc () and free()) is vulnerable to programming errors such as neglected or false memory release operations causing memory leaks or dangling pointers. Such operations have the potential to break the soundness of the type system and are therefore usually not available for strongly typed languages. Type-safe languages in combination with static analyses - which respect hardware as well as system-specific information - can efficiently be employed to provide a runtime system including memory management (MM) that is specifically suited to an embedded application on a particular hardware device. In the context of this paper, we present novel memory-management strategy we implemented in our KESO JVM. It is a latency-aware garbage-collection algorithm called LAGC. Also, we introduce the static analyses that can assist LAGC. The application developers have to ensure that there is enough time for the GCs to run. Hardware characteristics such as soft-error proneness of the hardware or the memory layout can also be taken into consideration as demanded by the system configuration. This is achieved by integrating the GCs in the design process of the whole system just as any other user application, which is the reason why this approach is called cooperative memory management. The suggested strategies require reasonably low overhead.

关键词： Memory management Runtime Hardware Java embedded systems Random access memory Resource management

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cases'12 - Proceedings of the 2012 ACM international conference on compilers, architectures and synthesis for embedded systems, Co-located with ESWEEK

CASES'12 - Proceedings of the 2012 ACM International Confere...

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2012 ACM international conference on compilers, architectures and synthesis for embedded systems, cases 2012, Co-located with 8th embedded systems Week, ESWEEK 2012

ISBN: (纸本)9781450314244

The proceedings contain 23 papers. The topics discussed include: side channel attacks and the non volatile memory of the future;a cost-effective tag design for memory data authentication in embedded systems;static secure page allocation for light-weight dynamic information flow tracking;a hybrid just-in-time compiler for Android: comparing JIT types and the result of cooperation;power agnostic technique for efficient temperature estimation of multicore embedded systems;scenario-based design flow for mapping streaming applications onto on-chip many-core systems;the RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems;function inlining and loop unrolling for loop acceleration in reconfigurable processors;energy efficient hybrid display and predictive models for embedded and mobile systems;and energy efficient special instruction support in an embedded processor with compact ISA.

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Automatic extraction of pipeline parallelism for embedded heterogeneous multi-core platforms

Automatic extraction of pipeline parallelism for embedded he...

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2013 international conference on compilers, architecture and synthesis for embedded systems, cases 2013

作者： Cordes, Daniel Engel, Michael Neugebauer, Olaf Marwedel, Peter TU Dortmund University Dortmund Germany

ISBN: (纸本)9781479914005

Automatic parallelization of sequential applications is the key for efficient use and optimization of current and future embedded multi-core systems. However, existing approaches often fail to achieve efficient balancing of tasks running on heterogeneous cores of an MPSoC. A reason for this is often insufficient knowledge of the underlying architecture's performance. In this paper, we present a novel parallelization approach for embedded MPSoCs that combines pipeline parallelization for loops with knowledge about different execution times for tasks on cores with different performance properties. Using Integer Linear Programming, an optimal solution with respect to the model used is derived implementing tasks with a well-balanced execution behavior. We evaluate our pipeline parallelization approach for heterogeneous MPSoCs using a set of standard embedded benchmarks and compare it with two existing state-of-the-art approaches. For all benchmarks, our parallelization approach obtains significantly higher speedups than either approach on heterogeneous MPSoCs. © 2013 IEEE.

关键词： Pipelines

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From software to accelerators with LegUp high-level synthesis

From software to accelerators with LegUp high-level synthesi...

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2013 international conference on compilers, architecture and synthesis for embedded systems, cases 2013

作者： Canis, Andrew Choi, Jongsok Fort, Blair Lian, Ruolong Huang, Qijing Calagar, Nazanin Gort, Marcel Qin, Jia Jun Aldham, Mark Czajkowski, Tomasz Brown, Stephen Anderson, Jason ECE Department University of Toronto Toronto ON Canada

ISBN: (纸本)9781479914005

embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support. © 2013 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Platform-dependent code generation for embedded real-time software

Platform-dependent code generation for embedded real-time so...

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2013 international conference on compilers, architecture and synthesis for embedded systems, cases 2013

作者： Kim, BaekGyu Phan, Linh T. X. Sokolsky, Oleg Lee, Lnsup University of Pennsylvania United States

ISBN: (纸本)9781479914005

Code generation for embedded systems is challenging, since the generated code (e.g., C code) is expected to run on a heterogeneous set of target platforms with different characteristics, such as hardware/software architectures and programming interfaces. We propose a code generation framework that provides the flexibility to generate different source code that is executable on each target platform. In our framework, the platform-dependent characteristics of a target platform are explicitly specified by an Architectural Analysis Description Language (AADL) model and a code snippet repository. The AADL model captures hardware/software architectural aspects of the platform, such as periodic/aperiodic threads and their interactions with sensors and actuators. The code snippet repository contains platform-dependent code snippets that are categorized according to the functions required to implement the components of the AADL model. These two elements of the platform capability are then used by the code generation algorithm to generate platform-dependent code for the given platform. We demonstrate the applicability of our framework using a case study of code generation for two infusion pump systems. © 2013 IEEE.

关键词： embedded systems

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