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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是141-150 订阅

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Specification and synthesis of real-time embedded distributed and parallel multiprocessor-based signal processing systems

Specification and synthesis of real-time embedded distribute...

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Janka, Randall S. Wills, Linda M. Cadence Design Systems Inc. 1117 Perimeter Center West Atlanta GA 30338 United States Sch. of Elec./Computer Engineering Georgia Institute of Technology Atlanta GA 30332-0250 United States

ISBN: (纸本)1581133383

The codesign of embedded real-time signal processing systems is complex. In certain application domains requiring high computational throughput, this complexity is due to the need to employing parallel processing and perhaps using heterogeneous processors. The use of commercial-off-the-shelf (COTS) multiprocessor (MP) hardware and software can reduce codesign complexity. Further complexity reduction can be obtained with emerging synthesis frameworks, which can generate deployable code by leveraging vendor communication and computation libraries. However, these synthesis frameworks are inadequate in providing a sound specification and design methodology (SDM) because they require the designer to first choose the implementation target before specification and design exploration. We have developed a new SDM known as MAGIC that allows the designer to capture the specification in an executable model that can then be used in design exploration to find the optimal COTS MP technology and architecture before committing to that technology. The MAGIC SDM exploits emerging open-standards based VSIPL computation middleware and MPI communication middleware to provide connectivity between specification and design with synthesis frameworks for implementation. This SDM is also shown to be applicable to the system-on-chip (SOC) domain, especially as embodied in a new framework called Virtual Component Co-design from Cadence Design systems.

关键词： Signal processing

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A Cost-Effective Tag Design for Memory Data Authentication in embedded systems

A Cost-Effective Tag Design for Memory Data Authentication i...

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ACM international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Hong, Mei Guo, Hui Hu, X. Sharon Univ New S Wales Sch Comp Sci & Engn Sydney NSW 2052 Australia

ISBN: (纸本)9781450314244

This paper presents a tag design approach for memory data integrity protection. The approach is area, power and memory efficient, suitable to embedded systems that often suffer from stringent resource restriction. Experiments have been performed to compare the proposed approach with the state-of-the-art designs, which demonstrate that the approach can produce a memory data protection design with a low resource cost - achieving overhead savings of about 39% on chip area, 45% on power consumption, 65% on performance, and 12% on memory cost while maintaining the same or higher security level.

关键词： tag design memory data authentication low on-chip cost embedded systems

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Application driven embedded system design: A face recognition case study

Application driven embedded system design: A face recognitio...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Ramani, Karthik Davis, Al School of Computing University of Utah Salt Lake City UT 84112 United States

ISBN: (纸本)9781595938268

The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core specialization has been employed in the embedded space and is likely to play an important role in future heterogeneous multi-core architectures as well. In this paper, the face recognition application domain is employed as a case study to showcase an architectural design methodology which generates a specialized core with high performance and very low powercharacteristics. Specifically, we create "ASIC-like" execution flows to sustain the high memory parallelism generated within the core. The price of this benefit is a significant increase in compilation complexity. The crux of the problem is the need to co-schedule the often conflicting constraints of data access, data movement, and computation. A modular compiler approach that employs integer linear programming (ILP) based "interconnect- aware" instruction and data scheduling techniques to solve this problem is then described. The resulting core running the compiled code delivers a 1.65x throughput improvement over a high performance processor (Pentium 4) while simultaneously achieving an 80x energy-delay improvement over an energy-efficient processor (XScale) and performs real-time face recognition at embedded power budgets. Copyright 2007 ACM.

关键词： embedded systems

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General loop fusion technique for nested loops considering timing and code size

General loop fusion technique for nested loops considering t...

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Liu, Meilin Zhuge, Qingfeng Shao, Zili Sha, Edwin H.-M. Department of Computer Science University of Texas at Dallas Richardson TX 75083 United States

ISBN: (纸本)1581138903

Loop fusion is commonly used to improve the instruction-level parallelism of loops for high-performance embedded computing systems. Loop fusion, however, is not always directly applicable because the fusion prevention dependencies may exist among loops. Most of the existing techniques still have limitations in fully exploiting the advantages of loop fusion, In this paper, we present a general loop fusion technique for loops or nested loops based on the loop dependency graph model, retiming, and multi-dimensional retiming concepts. We show that any "J+K" model loop can be legally fused using our legalizing fusion technique. Polynomial-time algorithms are developed to solve the loop fusion problem for "J+K" model loops considering both timing and code size of the final code. Our technique produces the final code and calculates the resultant code size directly from the retiming values. The experimental results show that our loop fusion technique always significantly reduces the schedule length. Copyright 2004 ACM.

关键词： embedded systems

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Work-in-Progress: DAPHNE - An Automotive Benchmark Suite for Parallel Programming Models on embedded Heterogeneous Platforms

Work-in-Progress: DAPHNE - An Automotive Benchmark Suite for...

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embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Sommer, Lukas Stock, Florian Solis-Vasquez, Leonardo Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany

ISBN: (纸本)9781450369244

Due to the ever-increasing computational demand of automotive applications, and in particular autonomous driving capabilities, the automotive industry and its suppliers are starting to adopt parallel and heterogeneous embedded computing platforms. However, C and C++, the currently dominating programming languages in this industry, do not provide sufficient mechanisms to fully exploit such platforms. As a result, vendors have begun to employ true parallel programming models such as OpenMP, CUDA or OpenCL. In this work, we report on a benchmark suite developed specifically to investigate the applicability of established parallel programming models to automotive workloads on heterogeneous platforms.

关键词： Automotive industry

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Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems

Eliminating inter-process cache interference through cache r...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Reddy, Rakesh Petrov, Peter University of Maryland College Park United States

ISBN: (纸本)9781595938268

We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to provide the required memory bandwidth. However, caches introduce two important problems for embedded systems. Cache outcomes in multi-tasking environments are notoriously difficult to predict, if not impossible, thus resulting in poor real-time guarantees. Additionally, caches contribute to a significant amount of power. These issues are key factors for many embedded systems. We study the effect of multiple tasks on the data cache, and propose a technique which leverages configurable cache architectures to eliminate inter-task cache interference. By mapping tasks to different cache partitions, interference is completely eliminated with only a minimal impact on performance. Furthermore, dynamic and leakage power are significantly reduced as only a subset of the cache is active at any moment. We introduce a profile-based, static analysis algorithm, which identifies a beneficial cache partitioning. The OS configures the data cache during context-switch by activating the corresponding *** experiments on a large set of multitasking benchmarks demonstrate that our technique not only efficiently eliminates inter-task interference but also significantly reduces both dynamic and leakage power. Copyright 2007 ACM.

关键词： embedded systems

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Virtual Multiprocessor: An analyzable, high-performance microarchitecture for real-time computing

Virtual Multiprocessor: An analyzable, high-performance micr...

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： El-Haj-Mahmoud, Ali Al-Zawawi, Ahmed S. Anantaraman, Aravindh Rotenberg, Eric Department of Electrical and Computer Engineering Center for Embedded Systems Research North Carolina State University Raleigh NC 27695

ISBN: (纸本)159593149X

The design of a real-time architecture is governed by a trade-off between analyzability necessary for real-time formalism and performance demanded by high-end embedded systems. We reconcile this trade-off with a novel Real-time Virtual Multiprocessor (RVMP). RVMP virtualizes a single in-order superscalar processor into multiple interference-free different-sized virtual processors. This provides a flexible spatial dimension, In the time dimension, the number and size of virtual processors can be rapidly reconfigured. A simple real-time scheduling approach concentrates scheduling within a small time interval, producing a simple repeating space/time schedule that orchestrates virtualization. RVMP successfully combines the analyzability (hence real-time formalism) of multiple processors with the flexibility (hence high performance) of simultaneous multithreading (SMT). Worst-case schedulability experiments show that more task-sets are provably schedulable on RVMP than on conventional rigid multiprocessors with equal aggregate resources, and the advantage only intensifies with more demanding task-sets. Run-time experiments show RVMP's statically-controlled coarser-grain space/time configurability is as effective as unsafe SMT. Moreover, RVMP provides a real-time formalism that SMT does not currently provide. Copyright 2005 ACM.

关键词： Computer architecture

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Equivalence Checking of Arithmetic Expressions using Fast Evaluation

Equivalence Checking of Arithmetic Expressions using Fast Ev...

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Ghodrat, Mohammad Ali Givargis, Tony Nicolau, Alex Department of Computer Science Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)159593149X

Arithmetic expressions are the fundamental building blocks of hardware and software systems. An important problem in computational theory is to decide if two arithmetic expressions are equivalent. However, the general problem of equivalence checking, in digital computers, belongs to the NP Hard class of problems. Moreover, existing general techniques for solving this decision problem are applicable to very simple expressions and impractical when applied to more complex expressions found in programs written in high-level languages. In this paper we propose a method for solving;the arithmetic expression equivalence problem using partial evaluation. In particular, our technique is specifically designed to solve the problem of equivalence checking of arithmetic expressions obtained from high-level language descriptions of hardware/software systems, which consists of regular arithmetic operators (+, -, x) and logical operators (and, or, not). In our method, we use interval analysis to substantially prune the domain space of arithmetic expressions and limit the evaluation effort to a sufficiently limited set of subspaces. Our results show that the proposed method is fast enough to be of use in practice. Copyright 2005 ACM.

关键词： Digital arithmetic

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Thrifty-malloc: A HW/SW Codesign for the Dynamic Management of Hardware Transactional Memory in embedded Multicore systems

Thrifty-malloc: A HW/SW Codesign for the Dynamic Management ...

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international conference on Compliers, architectures, and synthesis of embedded systems (cases)

作者： Carle, Thomas Papagiannopoulou, Dimitra Moreshet, Tali Marongiu, Andrea Herlihy, Maurice Bahar, R. Iris Brown Univ Providence RI 02912 USA Boston Univ Boston MA 02215 USA Univ Bologna Bologna Italy Univ Toulouse Toulouse France

ISBN: (纸本)9781450344821

We present thrifty-malloc: a transaction-friendly dynamic memory manager for high-end embedded multicore systems. The manager combines modularity, ease-of-use and hardware transactional memory (HTM) compatibility in a lightweight and memory-efficient design. Thrifty-malloc is easy to deploy and configure for non-expert programmers, yet provides good performance with low memory overhead for highly-parallel embedded applications running on massively parallel processor arrays (MPPAs) or many-core architectures. In addition, the transparent mechanisms that increase our manager's resilience to unpredictable dynamic situations incur a low timing overhead in comparison to established techniques.

关键词： Managers

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Tutorial: Designing an Edge Inferencing Accelerator with High-Level synthesis

Tutorial: Designing an Edge Inferencing Accelerator with Hig...

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2023 international conference on compilers, architecture, and synthesis for embedded systems, cases 2023

作者： Klein, Russell Solanti, Petri Siemens WilsonvilleOR United States Siemens Munich Germany

ISBN: (纸本)9798400702907

Convolutional neural networks are computationally intensive. A single inference can require billions of multiply/accumulate operations. In the datacenter, where ample power, space, and cooling are available, high powered CPUs or GPUs can be used. However, in the embedded space, edge systems often do not have the power or compute capability to perform these calculations. Further, edge applications often have hard real-Time requirements. This combination necessitates the use of hardware accelerators for performing inferencing calculations. A bespoke accelerator will deliver the highest performance and efficiency, outperforming configurable IP by an order of magnitude or more. But transforming an algorithm developed in a machine learning framework, often in Python, into silicon can be a daunting task. Traditional hardware design is performed at the register transfer level (RTL). When designing in RTL, hardware engineers describe every register, every operator, and every connection in the design. At this level of detail, it is impractical for the designer to explore significantly different implementation architectures. High-Level synthesis (HLS) allows a hardware engineer to operate at a higher level of abstraction-specifically, at the algorithmic level-and use the facilities of the HLS tool to automate the conversion of the algorithm description into synthesizable RTL. This enables a broad set of architectures to be created and evaluated. And at the algorithmic level, the description of the hardware is much closer to the original Python, making the conversion faster, easier, and more natural. © 2023 ACM.

关键词： High level synthesis

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