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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

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Sustaining Moore's law in embedded computing through probabilistic and approximate design: Retrospects and prospects

Sustaining Moore's law in embedded computing through probabi...

引用

embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Palem, Krishna V. Chakrapani, Lakshmi N.B. Kedem, Zvi M. Lingamneni, Avinash Muntimadugu, Kirthi Krishna VISEN Center Rice University Houston TX United States Courant Institute of Mathematical Sciences New York University New York NY United States

ISBN: (纸本)9781605586267

The central theme of our work is the probabilistic and approximate design of embedded computing systems. This novel approach consists of two distinguishing aspects: (i) the design and implementation of embedded systems, using components which are susceptible to perturbations from various sources and (ii) a design methodology which consists of an exploration of a design space which characterizes the trade-off between quality of output and cost, to implement high performance and low energy embedded systems. In contrast with other work, our design methodology does not attempt to correct the errors introduced by components which are susceptible to perturbations, instead we design "good enough" systems. Our work has the potential to address challenges and impediments to Moore's law arising from material properties and manufacturing difficulties, which dictate that we shift from the current-day deterministic design paradigm to statistical and probabilistic designs of the future. In this paper, we provide a broad overview of our work on probabilistic and approximate design, present novel results in approximate arithmetic and its impact on digital signal processing algorithms, and sketch future directions for research. Copyright 2009 ACM.

关键词： embedded systems

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Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Multiple sleep mode leakage control for cache peripheral cir...

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Homayoun, Houman Makhzan, Mohammad Veidenbaum, Alex Center for Embedded Computer Systems University of California Irvine CA United States Department of Electrical and Computer Engineering University of California Irvine CA United States

ISBN: (纸本)9781605584690

This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral circuits, which according to recent studies account for a considerable amount of cache leakage. At circuit level, we propose a novel design with multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and wakeup delay. Architectural control is proposed to decide "when and how" to use these different low-leakage modes using cache miss information to guide its action. This control is based on simple state machines that do not impact area or power consumption and can thus be used even in the resource constrained processors. Experimental results indicate that proposed techniques can keep the L1 cache peripherals in one of the low-power modes for more than 85% of total execution time, on average. This translates to an average leakage power reduction of 50% for 65nm technology. The DL1 cache energy-delay product is reduced, on average, by 20%. Copyright 2008 ACM.

关键词： Timing circuits

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Bit section instruction set extension of ARM for embedded applications

Bit section instruction set extension of ARM for embedded ap...

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2002 international conference on compilers, architecture, and synthesis for embedded systems, cases '02

作者： Li, Bengu Gupta, Rajiv Department of Computer Science University of Arizona Tucson AZ 85721 United States

ISBN: (纸本)1581135750

Programs that manipulate data at subword level, i.e. bit sections within a word, are common place in the embedded domain. Examples of such applications include media processing as well as network processing codes. These applications spend significant amounts of time packing and unpacking narrow width data into memory words. The execution time and memory overhead of packing and unpacking operations can be greatly reduced by providing direct instruction set support for manipulating bit sections. In this paper we present the Bit Section eXtension (BSX) to the ARM instruction set. We selected the ARM processor for this research because it is one of the most popular embedded processor which is also being used as the basis of building many commercial network processing architectures. We present the design of BSX instructions and their encoding into the ARM instruction set. We have incorporated the implementation of BSX into the Simplescalar ARM simulator from Michigan. Results of experiments with programs from various benchmark suites show that by using BSX instructions the total number of instructions executed at runtime by many transformed functions are reduced by 4.26% to 27.27% and their code sizes are reduced by 1.27% to 21.05%. Copyright 2002 ACM.

关键词： ARM processors

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Vector Class on Limited Local Memory (LLM) Multi-core Processors

Vector Class on Limited Local Memory (LLM) Multi-core Proces...

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14th Confernece on compilers, architectures and synthesis for embedded systems (cases)

作者： Bai, Ke Lu, Di Shrivastava, Aviral Arizona State Univ Compiler Microarchitecture Lab Tempe AZ 85281 USA

ISBN: (纸本)9781450307130

Limited Local Memory (LLM) multi-core architecture is a promising solution for scalable memory hierarchy. LLM architecture, e.g., IBM Cell/B.E. is a purely distributed memory architecture in which each core can directly access only its small local memory, and that is why it is extremely power efficient. Vector is a popular container class in the C++ Standard Template Library (STL), which provides the functionality similar to a dynamic array. Due to the small non-virtualized memory in the LLM architecture, vector library implementation cannot be used as it is. In this paper, we propose and implement a scheme to manage vector class in the local memory present in each core of LLM multi-core architecture. Our scalable solution can transparently maintain vector data between the shared global memory and the local memories. In addition, different data transfer granularities are provided by our vector class to achieve better performance. We also propose a mechanism to ensure the validity of pointers-to-elements when the vector elements are moved into the global memory. Experimental result shows that our vector class can improve the programmability of vector class significantly while the overhead can be contained within 7%.

关键词： Vector local memory scratch pad memory embedded system multi-core processor IBM Cell PS3 MPI

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E 2: Less energy through multi-copy cache

E 2: Less energy through multi-copy cache

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6th embedded systems Week 2010, ESWEEK 2010 - 2010 international conference on compilers, architecture, and synthesis for embedded systems, cases'10

作者： Chakraborty, Arup Homayoun, Houman Khajeh, Amin Dutt, Nikil Eltawil, Ahmed Kurdahi, Fadi Center for Embedded Computer Systems University of California Irvine CA United States

ISBN: (纸本)9781605589039

Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation-induced failures in cache SRAM arrays, which compromise cache reliability. We present Multi-Copy Cache (MC2), a new cache architecture that achieves significant reduction in energy consumption through aggressive voltage scaling, while maintaining high error resilience (reliability) by exploiting multiple copies of each data item in the cache. Unlike many previous approaches, MC2 does not require any error map characterization and therefore is responsive to changing operating conditions (e.g., Vdd-noise, temperature and leakage) of the cache. MC2 also incurs significantly lower overheads compared to other ECC-based caches. Our experimental results on embedded benchmarks demonstrate that MC2 achieves up to 60% reduction in energy and energy-delay product (EDP) with only 3.5% reduction in IPC and no appreciable area overhead.

关键词： Fault tolerance

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System-Level Modeling and synthesis of Flow-Based Microfluidic Biochips

System-Level Modeling and Synthesis of Flow-Based Microfluid...

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14th conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Minhass, Wajid Hassan Pop, Paul Madsen, Jan Tech Univ Denmark DTU Informat DK-2800 Lyngby Denmark

ISBN: (纸本)9781450307130

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. There are several types of microfluidic biochips, each having its advantages and limitations. In this paper we are interested in flow-based biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. Although researchers have proposed significant work on the system-level synthesis of droplet-based biochips, which manipulate droplets on a two-dimensional array of electrodes, no research on system-level synthesis of flow-based biochips has been reported so far. The focus has been on application modeling and component-level simulation. Therefore, for the first time to our knowledge, we propose a system-level modeling and synthesis approach for flow-based biochips. We have developed a topology graph-based model of the biochip architecture, and we have used a sequencing graph to model the biochemical applications. We consider that the architecture of the biochip is given, and we are interested to synthesize an implementation, consisting of the binding of operations in the application to the functional units of the architecture, the scheduling of operations and the routing and scheduling of the fluid flows, such that the application completion time is minimized. We propose a List Scheduling-based heuristic for solving this problem. The proposed heuristic has been evaluated using two real-life case studies and a set of four synthetic benchmarks.

关键词： Microfluidics biochips modeling synthesis

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Software controlled memory layout reorganization for irregular array access patterns

Software controlled memory layout reorganization for irregul...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Cho, Doosan Issenin, Ilya Dutt, Nikil Yoon, Jonghee W. Paek, Yunheung School of EECS Seoul National University Center for Embedded Computer Systems University of California Irvine CA 92697

ISBN: (纸本)9781595938268

Many embedded array-intensive applications have irregular access patterns that are not amenable to static analysis for extraction of access patterns, and thus prevent efficient use of a Scratch Pad Memory (SPM) hierarchy for performance and power improvement. We present a profiling based strategy that generates a memory access trace which can be used to identify data elements with fine granularity that can profitably be placed in the SPMs to maximize performance and energy gains. We developed an entire toolchain that allows incorporation of the code required to profitably move data to SPMs;visualization of the extracted access pattern after profiling;and evaluation/exploration of the generated application code to steer mapping of data to the SPM to yield performance and energy *** present a heuristic approach that efficiently exploits the SPM using the profiler-driven access pattern behaviors. Experimental results on EEMBC and other industrial codes obtained with our framework show that we are able to achieve 36% energy reduction and reduce execution time by up to 22% compared to a cache based system. Copyright 2007 ACM.

关键词： Computer software

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Encryption overhead in embedded systems and sensor network nodes: Modeling and analysis

Encryption overhead in embedded systems and sensor network n...

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cases 2003: international conference on compilers, architecture, and synthesis for embedded systems

作者： Venugopalan, Ramnath Ganesan, Prasanth Peddabachagari, Pushkin Dean, Alexander Mueller, Frank Sichitiu, Mihail Center for Embedded Systems Research Depts. of ECE and CS North Carolina State University Raleigh NC 27695

ISBN: (纸本)1581136765

Recent research in sensor networks has raised issues of security for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices in the field. Limitations in processing power, battery life, communication bandwidth and memory constrain the applicability of existing cryptography standards for small embedded devices. A mismatch between wide arithmetic for security (32 bit word operations) and embedded data bus widths (often only 8 or 16 bits) combined with lack of certain operations (e.g., multiply) in the ISA present other challenges. This paper offers two contributions. First, a survey investigating the computational requirements for e a number of common cryptographic algorithms and embedded architectures is presented. The objective of this work is to cover a wide class of commonly used encryption algorithms and to determine the impact of embedded architectures on their performance. This will help designers predict a system's performance for cryptographic tasks. Second, methods to derive the computational overhead of embedded architectures in general for encryption algorithms are developed. This allows one to project computational limitations and determine the threshold of feasible encryption schemes under a set of the constraints for an embedded architecture. Experimental measurements indicate uniform cryptographic cost for each encryption class and each architecture class and negligible impact of caches. RC4 is shown to outperform RC5 for the Atmega platform. But when message authentication is required in addition to encryption, hash or block ciphers, such as RC5, have the advantage of providing support for both authentication and encryption. The analytical model allows to assess the impact of arbitrary embedded architectures as a multi-variant function for each encryption scheme. Overall, our results are not only valuable to assess the feasibility of encryption schemes for existing embedded architectures, they als

关键词： embedded systems

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Self-powered wearable sensor platforms for wellness

Self-powered wearable sensor platforms for wellness

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international conference on compilers, architecture and synthesis for embedded systems, cases 2015

作者： Misra, Veena Calhoun, Ben Bhansali, Shekhar Lach, John Datta, Suman Ozturk, Mehmet Bozkurt, Alper Oralkan, Omer Strohmaier, Jason Department of ECE North Carolina State Univ. United States Department of ECE University of Virginia United States Department of ECE Florida International University United States Department of EE Pennsylvania State University United States Department of ECE Bilkent University Ankara Turkey

ISBN: (纸本)9781467383202

Health care continues to be one of the biggest challenges facing our society. Factors such as lifestyle choices, genetics, aging, stress and environmental exposures play a critical role in determining health outcomes. Wearable technologies that can enable continuous/long-term personal health monitoring and personal environmental monitoring can empower users to make better lifestyle decisions and improve health outcomes. While wearable devices promise a compelling future of achieving wellness, current wearable products are not addressing the needs of the health space. To achieve this future, key challenges in wearable systems such as battery life, form factor, sensor functionality, configurability and data analysis will have to be carefully addressed to ensure user adoption and effectively manage health. © 2015 IEEE.

关键词： Energy harvesting

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Architectural synthesis of Flow-Based Microfluidic Large-Scale Integration Biochips

Architectural Synthesis of Flow-Based Microfluidic Large-Sca...

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ACM international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Minhass, Wajid Hassan Pop, Paul Madsen, Jan Blaga, Felician Stefan Tech Univ Denmark DTU Informat DK-2800 Lyngby Denmark

ISBN: (纸本)9781450314244

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. In this paper we are interested in flow-based biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. The manufacturing technology, soft lithography, used for the flow-based biochips is advancing faster than Moore's law, resulting in increased architectural complexity. However, the designers are still using full-custom and bottom-up, manual techniques in order to design and implement these chips. As the chips become larger and the applications become more complex, the manual methodologies will not scale, becoming highly inadequate. Therefore, for the first time to our knowledge,we propose a top-down architectural synthesis methodology for the flow-based biochips. Starting from a given biochemical application and a microfluidic component library, we are interested in synthesizing a biochip architecture, i.e., performing component allocation from the library based on the biochemical application, generating the biochip schematic (netlist) and then performing physical synthesis (deciding the placement of the microfluidic components on the chip and performing routing of the microfluidic channels), such that the application completion time is minimized. We evaluate our proposed approach by synthesizing architectures for real-life applications as well as synthetic benchmarks.

关键词： microfluidic biochips architecture synthesis flow-based

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