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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

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Vector Class on Limited Local Memory (LLM) Multi-core Processors

Vector Class on Limited Local Memory (LLM) Multi-core Proces...

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14th Confernece on compilers, architectures and synthesis for embedded systems (cases)

作者： Bai, Ke Lu, Di Shrivastava, Aviral Arizona State Univ Compiler Microarchitecture Lab Tempe AZ 85281 USA

ISBN: (纸本)9781450307130

Limited Local Memory (LLM) multi-core architecture is a promising solution for scalable memory hierarchy. LLM architecture, e.g., IBM Cell/B.E. is a purely distributed memory architecture in which each core can directly access only its small local memory, and that is why it is extremely power efficient. Vector is a popular container class in the C++ Standard Template Library (STL), which provides the functionality similar to a dynamic array. Due to the small non-virtualized memory in the LLM architecture, vector library implementation cannot be used as it is. In this paper, we propose and implement a scheme to manage vector class in the local memory present in each core of LLM multi-core architecture. Our scalable solution can transparently maintain vector data between the shared global memory and the local memories. In addition, different data transfer granularities are provided by our vector class to achieve better performance. We also propose a mechanism to ensure the validity of pointers-to-elements when the vector elements are moved into the global memory. Experimental result shows that our vector class can improve the programmability of vector class significantly while the overhead can be contained within 7%.

关键词： Vector local memory scratch pad memory embedded system multi-core processor IBM Cell PS3 MPI

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The performance and energy consumption of three embedded real-time operating systems 2

The performance and energy consumption of three embedded rea...

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Baynes, Kathleen Collins, Chris Fiterman, Eric Ganesh, Brinda Kohout, Paul Smit, Christine Zhang, Tiebing Jacob, Bruce Dept. of Electrical and Computer Engineering University of Maryland at College Park College ParkMD20742 United States

ISBN: (纸本)1581133995

This paper presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs by executing them on an accurate architectural model of a microcontroller with simulated real-time stimuli. We briefly describe the simulation environment and present a study that compares three RTOSs: μC/OS-II, a popular public-domain embedded real-time operating system;Echidna, a sophisticated, industrial-strength (commercial) RTOS;and NOS, a bare-bones multi-rate task scheduler reminiscent of typical "roll-your-own" RTOSs found in many commercial embedded systems. The microcontroller simulated in this study is the Motorola M-CORE processor: a low-power, 32-bit CPU core with 16-bit instructions, running at 20MHz. Copyright 2001 ACM.

关键词： Microcontrollers

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System-Level Modeling and synthesis of Flow-Based Microfluidic Biochips

System-Level Modeling and Synthesis of Flow-Based Microfluid...

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14th conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Minhass, Wajid Hassan Pop, Paul Madsen, Jan Tech Univ Denmark DTU Informat DK-2800 Lyngby Denmark

ISBN: (纸本)9781450307130

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. There are several types of microfluidic biochips, each having its advantages and limitations. In this paper we are interested in flow-based biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. Although researchers have proposed significant work on the system-level synthesis of droplet-based biochips, which manipulate droplets on a two-dimensional array of electrodes, no research on system-level synthesis of flow-based biochips has been reported so far. The focus has been on application modeling and component-level simulation. Therefore, for the first time to our knowledge, we propose a system-level modeling and synthesis approach for flow-based biochips. We have developed a topology graph-based model of the biochip architecture, and we have used a sequencing graph to model the biochemical applications. We consider that the architecture of the biochip is given, and we are interested to synthesize an implementation, consisting of the binding of operations in the application to the functional units of the architecture, the scheduling of operations and the routing and scheduling of the fluid flows, such that the application completion time is minimized. We propose a List Scheduling-based heuristic for solving this problem. The proposed heuristic has been evaluated using two real-life case studies and a set of four synthetic benchmarks.

关键词： Microfluidics biochips modeling synthesis

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Encryption overhead in embedded systems and sensor network nodes: Modeling and analysis

Encryption overhead in embedded systems and sensor network n...

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cases 2003: international conference on compilers, architecture, and synthesis for embedded systems

作者： Venugopalan, Ramnath Ganesan, Prasanth Peddabachagari, Pushkin Dean, Alexander Mueller, Frank Sichitiu, Mihail Center for Embedded Systems Research Depts. of ECE and CS North Carolina State University Raleigh NC 27695

ISBN: (纸本)1581136765

Recent research in sensor networks has raised issues of security for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices in the field. Limitations in processing power, battery life, communication bandwidth and memory constrain the applicability of existing cryptography standards for small embedded devices. A mismatch between wide arithmetic for security (32 bit word operations) and embedded data bus widths (often only 8 or 16 bits) combined with lack of certain operations (e.g., multiply) in the ISA present other challenges. This paper offers two contributions. First, a survey investigating the computational requirements for e a number of common cryptographic algorithms and embedded architectures is presented. The objective of this work is to cover a wide class of commonly used encryption algorithms and to determine the impact of embedded architectures on their performance. This will help designers predict a system's performance for cryptographic tasks. Second, methods to derive the computational overhead of embedded architectures in general for encryption algorithms are developed. This allows one to project computational limitations and determine the threshold of feasible encryption schemes under a set of the constraints for an embedded architecture. Experimental measurements indicate uniform cryptographic cost for each encryption class and each architecture class and negligible impact of caches. RC4 is shown to outperform RC5 for the Atmega platform. But when message authentication is required in addition to encryption, hash or block ciphers, such as RC5, have the advantage of providing support for both authentication and encryption. The analytical model allows to assess the impact of arbitrary embedded architectures as a multi-variant function for each encryption scheme. Overall, our results are not only valuable to assess the feasibility of encryption schemes for existing embedded architectures, they als

关键词： embedded systems

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A group-based wear-leveling algorithm for large-capacity flash memory storage systems

A group-based wear-leveling algorithm for large-capacity fla...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Jung, Dawoon Chae, Yoon-Hee Jo, Heeseung Kim, Jin-Soo Lee, Joonwon 335 Gwahangno Yuseong-gu Daejeon 305-701 Korea Republic of

ISBN: (纸本)9781595938268

Although NAND flash memory has become one of the most popular storage media for portable devices, it has a serious problem with respect to lifetime. Each block of NAND flash memory has a limited number of program/erase cycles, usually 10,000-100,000, and data in a block become unreliable after the limit. For this reason, distributing erase operations evenly across the whole flash memory media is an important concern in designing flash memory storage *** this paper, we propose a memory-efficient group-based wear-leveling algorithm. Our group-based algorithm achieves a small memory footprint by grouping several logically sequential blocks and managing only the summary information for each group. We also propose an effective group summary structure and a method to reduce unnecessary wear-leveling operations in order to enhance the wear-leveling performance. The evaluation results show that our group-based algorithm consumes only 8.75% of memory space compared to the previous scheme that manages per-block information, while showing roughly the same wear-leveling performance. Copyright 2007 ACM.

关键词： embedded systems

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Work-in-Progress: Physics-Based Software Analysis for Safety-Critical embedded Applications

Work-in-Progress: Physics-Based Software Analysis for Safety...

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embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Goettlich, Philipp Reuss, Hans-Christian ETAS GmbH Stuttgart Germany Univ Stuttgart Stuttgart Germany

ISBN: (纸本)9781450369244

Physics-based software systems are a new trend in automotive feature and control implementation. They are used for modern applications in the context of automated driving and ADAS. Implementing physical models on critical embedded targets (for example electronic control systems) causes many safety related challenges, as they are far more complex than ordinary control algorithms. The code needs to be secured appropriately. This paper proposes a new approach to include physical properties in the V&V (verification & validation) and testing process in order to analyze functional code behavior of physical systems on targets automatically. For this, physical properties are extracted from the physics-based models, compared with databases and defined as constraints in order to analyze discretizations and calculations of the code. The mass conservation law for example is very beneficial for evaluating different discretization methods of model code automatically. This way, an evaluation of the correct behavior is faster, more efficient and safety and development time of physics-based embedded application code is improved. Our approach proved to be useful in finding physics-related errors in physics-based embedded systems automatically. The generated physical constraints can be used for test data generation.

关键词： Physical properties

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Architectural synthesis of Flow-Based Microfluidic Large-Scale Integration Biochips

Architectural Synthesis of Flow-Based Microfluidic Large-Sca...

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ACM international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Minhass, Wajid Hassan Pop, Paul Madsen, Jan Blaga, Felician Stefan Tech Univ Denmark DTU Informat DK-2800 Lyngby Denmark

ISBN: (纸本)9781450314244

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. In this paper we are interested in flow-based biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. The manufacturing technology, soft lithography, used for the flow-based biochips is advancing faster than Moore's law, resulting in increased architectural complexity. However, the designers are still using full-custom and bottom-up, manual techniques in order to design and implement these chips. As the chips become larger and the applications become more complex, the manual methodologies will not scale, becoming highly inadequate. Therefore, for the first time to our knowledge,we propose a top-down architectural synthesis methodology for the flow-based biochips. Starting from a given biochemical application and a microfluidic component library, we are interested in synthesizing a biochip architecture, i.e., performing component allocation from the library based on the biochemical application, generating the biochip schematic (netlist) and then performing physical synthesis (deciding the placement of the microfluidic components on the chip and performing routing of the microfluidic channels), such that the application completion time is minimized. We evaluate our proposed approach by synthesizing architectures for real-life applications as well as synthetic benchmarks.

关键词： microfluidic biochips architecture synthesis flow-based

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Hardware support for code integrity in embedded processors

Hardware support for code integrity in embedded processors

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Milenković, Milena Milenković, Aleksandar Jovanov, Emil WBI Performance II IBM Austin TX 78758 United States Electrical and Computer Engineering Department University of Alabama in Huntsville Huntsville AL 35899 United States

ISBN: (纸本)159593149X

Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increase, the applications running on these systems also grow in size and complexity, and so does the number of security vulnerabilities. Attacks that impair code integrity by injecting and executing malicious code are one of the major security issues. This problem can be addressed at different levels, from more secure software and operating systems, down to solutions that require hardware support. Most of the existing techniques tackle the problem of security flaws at the software level, but this approach lacks generality and often induces prohibitive overhead in performance and cost, or generates a significant number of false alarms. On the other hand, a further increase in the number of transistors on a single chip enables integrated hardware support for functions that formerly were restricted to the software domain. Hardware-supported defense techniques have the potential to be more general and more efficient than solely software solutions. This paper proposes four new architectural extensions to ensure complete run-time code integrity using instruction block signature verification. The experimental analysis shows that the proposed techniques have low performance and energy overhead. In addition, the proposed mechanism has low hardware complexity, and does not impose either changes to the compiler or changes to the existing instruction set architecture. Copyright 2005 ACM.

关键词： Microprocessor chips

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Power efficient encoding techniques for off-chip data buses

Power efficient encoding techniques for off-chip data buses

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cases 2003: international conference on compilers, architecture, and synthesis for embedded systems

作者： Suresh, Dinesh C. Agrawal, Banit Yang, Jun Najjar, Walid Bhuyan, Laxmi Computer Science and Engineering University of California Riverside CA 92521 United States

ISBN: (纸本)1581136765

Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as they consume a significant amount of total power. Since the bus power consumption is proportional to the switching activity, reducing the bus switching is an effective way to reduce bus power. While numerous techniques exist for reducing bus power in address buses, only a handful of techniques have been proposed for data-bus power reduction, where Frequent Value Encoding (FVE) is the best existing scheme to reduce the transition activity on the data buses. In this paper, we propose improved frequent value data-bus encoding techniques aimed at reducing more switching activity and hence, more power consumption. We propose three new schemes and five new variations to exploit bit-wise temporal and spatial locality in the data bus values. Our technique does not use additional external control signal and captures bit-wise locality to efficiently encode data values. For all the embedded and SPEC applications we tested, the overall average switching reduction is 53% over unencoded data and 11% more than the conventional FVE scheme. Copyright 2003 ACM.

关键词： embedded systems

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Anomalous path detection with hardware support

Anomalous path detection with hardware support

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Zhang, Tao Zhuang, Xiaotong Pande, Santosh Lee, Wenke College of Computing Georgia Institute of Technology Atlanta GA 30332-0280 United States

ISBN: (纸本)159593149X

embedded systems are being deployed as a part of critical infrastructures and are vulnerable to malicious attacks due to internet accessibility. Intrusion detection systems have been proposed to protect computer systems from unauthorized penetration. Detecting an attack early on pays off since further damage is avoided and in some cases, resilient recovery could be adopted. This is especially important for embedded systems deployed in critical infrastructures such as Power Grids etc. where a timely intervention could save catastrophes. An intrusion detection system monitors dynamic program behavior against normal program behavior and raises an alert when an anomaly is detected. The normal behavior is learnt by the system through training and profiling. However, all current intrusion detection systems are purely software based and thus suffer from large performance degradation due to constant monitoring operations inserted in application code. Due to the potential performance overheads, software based solutions cannot monitor program behavior at a very fine level of granularity, thus leaving potential security holes as shown in the literature. Another important drawback of such methods is that they are unable to detect intrusions in near real time and the time lag could prove disastrous in real time embedded systems. In this paper, we propose a hardware-based approach to verify program execution paths of target applications dynamically and to detect anomalous executions. With hardware support, our approach offers multiple advantages over software based solutions including minor performance degradation, much stronger detection capability (a larger variety of attacks get detected) and zero-latency reaction upon an anomaly for near real time detection and thus much better security. Copyright 2005 ACM.

关键词： embedded systems

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