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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

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A group-based wear-leveling algorithm for large-capacity flash memory storage systems

A group-based wear-leveling algorithm for large-capacity fla...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Jung, Dawoon Chae, Yoon-Hee Jo, Heeseung Kim, Jin-Soo Lee, Joonwon 335 Gwahangno Yuseong-gu Daejeon 305-701 Korea Republic of

ISBN: (纸本)9781595938268

Although NAND flash memory has become one of the most popular storage media for portable devices, it has a serious problem with respect to lifetime. Each block of NAND flash memory has a limited number of program/erase cycles, usually 10,000-100,000, and data in a block become unreliable after the limit. For this reason, distributing erase operations evenly across the whole flash memory media is an important concern in designing flash memory storage *** this paper, we propose a memory-efficient group-based wear-leveling algorithm. Our group-based algorithm achieves a small memory footprint by grouping several logically sequential blocks and managing only the summary information for each group. We also propose an effective group summary structure and a method to reduce unnecessary wear-leveling operations in order to enhance the wear-leveling performance. The evaluation results show that our group-based algorithm consumes only 8.75% of memory space compared to the previous scheme that manages per-block information, while showing roughly the same wear-leveling performance. Copyright 2007 ACM.

关键词： embedded systems

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Work-in-Progress: Physics-Based Software Analysis for Safety-Critical embedded Applications

Work-in-Progress: Physics-Based Software Analysis for Safety...

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embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Goettlich, Philipp Reuss, Hans-Christian ETAS GmbH Stuttgart Germany Univ Stuttgart Stuttgart Germany

ISBN: (纸本)9781450369244

Physics-based software systems are a new trend in automotive feature and control implementation. They are used for modern applications in the context of automated driving and ADAS. Implementing physical models on critical embedded targets (for example electronic control systems) causes many safety related challenges, as they are far more complex than ordinary control algorithms. The code needs to be secured appropriately. This paper proposes a new approach to include physical properties in the V&V (verification & validation) and testing process in order to analyze functional code behavior of physical systems on targets automatically. For this, physical properties are extracted from the physics-based models, compared with databases and defined as constraints in order to analyze discretizations and calculations of the code. The mass conservation law for example is very beneficial for evaluating different discretization methods of model code automatically. This way, an evaluation of the correct behavior is faster, more efficient and safety and development time of physics-based embedded application code is improved. Our approach proved to be useful in finding physics-related errors in physics-based embedded systems automatically. The generated physical constraints can be used for test data generation.

关键词： Physical properties

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Task-level timing models for guaranteed performance in multiprocessor networks-on-chip

Task-level timing models for guaranteed performance in multi...

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cases 2003: international conference on compilers, architecture, and synthesis for embedded systems

作者： Poplavko, P. Basten, T. Bekooij, M. Van Meerbergen, J. Mesman, B. Department of Electrical Engineering Eindhoven University of Technology P.O. Box 513 NL-5600 MB Eindhoven Netherlands Embedded Systems and Architectures on Silicon Philips Research Laboratories Eindhoven WDC 31 Prof. Holstlaan 4 NL-5656 AA Eindhoven Netherlands

ISBN: (纸本)1581136765

We consider a dynamic application running on a multiprocessor network-on-chip as a set of independent jobs, each job possibly running on multiple processors. To provide guaranteed quality and performance, the scheduling of jobs, jobs themselves and the hardware must be amenable to timing analysis. For a certain class of applications and multiprocessor architectures, we propose exact timing models that effectively co-model both the computation and communication of a job. The models are based on interprocessor communication (IPC) graphs [4]. Our main contribution is a precise model of network-on-chip communication, including buffer models. We use a JPEG-decoder job as an example to demonstrate that our models can be used in practice to derive upper bounds on the job execution time and to reason about optimal buffer sizes. Copyright 2003 ACM.

关键词： Interconnection networks

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Hardware support for code integrity in embedded processors

Hardware support for code integrity in embedded processors

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Milenković, Milena Milenković, Aleksandar Jovanov, Emil WBI Performance II IBM Austin TX 78758 United States Electrical and Computer Engineering Department University of Alabama in Huntsville Huntsville AL 35899 United States

ISBN: (纸本)159593149X

Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increase, the applications running on these systems also grow in size and complexity, and so does the number of security vulnerabilities. Attacks that impair code integrity by injecting and executing malicious code are one of the major security issues. This problem can be addressed at different levels, from more secure software and operating systems, down to solutions that require hardware support. Most of the existing techniques tackle the problem of security flaws at the software level, but this approach lacks generality and often induces prohibitive overhead in performance and cost, or generates a significant number of false alarms. On the other hand, a further increase in the number of transistors on a single chip enables integrated hardware support for functions that formerly were restricted to the software domain. Hardware-supported defense techniques have the potential to be more general and more efficient than solely software solutions. This paper proposes four new architectural extensions to ensure complete run-time code integrity using instruction block signature verification. The experimental analysis shows that the proposed techniques have low performance and energy overhead. In addition, the proposed mechanism has low hardware complexity, and does not impose either changes to the compiler or changes to the existing instruction set architecture. Copyright 2005 ACM.

关键词： Microprocessor chips

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Static program analysis of embedded executable assembly code

Static program analysis of embedded executable assembly code

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Venkitaraman, Ramakrishnan Gupta, Gopal Laboratory Department of Computer Science University of Texas Dallas United States

ISBN: (纸本)1581138903

We consider the problem of automatically checking if coding standards have been followed in the development of embedded applications. The problem arises from practical considerations because DSP chip manufacturers (in our case Texas Instruments) want various third party software developers to adhere to a certain coding standard to facilitate system integration during application development. Checking for compliance with coding standards, in general, is undecidable. Moreover, only machine code of the system components is available since for proprietary reasons vendors of various components do not want to share their source code. In this paper, we describe an approach based on static analysis of embedded assembly code to check for compliance with such coding standards. This static analysis rests on an abstract interpretation framework. We illustrate our approach by showing how we statically analyze the presence of hard-coded pointer variables in embedded assembly code. Hard coded pointer variables are those that are assigned a fixed memory address by the programmer instead of being assigned a value via proper operations in the source language (e.g., malloc/calloc/realloc and & operator in C). Our analyzer takes object code as input, disassembles it, builds the flow-graph, and statically analyzes the flow-graph for the presence of dereferenced pointers that are hard coded. The analyzer is currently being extended to check for compliance with other rules adopted by TI as part of its coding standards. Copyright 2004 ACM.

关键词： embedded systems

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Multi-granularity sampling for simulating concurrent heterogeneous applications

Multi-granularity sampling for simulating concurrent heterog...

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Tawk, Melhem Ibrahim, Khaled Z. Niar, Smail University of Valenciennes Hipeac Network of Excellence 59313 Valenciennes Cedex 9 France IRISA/INRIA Campus de Beaulieu 35042 Rennes France INRIA Lille-Nord-Europe Hipeac Network of Excellence 40 Avenue Halley 59650 Villeneuve d'ASCQ France

ISBN: (纸本)9781605584690

Detailed or cycle-accurate/bit-accurate (CABA) simulation is a critical phase in the design flow of embedded systems. However, with increasing system complexity, full detailed simulation is prohibitively slower than the hardware being simulated. In this paper, we present an approach that uses the sampling technique to speed up the design flow of Multiprocessor System-on-Chip (MPSoC) systems. Based on the dynamic behavior of the applications running concurrently, our method dynamically chooses between multiple granularities of the sampling phase. The similarities of the execution phases for all possible granularities are first analyzed, then transitions between phase overlaps are discretized. To facilitate the detection of repetitions, one phase, with an appropriate granularity, is chosen per process. Unlike most other proposals, the associated performance is usually accurate enough not to need repeated resampling. The use of checkpointing in conjunction with our approach is simplified because the amount of the needed disk space is significantly reduced. Experimental results show that the simulation of concurrent heterogeneous applications can be accelerated by a factor of up to 60x, while maintaining an average performance estimation error lower than 5%. Copyright 2008 ACM.

关键词： embedded systems

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Smart Cache Cleaning: Energy Efficient Vulnerability Reduction in embedded Processors

Smart Cache Cleaning: Energy Efficient Vulnerability Reducti...

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14th conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Jeyapaul, Reiley Shrivastava, Aviral Arizona State Univ Compiler Microarchitecture Lab Tempe AZ 85287 USA

ISBN: (纸本)9781450307130

Incessant and rapid technology scaling has brought us to a point where todays, and future transistors are susceptible to transient errors induced by energy carrying particles, called soft errors. Within a processor, the sheer size and nature of data in the caches render it most vulnerable to electrical interferences on static data in the cache. Data in the cache is vulnerable to corruption by soft errors, for the time it remains in the cache. Write-through and earlywrite- back [17] cache configurations reduce the time for vulnerable data in the cache, at the cost of increased memory writes and therefore energy. We propose a smart cache cleaning methodology, that enables copying of only specific vulnerable cache blocks into the memory at chosen times, thereby ensuring data cache protection with minimal memory writes. Our experiments over LINPACK and Livermore benchmarks demonstrate 26% reduced energy-vulnerability product compared to that of hardware cache configurations.

关键词： soft error vulnerability hybrid technique smart cache architecture energy efficient cache write-back

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A dynamic memory management unit for embedded real-time system-on-a-chip

A dynamic memory management unit for embedded real-time syst...

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Shalan, Mohamed Mooney III, Vincent J. Georgia Institute of Technology Sch. of Elec./Computer Engineering 801 Atlantic Drive Atlanta GA 30332-0250 United States

ISBN: (纸本)1581133383

Dealing with global on-chip memory allocation/de-allocation in a dynamic yet deterministic way is an important issue for upcoming billion transistor multiprocessor System-on-a-Chip (SoC) designs. To achieve this, we propose a new memory management hierarchy called Two-Level Memory Management. To implement this memory management scheme - Which presents a paradigm shift in the way designers look at on-chip dynamic memory allocation - We present a System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation of the global on-chip memory, which we refer to as level two memory management (level one is the operating system management of memory allocated to a particular on-chip processor). In this way, heterogeneous processors in an SoC can request and be granted portions of the global memory in twenty clock cycles in the worst case for a four-processor SoC, which is at least an order of magnitude faster than software-based memory management. We present a sample implementation of the SoCDMMU and compare hardware and software implementations.

关键词： Real time systems

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The performance and energy consumption of three embedded real-time operating systems 2

The performance and energy consumption of three embedded rea...

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Baynes, Kathleen Collins, Chris Fiterman, Eric Ganesh, Brinda Kohout, Paul Smit, Christine Zhang, Tiebing Jacob, Bruce Dept. of Electrical and Computer Engineering University of Maryland at College Park College ParkMD20742 United States

ISBN: (纸本)1581133995

This paper presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs by executing them on an accurate architectural model of a microcontroller with simulated real-time stimuli. We briefly describe the simulation environment and present a study that compares three RTOSs: μC/OS-II, a popular public-domain embedded real-time operating system;Echidna, a sophisticated, industrial-strength (commercial) RTOS;and NOS, a bare-bones multi-rate task scheduler reminiscent of typical "roll-your-own" RTOSs found in many commercial embedded systems. The microcontroller simulated in this study is the Motorola M-CORE processor: a low-power, 32-bit CPU core with 16-bit instructions, running at 20MHz. Copyright 2001 ACM.

关键词： Microcontrollers

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Establishing a tight bound on task interference in embedded system instruction caches 2

Establishing a tight bound on task interference in embedded ...

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Dwyer, Harry Fernando, John Agere Systems 1247 S. Cedar Crest Blvd. AllentownPA18103 United States

ISBN: (纸本)1581133995

To help meet the increasing performance demands of embedded applications, caches are utilized in some embedded systems. However, caches are problematic in real-time systems because they may cause a task's execution time to be uncertain, making a tight worst-case time-bound difficult to achieve. To simplify an execution time analysis, conservative assumptions are often made that may waste system capability or filead to an unnecessarily costly system. Efficient system design requires methods to tightly bound the effect of complex cache behavior. This paper presents methods that bound the effect of sharing an instruction cache among multiple tasks. If an application is interrupted, the intervening task often changes cache state - so the application experiences degraded performance when it resumes. Techniques that tightly bound this effect are the goal of this paper. Our methodology uses the concept of a "live cache frame, " a cache frame that contains a block that is accessed in the future and without an intervening eviction. An intervening task delays the completion of an application both by its execution time and by evicting blocks from the application's live frames (LRU status changes have a secondary effect). Only these evictions cause future misses that would not otherwise occur. The maximum number of live frames coexistent during the execution of an application bound such misses, independent of intervening tasks. This is central to one method presented. We also present methods that exploit knowledge of the character of an intervening task to achieve a tighter bound when possible. Copyright 2001 ACM.

关键词： embedded systems

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