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FFT-cache: A flexible fault-tolerant cache architecture for ultra low voltage operation

FFT-cache: A flexible fault-tolerant cache architecture for ...

引用

embedded systems Week 2011, ESWEEK 2011 - 14th international conference on compilers, architectures and synthesis for embedded systems, cases'11

作者： Mofrad, Abbas Banaiyan Homayoun, Houman Dutt, Nikil Center for Embedded Computer Systems University of California Irvine United States Department of Computer Science and Engineering University of California San Diego United States

ISBN: (纸本)9781450307130

Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation-induced failures in cache SRAM arrays, which compromise cache reliability. In this paper, we propose Flexible Fault-Tolerant Cache (FFT-Cache) that uses a flexible defect map to configure its architecture to achieve significant reduction in energy consumption through aggressive voltage scaling, while maintaining high error reliability. FFT-Cache uses a portion of faulty cache blocks as redundancy - using block-level or line-level replication within or between sets - to tolerate other faulty caches lines and blocks. Our configuration algorithm categorizes the cache lines based on degree of conflict of their blocks to reduce the granularity of redundancy replacement. FFT-Cache thereby sacrifices a minimal number of cache lines to avoid impacting performance while tolerating the maximum amount of defects. Our experimental results on SPEC2K benchmarks demonstrate that the operational voltage can be reduced down to 375mV, which achieves up to 80% reduction in dynamic power and up to 48% reduction in leakage power with small performance impact and area overhead. Copyright © 2011 ACM.

关键词： Defects

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WCET-driven Cache-aware Code Positioning

WCET-driven Cache-aware Code Positioning

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14th Confernece on compilers, architectures and synthesis for embedded systems (cases)

作者： Falk, Heiko Kotthaus, Helena Univ Ulm Inst Embedded Systems Real Time Syst D-89069 Ulm Germany Tech Univ Dortmund Comp Sci 12 D-44221 Dortmund Germany

ISBN: (纸本)9781450307130

Code positioning is a well-known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of code fragments in memory avoids overlapping of cache sets and thus decreases the number of cache conflict misses. We present a novel cache-aware code positioning optimization driven by worst-case execution time (WCET) information. For this purpose, we introduce a formal cache model based on a conflict graph which is able to capture a broad class of cache architectures. This cache model is combined with a formal WCET timing model, resulting in a cache conflict graph weighted with WCET data. This conflict graph is then exploited by heuristics for code positioning of both basic blocks and entire functions. Code positioning is able to decrease the accumulated cache misses for a total of 18 real-life benchmarks by 15.5% on average for an automotive processor featuring a 2-way set-associative cache. These cache miss reductions translate to average WCET reductions by 6.1%. For direct-mapped caches, even larger savings of 18.8% (cache misses) and 9.0% (WCET) were achieved.

关键词： WCET Cache Code Positioning Locality Cache Miss

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

CASES 2006: International Conference on Compilers, Architect...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

ISBN: (纸本)1595935436

The proceedings contain 42 papers. The topics discussed include: an accurate and efficient simulation-based analysis for worst case interruption delay;automatic performance model construction for the fast software exploration of new hardware designs;supporting precise garbage collection in Java Bytecode-to-C ahead-of-time compiler for embedded systems;adapting compilation techniques to enhance the packing of instructions into registers;a network agent for diagnosis and analysis of real-time Ethernet networks;memory optimization by counting points in integer transformations of parametric polytopes;incremental elaboration for run-time reconfigurable hardware designs;adaptive and flexible dictionary code compression for embedded applications;automated compile-time and run-time techniques to increase usable memory in MMU-less embedded systems;and scalable subgraph mapping for acyclic computation accelerators.

关键词： Program compilers

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WCET-driven Branch Prediction aware Code Positioning

WCET-driven Branch Prediction aware Code Positioning

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14th Confernece on compilers, architectures and synthesis for embedded systems (cases)

作者： Plazar, Sascha Kleinsorge, Jan Marwedel, Peter Falk, Heiko Tech Univ Dortmund Comp Sci 12 D-44221 Dortmund Germany Ulm Univ Inst Embedded Syst Real Time Syst D-89081 Ulm Germany

ISBN: (纸本)9781450307130

In the past decades, embedded system designers moved from simple, predictable system designs towards complex systems equipped with caches, branch prediction units and speculative execution. This step was necessary in order to fulfill increasing requirements on computational power. Static analysis techniques considering such speculative units had to be developed to allow the estimation of an upper bound of the execution time of a program. This bound is called worst-case execution time (WCET). Its knowledge is crucial to verify whether hard real-time systems satisfy their timing constraints, and the WCET is a key parameter for the design of embedded systems. In this paper, we propose a WCET-driven branch prediction aware optimization which reorders basic blocks of a function in order to reduce the amount of jump instructions and mispredicted branches. We employed a genetic algorithm which rearranges basic blocks in order to decrease the WCET of a program. This enables a first estimation of the possible optimization potential at the cost of high optimization runtimes. To avoid time consuming repetitive WCET analyses, we developed a new algorithm employing integer-linear programming (ILP). The ILP models the worst-case execution path (WCEP) of a program and takes branch prediction effects into account. This algorithm enables short optimization runtimes at slightly decreased optimization results. In a case study, the genetic algorithm is able to reduce the benchmarks' WCET by up to 24.7% whereas our ILP-based approach is able to decrease the WCET by up to 20.0%.

关键词： Branch Prediction Code Positioning WCET

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embedded systems Week 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

Embedded Systems Week 2009 - 2009 International Conference o...

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embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

ISBN: (纸本)9781605586267

The proceedings contain 31 papers. The topics discussed include: sustaining Moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects;complete nanowire crossbar framework optimized for the multi-spacer patterning technique;exploiting residue number system for power-efficient digital signal processing in embedded processors;fast enumeration of maximal valid subgraphs for custom-instruction identification;hybrid multithreading for VLIW processors;spatial complexity of reversibly computable DAG;mapping stream programs onto heterogeneous multiprocessor systems;optimal loop parallelization for maximizing iteration-level parallelism;slicing based code parallelization for minimizing inter-processor communication;fine-grain performance scaling of soft vector processors;fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGs on FPGA;and streaming FFT on REDEFINE-v2: an application-architecture design space exploration.

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compilers, architectures and synthesis for embedded computing: Retrospect and prospect

Compilers, architectures and synthesis for embedded computin...

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6th embedded systems Week 2010, ESWEEK 2010 - 2010 international conference on compilers, architecture, and synthesis for embedded systems, cases'10

作者： Palem, Krishna V. Department of Computing Rice University Houston TX United States Institute of Sustainable and Applied Infodynamics Nanyang Technological University Singapore Singapore

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Challenges for embedded Multicore architecture

Challenges for Embedded Multicore Architecture

引用

6th embedded systems Week (ESWEEK)

作者： Carro, Luigi Gaydadjiev, Georgi N. Univ Fed Rio Grande do Sul Inst Informat Av Bento Goncalves 9500Bloco 4 Porto Alegre RS Brazil Delft Univ Technol Fac Elect Engn Math & Comp Sci NL-2628 CD Delft Netherlands

In this tutorial we discuss the impact of multicore architectures for embedded devices at different levels, ranging from heterogeneous/homogeneous ISAs to the organization and software development.

ISBN: (纸本)9781605589039

In this tutorial we discuss the impact of multicore architectures for embedded devices at different levels, ranging from heterogeneous/homogeneous ISAs to the organization and software development.

关键词： architectures embedded architectures Multicore architectures Computer organization

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E 2: Less energy through multi-copy cache

E 2: Less energy through multi-copy cache

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6th embedded systems Week 2010, ESWEEK 2010 - 2010 international conference on compilers, architecture, and synthesis for embedded systems, cases'10

作者： Chakraborty, Arup Homayoun, Houman Khajeh, Amin Dutt, Nikil Eltawil, Ahmed Kurdahi, Fadi Center for Embedded Computer Systems University of California Irvine CA United States

ISBN: (纸本)9781605589039

Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation-induced failures in cache SRAM arrays, which compromise cache reliability. We present Multi-Copy Cache (MC2), a new cache architecture that achieves significant reduction in energy consumption through aggressive voltage scaling, while maintaining high error resilience (reliability) by exploiting multiple copies of each data item in the cache. Unlike many previous approaches, MC2 does not require any error map characterization and therefore is responsive to changing operating conditions (e.g., Vdd-noise, temperature and leakage) of the cache. MC2 also incurs significantly lower overheads compared to other ECC-based caches. Our experimental results on embedded benchmarks demonstrate that MC2 achieves up to 60% reduction in energy and energy-delay product (EDP) with only 3.5% reduction in IPC and no appreciable area overhead.

关键词： Fault tolerance

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From ESL 2010 to ESL 2015 10

From ESL 2010 to ESL 2015

引用

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

作者： Jeremiassen, Tor Martin, Grant Kogel, Tim Donlin, Adam Takach, Andres Chatha, Karam Texas Instruments United States Tensilica United States Synopsys United States Xilinx United States Mentor Graphics United States Arizona State University United States

ISBN: (纸本)9781605589053

In 2010, a wave of consolidation swept over the Electronic System Level (ESL) design industry. It brought ESL providers together with mainstream EDA houses and created opportunities for new ESL ventures. This paper contains short summaries of presentations in a special session focusing on the future of ESL. The session has two goals: the first is to present the state of the art in ESL tools and practice and, second, share a vision of the technical challenges that the next generation of ESL companies should address. The session includes a mix of perspectives from both ESL solution vendors and end-users and touches all all four ESL use cases: software virtual platforms, performance analysis, high level synthesis and verification.

关键词： High level synthesis

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Fine-grain Dynamic Instruction Placement for L0 Scratch-Pad Memory

Fine-grain Dynamic Instruction Placement for L0 Scratch-Pad ...

引用

6th embedded systems Week (ESWEEK)

作者： Park, Jongsoo Balfour, James Dally, William J. Stanford Univ Stanford CA 94305 USA NVIDIA Res Santa Clara CA USA

ISBN: (纸本)9781605589039

We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm captures a large fraction of instruction reuse missed by coarse-grain placement algorithms whose unit of transfer is restricted to loops or functions within the capacity of spms. Evaluation of L0 spms with our fine-grain algorithm in 17 applications shows that the energy consumed by instruction storage hierarchy is reduced by 38% and 31% compared to that of L0 instruction caches and L0 spms with an ideal coarse-grain algorithm, respectively.

关键词： Code Placement compilers embedded systems Scratch-Pad Memory

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