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A holistic approach to network-on-chip synthesis 10

A holistic approach to network-on-chip synthesis

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Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

作者： Leary, Glenn Chatha, Karam S. Department of CSE Arizona State University P.O. Box 875406 Tempe AZ 85287-5406 United States

ISBN: (纸本)9781605589053

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

关键词： Network-on-chip

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Message from the cases 2010 program chairs

Embedded Systems Week 2010 - Proceedings of the 2010 Interna...

引用

embedded systems Week 2010 - Proceedings of the 2010 international conference on compilers, architecture and synthesis for embedded systems, cases'10 2010年 v页

作者： Tatge, Reid Kathail, Vinod

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Routing-Based synthesis of Digital Microfluidic Biochips

Routing-Based Synthesis of Digital Microfluidic Biochips

引用

6th embedded systems Week (ESWEEK)

作者： Maftei, Elena Pop, Paul Madsen, Jan Tech Univ Denmark DTU Informat DK-2800 Lyngby Denmark

ISBN: (纸本)9781605589039

Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the basic functions for biochemical analysis. The "digital" microfluidic biochips are manipulating liquids not as a continuous flow, but as discrete droplets on a two-dimensional array of electrodes. Basic microfluidic operations, such as mixing and dilution, are performed on the array, by routing the corresponding droplets on a series of electrodes. So far, researchers have assumed that these operations are executed on rectangular virtual devices, formed by grouping several adjacent electrodes. One drawback is that all electrodes are considered occupied during the operation execution, although the droplet uses only one electrode at a time. Moreover, the operations can actually execute by routing the droplets on any sequence of electrodes on the array. Hence, in this paper, we eliminate the concept of virtual modules and allow the droplets to move on the chip on any route during operation execution. Thus, the synthesis problem is transformed into a routing problem. We propose an approach derived from a Greedy Randomized Adaptive Search Procedure (GRASP) and we show that by considering routing-based synthesis, significant improvements can be obtained in the application completion time.

关键词： Microfluidics biochips synthesis routing

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Enabling Large Decoded Instruction Loop Caching for Energy-Aware embedded Processors

Enabling Large Decoded Instruction Loop Caching for Energy-A...

引用

6th embedded systems Week (ESWEEK)

作者： Gu, Ji Guo, Hui Univ New South Wales Sch Comp Sci & Engn Sydney NSW 2052 Australia

ISBN: (纸本)9781605589039

Low energy consumption in embedded processors is increasingly important in step with the system complexity. The on-chip instruction cache (I-cache) is usually a most energy consuming component on the processor chip due to its large size and frequent access operations. To reduce such energy consumption, the existing loop cache approaches use a tiny decoded cache to filter the I-cache access and instruction decode activity for repeated loop iterations. However, such designs are effective to small and simple loops, and only suitable for DSP kernel-like applications. They are not effectual to many embedded applications where complex loops are common. In this paper, we propose a decoded loop instruction cache (DLIC) that is small, hence energy efficient, yet can capture most loops, including large, nested ones with branch executions, so that a significant amount of I-cache accesses and instruction decoding can be eradicated. Experiments on a set of embedded benchmarks show that our proposed DLIC scheme can reduce energy consumption by up to 87%. On average, 66% energy can be saved on instruction fetching and decoding, at a performance overhead of only 1.4%.

关键词： Cache hierarchy filter cache instruction decode low power low energy embedded systems

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A Memory Interface for Multi-Purpose Multi-Stream Accelerators

A Memory Interface for Multi-Purpose Multi-Stream Accelerato...

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6th embedded systems Week (ESWEEK)

作者： Girbal, Sylvain Temam, Olivier Yehia, Sami Berry, Hugues Li, Zheng Thales Res & Technol Embedded Syst Lab Palaiseau France INRIA Saclay ALCHEMY Grp Orsay France

ISBN: (纸本)9781605589039

Power and programming challenges make heterogeneous multicores composed of cores and ASICs an attractive alternative to homogeneous multi-cores. Recently, multi-purpose loop-based generated accelerators have emerged as an especially attractive accelerator option. They have several assets: short design time (automatic generation), flexibility (multi-purpose) but low configuration and routing overhead (unlike FPGAs), computational performance (operations are directly mapped to hardware), and a focus on memory throughput by leveraging loop constructs. However, with multiple streams, the memory behavior of such accelerators can become at least as complex as that of superscalar processors, while they still need to retain the memory ordering predictability and throughput efficiency of DMAs. In this article, we show how to design a memory interface for multi-purpose accelerators which combines the ordering predictability of DMAs, retains key efficiency features of memory systems for complex processors, and requires only a fraction of their cost by leveraging the properties of streams references. We evaluate the approach with a synthesizable version of the memory interface for an example 9-task generated loop-based accelerator.

关键词： Memory interface Accelerators multi-stream

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MNEMEE - A Framework for Memory Management and Optimization of Static and Dynamic Data in MPSoCs

MNEMEE - A Framework for Memory Management and Optimization ...

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6th embedded systems Week (ESWEEK)

作者： Mallik, Arindam Marwedel, Peter Soudris, Dimitrios Stuijk, Sander IMEC VZW B-3000 Leuven Belgium TU Dortmund Dortmund Germany Natl Tech Univ Athens GR-10682 Athens Greece Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781605589039

As embedded systems are becoming the center of our digital life, system design becomes progressively harder. The integration of multiple features on devices with limited resources requires careful and exhaustive exploration of the design search space in order to efficiently map modern applications to an embedded multi-processor platform. The MNEMEE project [1] addresses this challenge by offering a unique integrated tool flow that performs source-to-source transformations to automatically optimize the original source code and map it on the target platform. The optimizations aim at reducing the number of memory accesses and the required memory storage of both dynamically and statically allocated data. Furthermore, the MNEMEE tool flow performs optimal assignment of all data on the memory hierarchy of the target platform. Overall, the MNEMEE techniques embedded in it will lead to more cost efficient systems that offer a better performance and lower energy consumption. This tutorial gives an overview of the MNEMEE tool flow. The objective of the tutorial is to familiarize the audience with the tool framework and the optimizations used in the individual tools. The tutorial also features a demonstration of the tool flow. This demonstration shows that the tools developed in the MNEMEE project provide a user-friendly and efficient framework for MPSoC programming and memory management.

关键词： MPSoc Design embedded software Memory Management Automatic Parallelization

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Implementing Dynamic Implied Addressing Mode for Multi-Output Instructions

Implementing Dynamic Implied Addressing Mode for Multi-Outpu...

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6th embedded systems Week (ESWEEK)

作者： Youn, Jonghee M. Lee, Jongwon Paek, Yunheung Kim, Jongwung Cho, Jeonghun Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul South Korea Kyungpook Natl Univ Sch Elect Engn & Comp Sci Daegu South Korea

ISBN: (纸本)9781605589039

The ever-increasing demand for faster execution time, smaller resource usage and lower energy consumption has compelled architects of embedded processors to adopt more specialized hardware features with irregular data paths and heterogeneous registers that are customized to the needs of their target applications. These processors consequently provide a rich set of specialized instructions in order to enable programmers to access these features. Such an instruction is typically a multi-output instruction (MOI), which outputs multiple results parallely in order to exploit inherent underlying hardware parallelism. Earlier study has exhibited that MOIs help to enhance performance in aspect of instruction counts and code size. However, as MOIs require more operands, they tend to increase not only the size of the instruction set but also the size of individual instructions. This can be a serious setback for embedded processors, which are mostly subject to strong resource limitations (particularly in this case, limited instruction encoding space). For this reason, these processors are often allowed to include only a very small subset of the total desired MOIs in their instruction sets, despite there can be sufficient silicon real estate to accommodate these specialized MOIs. To attack this problem, we introduce a novel instruction encoding scheme based on the dynamic implied addressing mode (DIAM). In this paper, we will discuss how we have overcome the encoding space problem for our target embedded processor whose instruction set has been augmented with a variety of MOIs. Our DIAM-based encoding scheme employs a small on-chip buffer to supplement extra encoding information for MOIs at run time. The empirical results are promising: the scheme allows us to encode many more MOIs for our processor;thereby helping us to achieve considerable reduction of code size as well as running time after the DIAM is additively implemented in the original architecture.

关键词： embedded Processor Compiler Optimization

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embedded systems Week 2008 - Proceedings of the 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

Embedded Systems Week 2008 - Proceedings of the 2008 Interna...

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

ISBN: (纸本)9781605584690

The proceedings contain 27 papers. The topics discussed include: a light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization;ZebraNet and beyond: applications and systems support for mobile, dynamic networks;non-intrusive dynamic application profiler for detailed loop execution characterization;exploring and predicting the architecture/optimizing compiler co-design space;compiling custom instructions onto expression-grained reconfigurable architectures;dynamic coprocessor management for FPGA-enhanced compute platforms;power on demand for mobile computing devices;efficiency and scalability of barrier synchronization on NoC based many-core architectures;decoupled root scanning in multi-processor systems;and efficient code caching to improve performance and energy consumption for Java applications.

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Design and synthesis of a Multiprocessor System-on-Chip architecture for Real-Time Biomedical Signal Processing in Gamma Cameras

Design and Synthesis of a Multiprocessor System-on-Chip Arch...

引用

IFIP international conference embedded and Ubiquitous Computing

作者： Sun, Kai Wang, Meng Shao, Zili Liu, Hui Wei, Hongxing Wang, Tianmiao Hong Kong Polytech Univ Dept Comp Kowloon Hong Kong Peoples R China Beihang Univ Robot Res Inst Beijing 100083 Peoples R China Xidan Univ Inst Software Engn Xian Peoples R China

MPSoC (Multi-Processor System-on-Chip) architecture is becoming increasingly used because it can provide designers much more opportunities to meet specific performance and power goals. In this paper, we propose an MPSoC architecture for implementing real-time signal processing in gamma camera. Based on a fully analysis of the characteristics of the application, we design several algorithms to optimize the systems in terms of processing speed, power consumption, and area costs etc. Two types of DSP core have been designed for the integral algorithm and the coordinate algorithm, the key parts of signal processing in a gamma camera. An interconnection synthesis algorithm is proposed to reduce the area cost of the Network-on-Chip. We implement our MPSoC architecture on FPGA, and synthesize DSP cores and Network-on-Chip using Synopsys Design Compiler with a UMC 0.18 mu m standard cell library. The results show that our technique can effectively accelerate the processing and satisfy the requirements of real-time signal processing for 256 x 256 image construction.

关键词： Real time Multiprocessor system-on-chip

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embedded systems Week 2008 - Proceedings of the 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08: Foreword

Embedded Systems Week 2008 - Proceedings of the 2008 Interna...

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embedded systems Week 2008 - Proceedings of the 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08 2008年 iii页

作者： Altman, Erik Parameswaran, Sridevan IBM Research University of New South Wales Australia

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