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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

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Compilation techniques for energy reduction in horizontally partitioned cache architectures

Compilation techniques for energy reduction in horizontally ...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Shrivastava, Aviral Issenin, Ilya Dutt, Nikil Center for Embedded Computer Systems Department of Information and Computer Science University of California Irvine Irvine CA United States

ISBN: (纸本)159593149X

Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally partitioned caches help reduce cache pollution and thereby improve performance. Consequently most previous research has focused on exploiting horizontally partitioned data caches to improve performance, and achieve energy reduction only as a byproduct of performance improvement. In constrast, in this paper we show that optimizing for performance trades-off several opportunities for energy reduction. Our experiments on a HP iPAQ h4300-like memory subsystem demonstrate that optimizing for energy consumption results in up to 127% less memory subsystem energy consumption than the performance optimal solution. Furthermore, we show that energy optimal solution incurs on average only 1.7% performance penalty. Therefore, with energy consumption becoming a first class design constraint, there is a need for compilation techniques aimed at energy reduction. To achieve aforementioned energy savings we propose and explore several low-complexity algorithms aimed at reducing the energy consumption and show that very simple greedy heuristics achieve 97% of the possible memory subsystem energy savings. Copyright 2005 ACM.

关键词： Buffer storage

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Providing time- and space- efficient procedure calls for asynchronous Software Thread Integration

Providing time- and space- efficient procedure calls for asy...

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Asokan, Vasanth Dean, Alexander G. Center for Embedded Systems Research Department of Electrical and Computer Engineering North Carolina State University Raleigh NC 27695-7256 United States

ISBN: (纸本)1581138903

Asynchronous Software Thread Integration (ASTI) provides fine-grain concurrency in real-time threads by statically scheduling (integrating) code from primary threads into secondary threads, reducing the context switching needed and allowing recovery of fine-grain idle time. Unlike STI, ASTI allows asynchronous thread progress. Current ASTI techniques do not support procedure calls in the secondary thread because they lead to timing conflicts during static scheduling. ASTI requires knowing the secondary thread's instruction execution schedule to guide placement of real-time instructions from the primary thread. A secondary thread procedure called from multiple sites will have ambiguous timing at compile time. In this paper we remove this constraint using both procedure inlining and cloning. We present a formal approach to choosing a subset of calls to inline and to remove the timing conflicts in the remaining call sites in an efficient fashion. Excessive inlining and cloning both lead to code size explosion, while poor choices in timing conflict elimination slow program execution. The cloned threads show a significant speedup when compared to non-cloned versions yet have low code expansion. The techniques presented here have been implemented in our post-pass compiler Thrint and demonstrated on a benchmark suite of secondary threads representative of low-end embedded systems. Copyright 2004 ACM.

关键词： Computer software

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Compositional Analysis of Real-Time embedded systems

Compositional Analysis of Real-Time Embedded Systems

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14th Confernece on compilers, architectures and synthesis for embedded systems (cases)

作者： Phan, Linh T. X. Lee, Insup Sokolsky, Oleg Univ Penn Dept Comp & Informat Sci Philadelphia PA 19104 USA

ISBN: (纸本)9781450307130

This tutorial is concerned with various aspects of component-based design and compositional analysis of real-time embedded systems. It will first give an overview of component-based frameworks and their underlying principles. It will then go in-depth into abstraction methods for real-time components and techniques for computing their optimal interfaces, for both systems implemented on uniprocessor and multiprocessor platforms, as well as extensions to multi-mode systems. Besides theoretical aspects, the tutorial will also present an implementation of the compositional analysis framework on Xen virtualization and a demonstration of the CARTS toolset with several examples seeing the techniques in action. It will also include two case studies highlighting the utility of the framework, including the ARINC-653 avionics software and a smart-phone application. We will conclude the tutorial with a number of open challenges and research opportunities in this domain.

关键词： Real-time interfaces Compositional schedulability analysis Hierarchical scheduling Multi-mode systems

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On-the-Fly Load Data Value Tracing in Multicores

On-the-Fly Load Data Value Tracing in Multicores

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international conference on Compliers, architectures, and synthesis of embedded systems (cases)

作者： Ponugoti, Mounika Tewar, Amrish K. Milenkovic, Aleksandar Univ Alabama Dept Elect & Comp Engn 301 Sparkman Dr Huntsville AL 35899 USA

ISBN: (纸本)9781450344821

Software testing and debugging of modern multicore-based embedded systems is a challenging proposition because of growing hardware and software complexity, increased integration, and tightening time-to-market. To find more bugs faster, software developers of real-time embedded systems increasingly rely on on-chip trace and debug resources, including hefty on-chip buffers and wide trace ports. However, these resources often offer limited visibility of the system, increase the system cost, and do not scale well with a growing number of cores. This paper introduces mlvCFiat, a hardware/software mechanism for capturing and filtering load data value traces in multicores. It relies on first access tracking in data caches and equivalent modules in the software debugger to significantly reduce the number of trace events streamed out of the target platform. Our experimental evaluation explores the effectiveness of the proposed technique as a function of cache sizes, encoding mechanism, and the number of cores. The results show that mlvCFiat significantly reduces the total trace port bandwidth. The improvements relative to the existing Nexus-like load data value tracing range from 15 to 33 times for a single core and from 14 to 20 times for an octa core.

关键词： Real-time embedded systems Multicores Software testing and debugging Program Tracing

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Exploiting pipelining to relax register-file port constraints of instruction-set extensions

Exploiting pipelining to relax register-file port constraint...

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Pozzi, Laura Ienne, Paolo School of Computer and Communication Sciences CH-1015 Lausanne Switzerland

ISBN: (纸本)159593149X

Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). While these processors have become available, the state of the art on automatic ISE identification is improving;many algorithms are being proposed for choosing, given the application's source code, the best ISEs under various constraints. Read and write ports between the AFUs and the processor register file are an expensive asset, fixed in the microarchitecture - some processors indeed only allow two read and one write ports - and, on the other hand, a large availability of inputs and outputs to and from the AFUs exposes high speedup. This paper proposes a solution to the limitation of actual register file ports by serialising register file access and therefore addressing multi-cycle read and write. It does so in an innovative way for two reasons: (1) it exploits and brings forward the progress in ISE identification under constraint [1, 16, 4, 19], and (2) it combines register file access serialisation with pipelining in order to obtain the best global solution. This paper proposes an algorithm for scheduling graphs - corresponding to ISEs - under input/output constraint;experiments show that by using the proposed method applications can be sped-up tangibly: speedup for low I/O constraints is 32% better on average, and 65% better at best, than that obtained by state of the art techniques. Copyright 2005 ACM.

关键词： embedded systems

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Storage allocation for embedded processors 2

Storage allocation for embedded processors

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Sjödin, Jan Von Platen, Carl Uppsala University Department of Information Technology Box 337 UppsalaSE-751 05 Sweden IAR Systems Malmö Slagthus Carlsgatan 12 A MalmöSE-211 20 Sweden

ISBN: (纸本)1581133995

In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted to certain native pointer types. Different pointer types vary in size and cost. For example, it is typically cheaper to use an 8-bit pointer than a 16-bit pointer. The problem is to allocate data and select pointer types in the most effective way. Frequently accessed variables should be allocated in fast memory, and frequently used pointers and pointer expressions should be assigned cheap pointer types. Common practice is to perform this task manually. We present a model for storage allocation that is capable of describing architectures with irregular memory organization and with several native pointer types. This model is used in an integer linear programming (ILP) formulation of the problem. An ILP solver is applied to get an optimal solution under the model. We describe allocation of global variables and local variables with static storage duration. A whole program optimizing C compiler prototype was used to implement the allocator. Experiments were performed on the Atmel AVR 8-bit microcontroller [2] using small to medium sized C programs. The results varied with the benchmarks, with up to 8% improvement in execution speed and 10% reduction in code size. Copyright 2001 ACM.

关键词： Integer programming

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Efficient longest executable path search for programs with complex flows and pipeline effects 2

Efficient longest executable path search for programs with c...

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Stappert, Friedhelm Ermedahl, Andreas Engblom, Jakob C-LAB Fürstenallee 11 Paderborn33102 Germany DoCS Uppsala University Box 325 UppsalaSE-751 05 Sweden IAR Systems AB Box 23051 UppsalaSE-750 23 Sweden

ISBN: (纸本)1581133995

Current development tools for embedded real-time systems do not efficiently support the timing aspect. The most important timing parameter for scheduling and system analysis is the Worst-Case Execution Time (WCET) of a program. This paper presents a fast and effective WCET calculation method that takes account of low-level machine aspects like pipelining and caches, and high-level program flow like loops and infeasible paths. The method is more efficient than previous path-based approaches, and can easily handle complex programs. By separating the low-level from the high-level analysis, the method is easy to retarget. Experiments confirm that speed does not sacrifice precision, and that programs with extreme numbers of potential execution paths can be analyzed quickly. Copyright 2001 ACM.

关键词： embedded systems

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A simplified java bytecode compilation system for resource-constrained embedded processors

A simplified java bytecode compilation system for resource-c...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Badea, Carmen Nicolau, Alexandru Veidenbaum, Alexander V. Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)9781595938268

embedded platforms are resource-constrained systems in whichperformance and memory requirements of executed code are ofcritical importance. However, standard techniques such as full just-in-time(JIT) compilation and/or adaptive optimization (AO) may not be appropriate for this type of systems due to memory and compilation overheads. The research presented in this paper proposes a technique that combines some of the main benefits of JIT compilation, superoperators(SOs) and profile-guided optimization, in order to deliver a lightweight Java bytecode compilation system, targeted for resource-constrained environments, that achieves runtime performance similar to that of state-of-the-art JIT/AO systems, while having a minimal impact on runtime memory *** key ideas are to use profiler-selected, extended bytecode basic blocks as superoperators (new bytecode instructions) and to perform few, but very targeted, JIT/AO-like optimizations at compile time only on the superoperators. bytecode, as directed by compilation .hints. encoded as annotations. As such, our system achieves competitive performance to a JIT/AO system, but witha much lower impact on runtime memory consumption. Moreover,it is shown that our proposed system can further improveprogram performance by selectively inlining method calls embedded in the chosen superoperators, as directed by runtime profiling data and with minimal impact on classfile size. For experimental evaluation, we developed three Virtual Machines(VMs) that employ the ideas presented above. The customized VMs are first compared (w.r.t. runtime performance) to a simple, fast-to-develop VM (baseline) and then to a VM that employs JIT/AO. Our best-performing system attains speedups ranging from a factor of 1.52 to a factor of 3.07, w.r.t. to the baseline VM. When compared to a state-of-the-art JIT/AO VM, our proposed system performs better for three of the benchmarks and worse by less than a factor of 2 for three others. But our SO-ext

关键词： embedded systems

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embedded ISA support for enhanced floating-point to fixed-point ANSI C compilation

Embedded ISA support for enhanced floating-point to fixed-po...

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Aamodt, Tor Chow, Paul Dept. of Elec./Computer Engineering University of Toronto Toronto Ont. M5S 3G4 Canada

ISBN: (纸本)1581133383

Recently tools for automating the translation of floating-point signal-processing applications written in ANSI C into fixed-point have been presented [36, 19, 8]. This paper introduces a novel fixed-point instruction-set operation, Fractional Multiplication with internal Left Shift (FMLS), and an associated translation algorithm-Intermediate-Result-Profiling based Shift Absorption (IRP-SA), that enhance fixed-point rounding-noise and runtime performance. A significant feature of FMLS is that it is well suited to the latest generation of embedded processors that maintain relatively homogeneous register architectures. FMLS may improve the rounding-noise performance of fractional multiplication operations in three ways depending upon the specific fixed-point scaling properties an application exhibits. The IRP-SA algorithm enhances this by exploiting the modular nature of 2's-complement addition which allows the discarding of most-significant-bits that are redundant due to inter-operand correlations. Rounding-noise reductions equivalent to carrying as much as 2.0 additional bits of precision throughout the computation are presented. Furthermore, by encoding a very limited set of output shift values (two left, one left, none, and one right) into the FMLS operation, speedups of up to 13 percent are observed.

关键词： embedded systems

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Heterogeneous memory management for embedded systems 2

Heterogeneous memory management for embedded systems

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Avissar, Oren Barua, Rajeev Stewart, Dave ECE Department University of Maryland College ParkMD20742 United States Embedded Research Solutions LLC 9687F Gerwig Lane ColumbiaMD21046 United States

ISBN: (纸本)1581133995

This paper presents a technique for the efficient compiler management of software-exposed heterogeneous memory. In many lower-end embedded chips, often used in micro-controllers and DSP processors, heterogeneous memory units such as scratch-pad SRAM, internal DRAM, external DRAM and ROM are visible directly to the software, without automatic management by a hardware caching mechanism. Instead the memory units are mapped to different portions of the address space. Caches are avoided because of their cost and power consumption, and because they make it difficult to guarantee real-time performance. For this important class of embedded chips, the allocation of data to different memory units to maximize performance is the responsibility of the software. Current practice typically fileaves it to the programmer to partition the data among the different memory units. We present a compiler strategy that automatically partitions the data among the memory units. We show that this strategy is optimal among all static partitions for global and stack data, and a good heuristic for heap data. For global and stack data, the scheme is provably equal to or better than any other compiler scheme or set of programmer annotations. Preliminary results show the benefits of optimal allocation: with just 20% of the data in SRAM, the formulation is able to decrease the runtime by 39% on average for our benchmarks vs. allocating all data to slow memory, without any programmer involvement. For some programs, filess than 5% of data in SRAM achieves a similar speedup. Copyright 2001 ACM.

关键词： Static random access storage

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