The proceedings contain 14 papers. The topics discussed include: work-in-progress: persistence improvement for distributed cache with NVM based storage system;work-in-progress: communication-aware scheduling of data-p...
ISBN:
(纸本)9781538655641
The proceedings contain 14 papers. The topics discussed include: work-in-progress: persistence improvement for distributed cache with NVM based storage system;work-in-progress: communication-aware scheduling of data-parallel tasks;work in progress: GeMS: a generator for modulo scheduling problems;work-in-progress: a partitioning strategy for exploring error-resilience in circuits;work in progress: performance modeling for data distribution in heterogeneous computing systems;work in progress: EPerf: energy-efficient execution of user-interactive event-driven applications;and work-in-progress: DRAM cache access optimization leveraging line locking in tag cache.
The proceeding contains 36 papers. The topics discussed include: hierarchical coarse-grained stream compilation for software defined radio;an efficient framework for dynamic reconfiguration of instruction-set customiz...
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ISBN:
(纸本)9781595938268
The proceeding contains 36 papers. The topics discussed include: hierarchical coarse-grained stream compilation for software defined radio;an efficient framework for dynamic reconfiguration of instruction-set customization;compiler generation from structural architecture descriptions;lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms;light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs;supporting multithreading in configurable soft processor cores;a group-based wear-leveling algorithm for large-capacity flash memory storage systems;facilitating compiler optimizations through the dynamic mapping of alternate register structures;vertical object layout and compression for fixed heaps;software controlled memory layout reorganization for irregular array access patterns;a self-maintained memory module supporting DMM;compiling code accelerators for FPGAs;and multicore architectures.
The proceedings contain 31 papers. The topics discussed include: design space characterization for architecture/compiler co-exploration;storage allocation for embedded processors;an empirical evaluation of high level ...
ISBN:
(纸本)1581133995
The proceedings contain 31 papers. The topics discussed include: design space characterization for architecture/compiler co-exploration;storage allocation for embedded processors;an empirical evaluation of high level transformations for embedded processors;a novel approach to code analysis of digital signal processing systems;the very portable optimizer for digital signal processors;patchable instruction ROM architecture;hardware compilation of sequential Ada;a new method for compiling schizophrenic synchronous programs;transparent data-memory organizations for digital signal processors;a vision for embedded software;combined partitioning and data padding for scheduling multiple loop nests;heterogeneous memory management for embeddedsystems;establishing a tight bound on task interference in embedded system instruction caches;personal, handheld, wireless: the future of digital technology;pattern matching in reconfigurable logic for packet classification;personal, handheld, wireless: the future of digital technology;efficient longest executable path search for programs with complex flows and pipeline effects;and tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures.
The proceedings contain 31 papers. The topics discussed include: sustaining Moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects;complete nanowire crossbar fram...
ISBN:
(纸本)9781605586267
The proceedings contain 31 papers. The topics discussed include: sustaining Moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects;complete nanowire crossbar framework optimized for the multi-spacer patterning technique;exploiting residue number system for power-efficient digital signal processing in embedded processors;fast enumeration of maximal valid subgraphs for custom-instruction identification;hybrid multithreading for VLIW processors;spatial complexity of reversibly computable DAG;mapping stream programs onto heterogeneous multiprocessor systems;optimal loop parallelization for maximizing iteration-level parallelism;slicing based code parallelization for minimizing inter-processor communication;fine-grain performance scaling of soft vector processors;fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGs on FPGA;and streaming FFT on REDEFINE-v2: an application-architecture design space exploration.
The proceedings contain 22 papers. The topics discussed include: work-in-progress: reliability evaluation of power SCADA system with three-layer IDS;work-in-progress: MLGOPerf: an ML guided inliner to optimize perform...
ISBN:
(纸本)9781665472968
The proceedings contain 22 papers. The topics discussed include: work-in-progress: reliability evaluation of power SCADA system with three-layer IDS;work-in-progress: MLGOPerf: an ML guided inliner to optimize performance;work in progress: ACAC: an adaptive congestion-aware approximate communication mechanism for network-on-chip systems;work-in-progress: ExpCache: online-learning based cache replacement policy for non-volatile memory;on evaluation of on-chip thermal covert channel attacks;work-in-progress: prediction-based fine-grained LDPC reading to enhance high-density flash read performance;work-in-progress: object detection acceleration method by improving execution efficiency of AI device;and work-in-progress: toward a robust, reconfigurable hardware accelerator for tree-based genetic programming.
The proceedings contain 24 papers. The topics discussed include: the improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators;heuristics for greedy transport triggered architecture inter...
ISBN:
(纸本)9781450330503
The proceedings contain 24 papers. The topics discussed include: the improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators;heuristics for greedy transport triggered architecture interconnect exploration;energy-efficient VFI-partitioned multicore design using wireless NOC architectures;retargetable automatic generation of compound instructions for CGRA based reconfigurable processor applications;CoreFab: concurrent reconfigurable fabric utilization in heterogeneous multi-core systems;automatic custom instruction identification in memory streaming algorithms;auto-parallelization of data structure operations for GPUs;a novel compilation flow for parametric dataflow: programming model, scheduling, and application to heterogeneous MPSoC;a compiler framework for automatically mapping data parallel programs to heterogeneous MPSoCs;team up: cooperative memory management in embeddedsystems;a low-cost memory interface for high-throughput accelerators;and EnVM : virtual memory design for new memory architectures.
The proceedings contain 28 papers. The topics discussed include: balancing memory and performance through selective flushing of software code caches;Erbium: a deterministic, concurrent intermediater representation to ...
ISBN:
(纸本)9781605589039
The proceedings contain 28 papers. The topics discussed include: balancing memory and performance through selective flushing of software code caches;Erbium: a deterministic, concurrent intermediater representation to map data-flow tasks to scalable, persistent streaming processes;resource recycling: putting idle resources to work on a composable accelerator;instruction selection by graph transformation;routing-based synthesis of digital microfluidic biochips;mosaic of organic development through technology intervention in the rural Indian context;the virtual hospital: the emergence of telemedicine;implementing virtual secure circuit using a custom-instruction approach;mighty-morphing power-SIMD;towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE;implementing dynamic implied addressing mode for multi-output instructions;a memory interface for multi-purpose multi-stream accelerators;and hardware-based data value and address trace filtering techniques.
The proceedings contain 24 papers. The topics discussed include: expandable process networks to efficiently specify and explore task, data, and pipeline parallelism;automatic extraction of pipeline parallelism for emb...
ISBN:
(纸本)9781479914005
The proceedings contain 24 papers. The topics discussed include: expandable process networks to efficiently specify and explore task, data, and pipeline parallelism;automatic extraction of pipeline parallelism for embedded heterogeneous multi-core platforms;platform-dependent code generation for embedded real-time software;a novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory;scrubbing unit repositioning for fast error repair in FPGAs;exploiting phase inter-dependencies for faster iterative compiler optimization phase order searches;compiled multithreaded data paths on FPGAs for dynamic workloads;simultaneously optimizing dram cache hit latency and miss rate via novel set mapping policies;minimizing code size via page selection optimization on partitioned memory architectures;and CAeSaR: unified cluster-assignment scheduling and communication reuse for clustered VLIW processors.
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