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Exposing non-standard architectures to embedded software using compile-time virtualisation

Exposing non-standard architectures to embedded software usi...

引用

embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Gray, Ian Audsley, Neil C. Department of Computer Science University of York York United Kingdom

ISBN: (纸本)9781605586267

The architectures of embedded systems are often application-specific, containing multiple heterogenous cores, non-uniform memory, on-chip networks and custom hardware elements (e.g. DSP cores). Standard programming languages do not use these many of these features natively because they assume a traditional single processor and a single logical address space abstraction that hides these architectural details. This paper describes Compile-Time Virtualisation, a technique which uses a virtualisation layer to map software onto the target architecture whilst allowing the programmer to control the virtualisation mappings in order to effectively exploit custom architectures. Copyright 2009 ACM.

关键词： Virtualization

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Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips

Tabu search-based synthesis of dynamically reconfigurable di...

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embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Maftei, Elena Pop, Paul Madsen, Jan DTU Informatics Technical University of Denmark DK-2800 Kgs. Lyngby Denmark

ISBN: (纸本)9781605586267

Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the necessary functions for biochemical analysis. The "digital" microfluidic biochips are manipulating liquids not as a continuous flow, but as discrete droplets, and hence they are highly reconfigurable and scalable. A digital biochip is composed of a two-dimensional array of cells, together with reservoirs for storing the samples and reagents. Several adjacent cells are dynamically grouped to form a virtual device, on which operations are executed. During the execution of an operation, the virtual device can be reconfigured to occupy a different group of cells on the array. In this paper, we present a Tabu Search metaheuristic for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determines the allocation, resource binding, scheduling and placement of the operations in the application. In our approach, we consider moving the modules during their operation, in order to improve the completion time of the biochemical application. The proposed heuristic has been evaluated using three real-life case studies and ten synthetic benchmarks. Copyright 2009 ACM.

关键词： Tabu search

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Exploiting residue number system for power-efficient digital signal processing in embedded processors

Exploiting residue number system for power-efficient digital...

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embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Chokshi, Rooju Berezowski, Krzysztof S. Shrivastava, Aviral Piestrak, Stanislaw J. Microsoft Corporation Redmond WA United States Computer Science and Engineering Arizona State University Tempe AZ United States TIMA Laboratory 38031 Grenoble France LICM University of Metz 57070 Metz France

ISBN: (纸本)9781605586267

2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propagation. Residue Number System (RNS) breaks free of these bonds by decomposing a number into parts and performing arithmetic operations in parallel, significantly reducing the breadth of carry propagation. Consequently, RNS arithmetic has been proposed as a solution to improve the power-efficiency of arithmetic hardware. However, limitations of the expressiveness of RNS in terms of arithmetic operations together with overheads related to interaction with 2's complement arithmetic make programmable processor design that takes advantage of these benefits challenging. In this paper we meet this challenge by multi-tier synergistic co-design of architecture, micro-architecture, hardware components, as well as compilation techniques. Our experiments not only demonstrate simultaneous improvement of up to 30% in performance and 57% reduction in functional unit power consumption, but also that most of these benefits can be exploited with automatically generated code. Copyright 2009 ACM.

关键词： Digital signal processing

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Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions

Reducing impact of cache miss stalls in embedded systems by ...

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embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Bournoutian, Garo Orailoglu, Alex University of California San Diego 9500 Gilman Dr. #0404 San Diego CA 92093-0404 United States

ISBN: (纸本)9781605586267

Today, embedded processors are expected to be able to run complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for general-purpose processors. As such, the impact of memory latencies on the execution time increasingly becomes evident. All the while, it is also expected that embedded processors be power-conscientious as well as of minimal area impact. As a result, traditional methods for addressing performance and memory latencies, such as multiple issue, out-of-order execution and large, associative caches, are not aptly suited for the embedded domain due to the significant area and power overhead. This paper explores a novel approach to mitigating execution delays caused by memory latencies that would otherwise not be possible in a regular in-order, single-issue embedded processor without large, power-hungry constructs like a Reorder Buffer (ROB). The concept relies on both compile-time and run-time information to safely allow non-data-dependent instructions to continue executing while a memory stall has occurred. The simulation results show significant improvement in execution throughput of approximately 11%, while having a minimal impact on area overhead and power. Copyright 2009 ACM.

关键词： embedded systems

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Instruction cache locking inside a binary rewriter

Instruction cache locking inside a binary rewriter

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embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Anand, Kapil Barua, Rajeev Department of Electrical and Computer Engineering University of Maryland College Park MD United States

ISBN: (纸本)9781605586267

Cache memories in embedded systems play an important role in reducing the execution time of the applications. Various kinds of extensions have been added to cache hardware to enable software involvement in replacement decisions, thus improving the run-time over a purely hardware-managed cache. Novel embedded systems, like Intel's Xscale and ARM Cortex processors provide the facility of locking one or more lines in cache - this feature is called cache locking. This paper presents the first method in the literature for instruction-cache locking that is able to reduce the average-case run-time of the program. We devise a cost-benefit model to discover the memory addresses which should be locked in the cache. We implement our scheme inside a binary rewriter, thus widening the applicability of our scheme to binaries compiled using any compiler. Results obtained on a suite of MiBench and MediaBench benchmarks show up to 25% improvement in the instruction-cache miss rate on average and up to 13.5% improvement in the execution time on average for applications having instruction accesses as a bottleneck, depending on the cache configuration. The improvement in execution time is as high as 23.5% for some benchmarks. Copyright 2009 ACM.

关键词： embedded systems

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Sustaining Moore's law in embedded computing through probabilistic and approximate design: Retrospects and prospects

Sustaining Moore's law in embedded computing through probabi...

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embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Palem, Krishna V. Chakrapani, Lakshmi N.B. Kedem, Zvi M. Lingamneni, Avinash Muntimadugu, Kirthi Krishna VISEN Center Rice University Houston TX United States Courant Institute of Mathematical Sciences New York University New York NY United States

ISBN: (纸本)9781605586267

The central theme of our work is the probabilistic and approximate design of embedded computing systems. This novel approach consists of two distinguishing aspects: (i) the design and implementation of embedded systems, using components which are susceptible to perturbations from various sources and (ii) a design methodology which consists of an exploration of a design space which characterizes the trade-off between quality of output and cost, to implement high performance and low energy embedded systems. In contrast with other work, our design methodology does not attempt to correct the errors introduced by components which are susceptible to perturbations, instead we design "good enough" systems. Our work has the potential to address challenges and impediments to Moore's law arising from material properties and manufacturing difficulties, which dictate that we shift from the current-day deterministic design paradigm to statistical and probabilistic designs of the future. In this paper, we provide a broad overview of our work on probabilistic and approximate design, present novel results in approximate arithmetic and its impact on digital signal processing algorithms, and sketch future directions for research. Copyright 2009 ACM.

关键词： embedded systems

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Message from the cases 2009 conference Chairs

Embedded Systems Week 2009 - 2009 International Conference o...

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embedded systems Week 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09 2009年 iii页

作者： Henkel, Joerg Parameswaran, Sri

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cases'07: Proceedings of the 2007 international conference on compilers, architecture, and synthesis for embedded systems

CASES'07: Proceedings of the 2007 International Conference o...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

ISBN: (纸本)9781595938268

The proceeding contains 36 papers. The topics discussed include: hierarchical coarse-grained stream compilation for software defined radio;an efficient framework for dynamic reconfiguration of instruction-set customization;compiler generation from structural architecture descriptions;lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms;light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs;supporting multithreading in configurable soft processor cores;a group-based wear-leveling algorithm for large-capacity flash memory storage systems;facilitating compiler optimizations through the dynamic mapping of alternate register structures;vertical object layout and compression for fixed heaps;software controlled memory layout reorganization for irregular array access patterns;a self-maintained memory module supporting DMM;compiling code accelerators for FPGAs;and multicore architectures.

关键词： embedded systems

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Non-intrusive dynamic application profiler for detailed loop execution characterization

Non-intrusive dynamic application profiler for detailed loop...

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Nair, Ajay Lysecky, Roman Department of Electrical and Computer Engineering University of Arizona United States

ISBN: (纸本)9781605584690

Application profiling - the process of monitoring an application to determine the frequency of execution within specific regions - is an essential step within the design process for many software and hardware systems. In this paper, we present an efficient innovative, non-intrusive dynamic application profiler (DAProf) capable of profiling an executing application by monitoring the application's short backwards branches and providing detailed profiling statistics for characterizing loop execution behavior. DAProf is ideally suited for hard-ware/software partitioning approaches in which detailed loop execution information is needed to provide accurate performance estimates. DAProf provides a profiling accuracy of greater than 90% with only an 11% area overhead compared to a small ARM9. Copyright 2008 ACM.

关键词： embedded systems

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Dynamic coprocessor management for FPGA-enhanced compute platforms

Dynamic coprocessor management for FPGA-enhanced compute pla...

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Huang, Chen Vahid, Frank Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems Univ. of California Irvine United States

ISBN: (纸本)9781605584690

Various commercial programmable compute platforms have their processor architecture enhanced with field-programmable gate arrays (FPGAs). In a common usage scenario, an application loads custom processors into the FPGA to speed up application execution compared to processor-only execution. Transient applications, changing application workloads, and limited FPGA capacity have led to a new problem of operating-system-controlled dynamic management of the loading of coprocessors into the FPGAs for best overall performance or energy. We define the Dynamic Coprocessor Management problem and provide a mapping to an online optimization problem known as Metrical Task systems. We introduce a robust heuristic, called the fading cumulative benefit (FCBenefit) heuristic, that outperforms other heuristics, including a previously developed one for MTS. For two distinct application sets, we generate numerous workloads and show that the FCBenefit heuristic provides best results across all considered workloads. In our simulations, the heuristic's results were within 9% of the offline optimal for performance, and within 3% for energy. The heuristic may be applicable to a wide variety of dynamic architecture management problems. Copyright 2008 ACM.

关键词： Field programmable gate arrays (FPGA)

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