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Single Appearance Schedule with Dynamic Loop Count for Minimum Buffer from Synchronous Dataflow Graphs

Single Appearance Schedule with Dynamic Loop Count for Minim...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Oh, Hyunok Dutt, Nikil Ha, Soonhoi Center for Embedded Computer Systems University of California Irvine Irvine CA 92697 United States School of EECS Seoul National University Seoul 151-742 Korea Republic of

ISBN: (纸本)159593149X

In this paper, we propose a new single appearance schedule for synchronous dataflow programs to minimize data memory and code memory size at the same time. When the software code is automatically synthesized from the dataflow program graphs, a single appearance schedule promises only one appearance of each node definition in the generated code. While several heuristics have been developed to find a single appearance schedule, they all have to pay significant amount of data memory overhead compared with a buffer optimal schedule. The key idea of the proposed technique is to make a dynamic decision of loop count to make a schedule quasi-static. The proposed quasi-static static schedule produces a single appearance schedule code with minimum data memory requirement. We prove that the proposed scheduling technique is optimal for a chain-structured graph in terms of data memory requirement while maintaining the single appearance schedule. The only penalty for the proposed technique is slight performance overhead of computing loop counts dynamically. Experimental results show that the proposed algorithm reduces 20% total memory with less than 1% performance overhead compared with the previous single appearance schedule algorithms for CD2DAT and non uniform filter bank applications. Copyright 2005 ACM.

关键词： Computer software

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Work-in-Progress: A Neuromorphic Approach of the Sound Source Localization Task in Real-Time embedded systems

Work-in-Progress: A Neuromorphic Approach of the Sound Sourc...

引用

embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Gutierrez-Galan, Daniel Pedro Jimenez-Fernandez, Juan Jimenez-Fernandez, Angel Tapiador-Morales, Ricardo Rios-Navarro, Antonio Linares-Barranco, Alejandro Univ Seville Seville Spain

ISBN: (纸本)9781450369244

Autonomous robots have become a very popular topic within the artificial intelligence field. These systems are able to perform difficult or risky tasks that could be dangerous when done by humans or trained animals. Vision is commonly considered the most relevant input sensor for autonomous robots and tracking systems. However, auditory information is also important in some specific situations where vision cannot provide any useful information when navigating. In this work, a spike-based model of the medial superior olive of the inner ear has been implemented in reconfigurable hardware for performing sound source localization in real time. Future works will focus on integrating this information with vision in order to achieve a fully bio-inspired autonomous tracking system.

关键词： Neuromorphic auditory sensor FPGA binaural sound localization real-time audio processing spike-based system

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On-the-Fly Load Data Value Tracing in Multicores

On-the-Fly Load Data Value Tracing in Multicores

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international conference on Compliers, architectures, and synthesis of embedded systems (cases)

作者： Ponugoti, Mounika Tewar, Amrish K. Milenkovic, Aleksandar Univ Alabama Dept Elect & Comp Engn 301 Sparkman Dr Huntsville AL 35899 USA

ISBN: (纸本)9781450344821

Software testing and debugging of modern multicore-based embedded systems is a challenging proposition because of growing hardware and software complexity, increased integration, and tightening time-to-market. To find more bugs faster, software developers of real-time embedded systems increasingly rely on on-chip trace and debug resources, including hefty on-chip buffers and wide trace ports. However, these resources often offer limited visibility of the system, increase the system cost, and do not scale well with a growing number of cores. This paper introduces mlvCFiat, a hardware/software mechanism for capturing and filtering load data value traces in multicores. It relies on first access tracking in data caches and equivalent modules in the software debugger to significantly reduce the number of trace events streamed out of the target platform. Our experimental evaluation explores the effectiveness of the proposed technique as a function of cache sizes, encoding mechanism, and the number of cores. The results show that mlvCFiat significantly reduces the total trace port bandwidth. The improvements relative to the existing Nexus-like load data value tracing range from 15 to 33 times for a single core and from 14 to 20 times for an octa core.

关键词： Real-time embedded systems Multicores Software testing and debugging Program Tracing

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Storage allocation for embedded processors 2

Storage allocation for embedded processors

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Sjödin, Jan Von Platen, Carl Uppsala University Department of Information Technology Box 337 UppsalaSE-751 05 Sweden IAR Systems Malmö Slagthus Carlsgatan 12 A MalmöSE-211 20 Sweden

ISBN: (纸本)1581133995

In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted to certain native pointer types. Different pointer types vary in size and cost. For example, it is typically cheaper to use an 8-bit pointer than a 16-bit pointer. The problem is to allocate data and select pointer types in the most effective way. Frequently accessed variables should be allocated in fast memory, and frequently used pointers and pointer expressions should be assigned cheap pointer types. Common practice is to perform this task manually. We present a model for storage allocation that is capable of describing architectures with irregular memory organization and with several native pointer types. This model is used in an integer linear programming (ILP) formulation of the problem. An ILP solver is applied to get an optimal solution under the model. We describe allocation of global variables and local variables with static storage duration. A whole program optimizing C compiler prototype was used to implement the allocator. Experiments were performed on the Atmel AVR 8-bit microcontroller [2] using small to medium sized C programs. The results varied with the benchmarks, with up to 8% improvement in execution speed and 10% reduction in code size. Copyright 2001 ACM.

关键词： Integer programming

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Compositional Analysis of Real-Time embedded systems

Compositional Analysis of Real-Time Embedded Systems

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14th Confernece on compilers, architectures and synthesis for embedded systems (cases)

作者： Phan, Linh T. X. Lee, Insup Sokolsky, Oleg Univ Penn Dept Comp & Informat Sci Philadelphia PA 19104 USA

ISBN: (纸本)9781450307130

This tutorial is concerned with various aspects of component-based design and compositional analysis of real-time embedded systems. It will first give an overview of component-based frameworks and their underlying principles. It will then go in-depth into abstraction methods for real-time components and techniques for computing their optimal interfaces, for both systems implemented on uniprocessor and multiprocessor platforms, as well as extensions to multi-mode systems. Besides theoretical aspects, the tutorial will also present an implementation of the compositional analysis framework on Xen virtualization and a demonstration of the CARTS toolset with several examples seeing the techniques in action. It will also include two case studies highlighting the utility of the framework, including the ARINC-653 avionics software and a smart-phone application. We will conclude the tutorial with a number of open challenges and research opportunities in this domain.

关键词： Real-time interfaces Compositional schedulability analysis Hierarchical scheduling Multi-mode systems

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Efficient longest executable path search for programs with complex flows and pipeline effects 2

Efficient longest executable path search for programs with c...

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Stappert, Friedhelm Ermedahl, Andreas Engblom, Jakob C-LAB Fürstenallee 11 Paderborn33102 Germany DoCS Uppsala University Box 325 UppsalaSE-751 05 Sweden IAR Systems AB Box 23051 UppsalaSE-750 23 Sweden

ISBN: (纸本)1581133995

Current development tools for embedded real-time systems do not efficiently support the timing aspect. The most important timing parameter for scheduling and system analysis is the Worst-Case Execution Time (WCET) of a program. This paper presents a fast and effective WCET calculation method that takes account of low-level machine aspects like pipelining and caches, and high-level program flow like loops and infeasible paths. The method is more efficient than previous path-based approaches, and can easily handle complex programs. By separating the low-level from the high-level analysis, the method is easy to retarget. Experiments confirm that speed does not sacrifice precision, and that programs with extreme numbers of potential execution paths can be analyzed quickly. Copyright 2001 ACM.

关键词： embedded systems

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Memory overflow protection for embedded systems using run-time checks, reuse and compression

Memory overflow protection for embedded systems using run-ti...

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Biswas, Surupa Simpson, Matthew Barua, Rajeev ECE Department Univ. of MD College Park United States Computer Engg. Department Clemson University United States

ISBN: (纸本)1581138903

Out-of-memory errors are a serious source of unreliability in most embedded systems. Applications run out of main memory because of the frequent difficulty of estimating the memory requirement before deployment, either because it depends on input data, or because certain language features prevent estimation. The typical lack of disks and virtual memory in embedded systems has two serious consequences when an out-of-memory error occurs. First, there is no swap space for the application to grow into, and the system crashes. Second, since protection from virtual memory is usually absent, the fact that a segment has exceeded its bounds is not even detected and hence no pre-crash remedial action is possible. This work improves system reliability in two ways. First it proposes a low-overhead system of run-time checks by which the out-of-memory errors are detected just before they will happen, by using carefully optimized compiler-inserted run-time check code. Such error detection enables the designer to incorporate system-specific remedial action, such as transfer to manual control, shutting down of non-critical tasks, or other actions. Second, this work proposes five related techniques that can grow the stack or heap segment after it is out of memory, into previously un-utilized space such as dead variables and space freed by compressed live variables. These techniques can avoid the out-of-memory error if the extra space recovered is enough to complete execution. Results from our benchmarks show that the overheads from the system of run-time checks for detecting memory overflow are extremely low: the run-time and code-size overheads are 1.1% and 0.09% on average. When the reuse functionality is included, the run-time and code-size overheads increase to only 3.2% and 2.33%, but the method is able to grow the stack or heap beyond its over-flow by an amount that ranges from 0.7% to 93.5% of the combined stack and heap size. Copyright 2004 ACM.

关键词： embedded systems

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Heterogeneous memory management for embedded systems 2

Heterogeneous memory management for embedded systems

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Avissar, Oren Barua, Rajeev Stewart, Dave ECE Department University of Maryland College ParkMD20742 United States Embedded Research Solutions LLC 9687F Gerwig Lane ColumbiaMD21046 United States

ISBN: (纸本)1581133995

This paper presents a technique for the efficient compiler management of software-exposed heterogeneous memory. In many lower-end embedded chips, often used in micro-controllers and DSP processors, heterogeneous memory units such as scratch-pad SRAM, internal DRAM, external DRAM and ROM are visible directly to the software, without automatic management by a hardware caching mechanism. Instead the memory units are mapped to different portions of the address space. Caches are avoided because of their cost and power consumption, and because they make it difficult to guarantee real-time performance. For this important class of embedded chips, the allocation of data to different memory units to maximize performance is the responsibility of the software. Current practice typically fileaves it to the programmer to partition the data among the different memory units. We present a compiler strategy that automatically partitions the data among the memory units. We show that this strategy is optimal among all static partitions for global and stack data, and a good heuristic for heap data. For global and stack data, the scheme is provably equal to or better than any other compiler scheme or set of programmer annotations. Preliminary results show the benefits of optimal allocation: with just 20% of the data in SRAM, the formulation is able to decrease the runtime by 39% on average for our benchmarks vs. allocating all data to slow memory, without any programmer involvement. For some programs, filess than 5% of data in SRAM achieves a similar speedup. Copyright 2001 ACM.

关键词： Static random access storage

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Highly energy and performance efficient embedded computing through approximately correct arithmetic: A mathematical foundation and preliminary experimental validation

Highly energy and performance efficient embedded computing t...

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Chakrapani, Lakshmi N.B. Muntimadugu, Kirthi Krishna Lingamneni, Avinash George, Jason Palem, Krishna V. Department of Computer Science Rice University Houston TX United States Department of Electrical and Computer Engineering Rice University Houston TX United States School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA United States Department of Computer Science Department of Electrical and Computer Engineering Rice University Houston TX United States California Institute of Technology United States

ISBN: (纸本)9781605584690

We develop a theoretical foundation to characterize a novel methodology for low energy and high performance DSP for embedded computing. Computing elements are operated at a frequency higher than that permitted by a conventionally correct circuit design, enabling a trade-off between error that is deliberately introduced, and the energy consumed. Similar techniques considered previously were relevant to deeply scaled future technology generations. Our work extends this idea to be applicable to current-day designs through: (i) a mathematically rigorous foundation characterizing a tradeoff between energy consumed and the quality of solution, and (ii) a means of achieving this trade off through very aggressive voltage scaling beyond that of a conventionally designed circuit. Through our "CMOS inspired" mathematical model, we show that our approach is better (by an exponential factor) than the conventional uniform voltage scaling approach for comparable computational speed or performance. We further establish through experimental study that a similar improvement by a factor of 3.4x to the SNR over conventional voltage-scaled approaches can be achieved in the context of the ubiquitous discrete Fourier transform. Copyright 2008 ACM.

关键词： Voltage scaling

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CaffePresso: An Optimized Library for Deep Learning on embedded Accelerator-based platforms

CaffePresso: An Optimized Library for Deep Learning on Embed...

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international conference on Compliers, architectures, and synthesis of embedded systems (cases)

作者： Hegde, Gopalakrishna Siddhartha Ramasamy, Nachiappan Kapre, Nachiket Nanyang Technol Univ Sch Comp Sci & Engn Singapore 639798 Singapore

ISBN: (纸本)9781450344821

Off-the-shelf accelerator-based embedded platforms offer a competitive energy-efficient solution for lightweight deep learning computations over CPU-based systems. Low-complexity classifiers used in power-constrained and performance-limited scenarios are characterized by operations on small image maps with 23 deep layers and few class labels. For these use cases, we consider a range of embedded systems with 5-20W power budgets such as the Xilinx ZC706 board (with MXP soft vector processor), NVIDIA Jetson TX1 (GPU), TI Keystone II (DSP) as well as the Adapteva Parallella board (custom multi-core with NoC). Deep Learning computations push the capabilities of these platforms to the limit through compute-intensive evaluations of multiple 2D convolution filters per layer, and high communication requirements arising from the movement of intermediate maps across layers. We present CaffePresso, a Caffe-compatible framework for generating optimized mappings of user-supplied ConvNet specifications to target various accelerators such as FPGAs, DSPs, GPUs, RISC-multicores. We use an automated code generation and auto-tuning approach based on knowledge of the ConvNet requirements, as well as platform-specific constraints such as on-chip memory capacity, bandwidth and ALU potential. While one may expect the Jetson TX1 + cuDNN to deliver high performance for ConvNet configurations, (1) we observe a flipped result with slower GPU processing compared to most other systems for smaller embedded-friendly datasets such as MNIST and CIFAR10, and (2) faster and more energy efficient implementation on the older 28nm TI Key-stone II DSP over the newer 20nm NVIDIA TX1 SoC in all cases.

关键词： Energy efficiency

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