检索结果-内蒙古大学图书馆

international conference on Compliers, architectures, and synthesis of embedded systems (cases)

作者： Hegde, Gopalakrishna Siddhartha Ramasamy, Nachiappan Kapre, Nachiket Nanyang Technol Univ Sch Comp Sci & Engn Singapore 639798 Singapore

ISBN: (纸本)9781450344821

Off-the-shelf accelerator-based embedded platforms offer a competitive energy-efficient solution for lightweight deep learning computations over CPU-based systems. Low-complexity classifiers used in power-constrained and performance-limited scenarios are characterized by operations on small image maps with 23 deep layers and few class labels. For these use cases, we consider a range of embedded systems with 5-20W power budgets such as the Xilinx ZC706 board (with MXP soft vector processor), NVIDIA Jetson TX1 (GPU), TI Keystone II (DSP) as well as the Adapteva Parallella board (custom multi-core with NoC). Deep Learning computations push the capabilities of these platforms to the limit through compute-intensive evaluations of multiple 2D convolution filters per layer, and high communication requirements arising from the movement of intermediate maps across layers. We present CaffePresso, a Caffe-compatible framework for generating optimized mappings of user-supplied ConvNet specifications to target various accelerators such as FPGAs, DSPs, GPUs, RISC-multicores. We use an automated code generation and auto-tuning approach based on knowledge of the ConvNet requirements, as well as platform-specific constraints such as on-chip memory capacity, bandwidth and ALU potential. While one may expect the Jetson TX1 + cuDNN to deliver high performance for ConvNet configurations, (1) we observe a flipped result with slower GPU processing compared to most other systems for smaller embedded-friendly datasets such as MNIST and CIFAR10, and (2) faster and more energy efficient implementation on the older 28nm TI Key-stone II DSP over the newer 20nm NVIDIA TX1 SoC in all cases.

关键词： Energy efficiency

来源：评论

学校读者我要写书评

暂无评论

Efficient design space exploration in PICO

Efficient design space exploration in PICO

引用

Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Abraham, Santosh G. Rau, B.R. Hewlett-Packard Laboratories Palo Alto CA 94304 United States

ISBN: (纸本)1581133383

Automated design tools must understand and exploit the hierarchical structure of large design spaces. We have developed a general methodology for decomposing system design spaces into smaller component design spaces, followed by component-level evaluation, filtering, recomposition and system-level evaluation. This methodology greatly reduces the time and cost of design space exploration, since the typical number of system-level evaluations is greatly reduced. This paper describes the application of our decomposition methodology in the context of PICO. PICO is a design space exploration system that automatically generates embedded designs consisting of a stylized processor, hardware accelerator and a cache hierarchy, each customized to a benchmark. First, PICO splits the specified system design space into smaller design spaces, one for each of the components, viz. processor, accelerator and data/instruction/unified caches. PICO further partitions each component design space into predicated design spaces, so that all designs in a predicated design space satisfy a specified predicate. PICO uses component-level evaluations to identify the performance-cost optimal component-level Pareto designs in each predicated design space. PICO generates all compositions of Pareto designs from compatible predicated design spaces and uses a system-level evaluation to identify the Pareto designs at the system level. For reasonable design spaces, PICO reduces the design exploration time by over four orders of magnitude compared to an exhaustive approach.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

Energy Efficient Hybrid Display and Predictive Models for embedded and Mobile systems

Energy Efficient Hybrid Display and Predictive Models for Em...

引用

ACM international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Wen, Yuanfeng Liu, Ziyi Shi, Weidong Jiang, Yifei Cheng, Albert M. K. Le, Khoa Univ Houston Dept Comp Sci Houston TX 77004 USA

ISBN: (纸本)9781450314244

Electrophoretic displays (EPDs) and organic light emitting diode (OLEDs) are two key technologies used in mobile devices. In this paper, we propose the design of an integrated hybrid display combining a transparent OLED (TOLED) and a low power EPD, which is adaptive to show contents of a frame partially on either the TOLED or the EPD. A windows-based predictive model and a calibration algorithm on TOLED are introduced to decide how frame contents can be split between the two displays for achieving the best tradeoff between power reduction and user experiences. A simulation environment that can estimate both the energy consumption and optical properties of the proposed hybrid display is set up based on actual physical measurements. Simulation results show that the predictive model can make right decisions on choosing proper displays in over 90% of the test cases, and this new display design can save over 70% power under many mobile application contexts and still support contents that require fast update rates.

关键词： EPDs OLEDs Hybrid Display Predictive Model Calibration

来源：评论

学校读者我要写书评

暂无评论

Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization

Synterface: Efficient Chip-to-World Interfacing for Flow-Bas...

引用

embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Sridhar, Aditya Ibrahim, Mohamed Chakrabarty, Krishnendu Duke Univ Dept Elect & Comp Engn 130 Hudson Hall Durham NC 27708 USA

Flow-based microfluidic biochips can be used to perform bioassays by manipulating a large number of on-chip valves. These biochips are increasingly used today for biomolecular recognition, single-cell screening, and point-of-care disease diagnostics, and design-automation solutions for flow-based microfluidics enable the mapping and optimization of bimolecular protocols and software-based valve control. However, a key problem that has not received adequate attention is chip-to-world interfacing, which requires the use of off-chip control equipment to provide control signals for the on-chip valves. This problem is exacerbated by the increase in the number of valves as chips get more complex. To address the interfacing problem, we present an efficient pin-count minimization (synthesis) problem, referred to as Synterface, which uses on-chip microfluidic logic gates and optimization based on concepts from linear algebra. We present results to show that Synterface significantly reduces pin-count and simplifies the external interface for flow-based microfluidics.

关键词： Microfluidic biochips chip-to-world interfacing synthesis logic gates

来源：评论

学校读者我要写书评

暂无评论

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Compiler-decided dynamic memory allocation for scratch-pad b...

引用

cases 2003: international conference on compilers, architecture, and synthesis for embedded systems

作者： Udayakumaran, Sumesh Barua, Rajeev Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 United States

ISBN: (纸本)1581136765

This paper presents a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in energy consumption, area and overall runtime, even with a simple allocation scheme [4]. Existing scratch-pad allocation methods are of two types. First, software-caching schemes emulate the workings of a hardware cache in software. Instructions are inserted before each load/store to check the software-maintained cache tags. Such methods in-cur large overheads in runtime, code size, energy consumption and SRAM space for tags and deliver poor real-time guarantees just like hardware caches. A second category of algorithms partitions variables at compile-time into the two banks. For example, our previous work in [3] derives a provably optimal static allocation for global and stack variables and achieves a speedup over all earlier methods. However, a drawback of such static allocation schemes is that they do not account for dynamic program behavior. It is easy to see why a data allocation that never changes at runtime cannot achieve the full locality benefits of a cache. In this paper we present a dynamic allocation method for global and stack data that for the first time, (i) accounts for changing program requirements at runtime (ii) has no software-caching tags (iii) requires no run-time checks (iv) has extremely low overheads, and (v) yields 100% predictable memory access times. In this method data that is about to be accessed frequently is copied into the SRAM using compiler-inserted code at fixed and infrequent points in the program. Earlier data is evicted if necessary. When compared to a provably optimal static allocation our results show runtime reductions ranging from 11% to 38%, averaging 31.2%, using no additional hardware

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

Efficient Tracing Methodology Using Automata Processor

Efficient Tracing Methodology Using Automata Processor

引用

作者： Seo, Minjun Kurdahi, Fadi Univ Calif Irvine Ctr Embedded Cyber Phys Syst Irvine CA 92617 USA

Tracing or trace interface has been used in various ways to find system defects or bugs. As embedded systems are increasingly used in safety-critical applications, tracing can provide useful information during system execution at runtime. Non-intrusive tracing that does not affect system performance has become especially important, but unfortunately, the biggest obstacle to this approach was the vast amount of real-time trace data, making it challenging to address complex requirements with relatively limited hardware implementations. Automata processors can be programmed with a memory-like structure of automata and have a structure specific to streaming data, large capacity, and parallel processing functions. This paper promotes the idea of high-level system-on-chip monitoring using automata processors. We used a safety-critical pacemaker application in the experiments, described timed automata (TA)-based requirements, and tested intentionally injected 4,000 random failures. The TA model converted for Automata Processor to monitor system, correctness, and safety properties achieved 100% failure detection rate in the experiment, and the detected failure is reported as fast enough to allow enough extent for failure recovery.

关键词： Tracing tracing methodology runtime verification

来源：评论

学校读者我要写书评

暂无评论

IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of embedded systems

引用

ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 1-22页

作者： Smirnov, Fedor Pourmohseni, Behnaz Glass, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Cauerstr 11 D-91058 Erlangen Germany Univ Ulm Albert Einstein Allee 11 D-89081 Ulm Germany

Design Space Exploration (DSE) techniques for complex embedded systems must cope with a huge variety of applications and target architectures as well as a wide spectrum of objectives and constraints. In particular, existing design automation approaches are either problem-independent, in that they do not exploit any knowledge about the optimization problem at hand, or are tailored to specific a priori assumptions about the problem and/or a specific set of design objectives. While the latter are only applicable within a very limited scope of design problems, the former may struggle to deliver high-quality solutions for problems with large design spaces and/or complex design objectives. As a remedy, we propose Importance-Guided Order Rearrangement (IGOR) as a novel approach for DSE of embedded systems. Instead of relying on an a priori problem knowledge, IGOR uses a machine-learning-inspired technique to dynamically analyze the importance of design decisions, i.e., the impact that these decisions-within the specific problem that is being optimized-have on the quality of explored problem solutions w.r.t. the given design objectives. Throughout the DSE, IGOR uses this information to guide the optimization towards the most promising regions of the design space. Experimental results for a variety of applications from different domains of embedded computing and for different optimization scenarios give evidence that the proposed approach is both scalable and adaptable, as it can be used for the optimization of systems described by several thousands constraints, where it outperforms both problem-specific and problem-independent optimization approaches and achieves e-dominance improvements of up to 95%.

关键词： Design space exploration constrained combinatorial problems multi-objective optimization embedded systems

来源：评论

学校读者我要写书评

暂无评论

Memory allocation for embedded systems with a compile-time-unknown scratch-pad size

Memory allocation for embedded systems with a compile-time-u...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Nguyen, Nghi Dominguez, Angel Barua, Rajeev Electrical and Computer Engineering Department University of Maryland College Park MD 20742 United States

ISBN: (纸本)159593149X

This paper presents the first memory allocation scheme for embedded systems having scratch-pad memory whose size is unknown at compile time. A scratch-pad memory (SPM) is a fast compiler-managed SRAM that replaces the hardware-managed cache. Its uses are motivated by its better real-time guarantees as compared to cache and by its significantly lower overheads in energy consumption, area and access time. Existing data allocation schemes for SPM all require that the SPM size be known at compile-time. Unfortunately, the resulting executable is tied to that size of SPM and is not portable to processor implementations having a different SPM size. Such portability would be valuable in situations where programs for an embedded system are not burned into the system at the time of manufacture, but rather are downloaded onto it during deployment, either using a network or portable media such as memory sticks. Such post-deployment code updates are common in distributed networks and in personal hand-held devices. The presence of different SPM sizes in different devices is common because of the evolution in VLSI technology across years. The result is that SPM cannot be used in such situations with downloaded code. To overcome this limitation, this work presents a compiler method whose resulting executable is portable across SPMs of any size. The executable at run-time places frequently used objects in SPM;it considers code, global variables and stack variables for placement in SPM. The allocation is decided by modified loader software before the program is first run and once the SPM size can be discovered. The loader then modifies the program binary based on the decided allocation. To keep the overhead low, much of the pre-processing for the allocation is done at compile-time. Results show that our benchmarks average a 36% speed increase versus an all-DRAM allocation, while the optimal static allocation scheme, which knows the SPM size at compile-time and is thus an un-achievabl

关键词： Storage allocation (computer)

来源：评论

学校读者我要写书评

暂无评论

Power and Thermal Management in Massive Multicore Chips: Theoretical Foundation meets Architectural Innovation and Resource Allocation

Power and Thermal Management in Massive Multicore Chips: The...

引用

international conference on Compliers, architectures, and synthesis of embedded systems (cases)

作者： Bogdan, Paul Pande, Partha Pratim Amrouch, Hussam Shafique, Muhammad Henkel, Joerg Univ Southern Calif Dept Elect Engn 3740 McClintock Ave Los Angeles CA 90089 USA Washington State Univ Sch EECS 355 NE Spokane St EME 102 Pullman WA 99164 USA Karlsruhe Inst Technol Chair Embedded Syst D-76131 Karlsruhe Germany

ISBN: (纸本)9781450344821

Continuing progress and integration levels in silicon technologies make possible complete end-user systems consisting of extremely high number of cores on a single chip targeting either embedded or high-performance computing. However, without new paradigms of energy-and thermally-efficient designs, producing information and communication systems capable of meeting the computing, storage and communication demands of the emerging applications will be unlikely. The broad topic of power and thermal management of massive multicore chips is actively being pursued by a number of researchers worldwide, from a variety of different perspectives, ranging from workload modeling to efficient on-chip network infrastructure design to resource allocation. Successful solutions will likely adopt and encompass elements from all or at least several levels of abstraction. Starting from these ideas, we consider a holistic approach in establishing the Power-Thermal-Performance (PTP) trade-offs of massive multicore processors by considering three inter-related but varying angles, viz., on-chip traffic modeling, novel Networks-on-Chip (NoC) architecture and resource allocation/mapping

关键词： Resource allocation

来源：评论

学校读者我要写书评

暂无评论

MTSS: Multi task stack sharing for embedded systems

MTSS: Multi task stack sharing for embedded systems

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Middha, Bhuvan Simpson, Matthew Barua, Rajeev Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 United States

ISBN: (纸本)159593149X

Out-of-memory errors are a serious source of unreliability in most embedded systems [22]. Applications run out of main memory because of the frequent difficulty of estimating the memory requirement before deployment, either because it depends on input data, or because certain language features prevent estimation. The typical lack of disks and virtual memory in embedded systems has a serious consequence when an out-of-memory error occurs. Since there is no swap space for the application to grow into, the system crashes if its memory footprint is exceeded by even one byte. This work improves system reliability for multi-tasking embedded systems by proposing MTSS, a multi-task stack sharing technique, that grows the stack of a particular task into other tasks in the system after it has overflown its bounds. This technique can avoid the out-of-memory error if the extra space recovered is enough to complete execution. Experiments show that MTSS, on an average, is able to recover 47% of the stack space allocated to the overflowing task in the free space of other tasks. Therefore, even if we underestimate the stack size of a particular task by 47% on an average, it will still run to completion by reusing stack in other task's stack. Alternatively, MTSS can also be used for decreasing the physical memory for an embedded system by reducing the initial memory allocated to each of the tasks and recovering the deficit by sharing stack with other tasks. Results show that MTSS used in this way can be used to reduce the memory required in multi-tasking embedded systems by 18% on an average, thus reducing the memory cost of the system. MTSS also offers good real time guarantees, since it uses a paging system that never incurs an episodic increase in run-time. The overheads of MTSS are extremely low: the run-time and code size overheads are 1.8% and 2.6% on an average, making it a feasible method for increasing system reliability and reducing the memory footprint of embedded systems

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：