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Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Multiple sleep mode leakage control for cache peripheral cir...

embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Homayoun, Houman Makhzan, Mohammad Veidenbaum, Alex Center for Embedded Computer Systems University of California Irvine CA United States Department of Electrical and Computer Engineering University of California Irvine CA United States

ISBN: (纸本)9781605584690

This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral circuits, which according to recent studies account for a considerable amount of cache leakage. At circuit level, we propose a novel design with multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and wakeup delay. Architectural control is proposed to decide "when and how" to use these different low-leakage modes using cache miss information to guide its action. This control is based on simple state machines that do not impact area or power consumption and can thus be used even in the resource constrained processors. Experimental results indicate that proposed techniques can keep the L1 cache peripherals in one of the low-power modes for more than 85% of total execution time, on average. This translates to an average leakage power reduction of 50% for 65nm technology. The DL1 cache energy-delay product is reduced, on average, by 20%. Copyright 2008 ACM.

关键词： Timing circuits

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Multi-granularity sampling for simulating concurrent heterogeneous applications

Multi-granularity sampling for simulating concurrent heterog...

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Tawk, Melhem Ibrahim, Khaled Z. Niar, Smail University of Valenciennes Hipeac Network of Excellence 59313 Valenciennes Cedex 9 France IRISA/INRIA Campus de Beaulieu 35042 Rennes France INRIA Lille-Nord-Europe Hipeac Network of Excellence 40 Avenue Halley 59650 Villeneuve d'ASCQ France

ISBN: (纸本)9781605584690

Detailed or cycle-accurate/bit-accurate (CABA) simulation is a critical phase in the design flow of embedded systems. However, with increasing system complexity, full detailed simulation is prohibitively slower than the hardware being simulated. In this paper, we present an approach that uses the sampling technique to speed up the design flow of Multiprocessor System-on-Chip (MPSoC) systems. Based on the dynamic behavior of the applications running concurrently, our method dynamically chooses between multiple granularities of the sampling phase. The similarities of the execution phases for all possible granularities are first analyzed, then transitions between phase overlaps are discretized. To facilitate the detection of repetitions, one phase, with an appropriate granularity, is chosen per process. Unlike most other proposals, the associated performance is usually accurate enough not to need repeated resampling. The use of checkpointing in conjunction with our approach is simplified because the amount of the needed disk space is significantly reduced. Experimental results show that the simulation of concurrent heterogeneous applications can be accelerated by a factor of up to 60x, while maintaining an average performance estimation error lower than 5%. Copyright 2008 ACM.

关键词： embedded systems

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Advanced conservative and optimistic register coalescing

Advanced conservative and optimistic register coalescing

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Bouchez, Florent Darte, Alain Rastello, Fabrice Compsys Team LIP UMR 5668 CNRS - ENS Lyon - UCB Lyon - Inria France

ISBN: (纸本)9781605584690

In the context of embedded systems, it is crucial to minimize memory transfers to reduce latency and power consumption. Stack access due to variable spilling during register allocation can be significantly reduced using aggressive live-range splitting. However, without a good (conservative) coalescing technique, the benefit of a good spilling may be lost due to the many register-to-register moves introduced. The challenge is thus to find a good trade-off between a too aggressive strategy that could make the interference graph uncolorable without more spilling, and a too conservative strategy that preserves colorability but leaves unnecessary moves. Two main approaches are "iterated register coalescing" by George and Appel and "optimistic coalescing" by Park and Moon. The first coalesces moves one by one conservatively. The second coalesces moves regardless of the colorability, then undo coalescings to reduce spilling. Focusing on greedy-k-colorable graphs - which are usually obtained after all spill decisions and, possibly, some split decisions - we show how these two approaches can be improved, optimistic coalescing with a more involved de-coalescing phase, incremental coalescing with a less pessimistic conservative technique. Unlike previous experiments, our results show that optimistic strategies do not outperform conservative ones. Our incremental conservative coalescing performs even better than our improved de-coalescing scheme and leads to about 15% improvement compared to the state-of-the-art optimistic coalescing. Copyright 2008 ACM.

关键词： embedded systems

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Highly energy and performance efficient embedded computing through approximately correct arithmetic: A mathematical foundation and preliminary experimental validation

Highly energy and performance efficient embedded computing t...

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embedded systems Week 2008 - 2008 international conference on compilers, architecture and synthesis for embedded systems, cases'08

作者： Chakrapani, Lakshmi N.B. Muntimadugu, Kirthi Krishna Lingamneni, Avinash George, Jason Palem, Krishna V. Department of Computer Science Rice University Houston TX United States Department of Electrical and Computer Engineering Rice University Houston TX United States School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA United States Department of Computer Science Department of Electrical and Computer Engineering Rice University Houston TX United States California Institute of Technology United States

ISBN: (纸本)9781605584690

We develop a theoretical foundation to characterize a novel methodology for low energy and high performance DSP for embedded computing. Computing elements are operated at a frequency higher than that permitted by a conventionally correct circuit design, enabling a trade-off between error that is deliberately introduced, and the energy consumed. Similar techniques considered previously were relevant to deeply scaled future technology generations. Our work extends this idea to be applicable to current-day designs through: (i) a mathematically rigorous foundation characterizing a tradeoff between energy consumed and the quality of solution, and (ii) a means of achieving this trade off through very aggressive voltage scaling beyond that of a conventionally designed circuit. Through our "CMOS inspired" mathematical model, we show that our approach is better (by an exponential factor) than the conventional uniform voltage scaling approach for comparable computational speed or performance. We further establish through experimental study that a similar improvement by a factor of 3.4x to the SNR over conventional voltage-scaled approaches can be achieved in the context of the ubiquitous discrete Fourier transform. Copyright 2008 ACM.

关键词： Voltage scaling

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Highly-cited ideas in system codesign and synthesis 08

Highly-cited ideas in system codesign and synthesis

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embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on Hardware/Software Codesign and System synthesis, CODES+ISSS 2008

作者： Vahid, Frank Givargis, Tony Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems UC Irvine United States Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781605584706

We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/software codesign and system synthesis community. Citations, meaning non-self-citations only, were considered from all papers known to Google Scholar, as well as only from subsequent CODES/ISSS papers. We list the most-cited CODES/ISSS papers of each year, summarizing their topics, and discussing common features of those papers. For comparison purposes, we also measured citations for the computer architecture community's ISCA and MICRO conferences, and for the field-programmable gate array community's FPGA and FCCM conferences. We point out several interesting differences among the citation patterns of the three communities. Copyright 2008 ACM.

关键词： Computer architecture

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embedded architecture description language

Embedded architecture description language

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32nd Annual IEEE international Computer Software and Applications conference, COMPSAC 2008

作者： Li, Juncao Pilkington, Nicholas T. Xie, Fei Liu, Qiang Department of Computer Science Portland State University Portland OR 97207 United States School of Software Tsinghua University Beijing 100084 China

ISBN: (纸本)9780769532622

In the state-of-the-art hardware/software (HW/SW) co-design of embedded systems, there is a lack of sufficient support for architectural specifications across HW/SW boundaries. Such an architectural specification ought to capture both hardware and software components and their interactions, and facilitate effective design exploitation of HW/SW trade-offs and scalable HW/SW co-verification. In this paper, we present the embedded architecture description language (EADL). It is based on a component model for embedded systems that unifies hardware and software components. EADL does not dictate execution and interface semantics of hardware and software components while supporting flexible platform-oriented semantics instantiation. EADL supports concise representation of embedded system architectures and also formulation of architectural patterns of embedded systems. Besides facilitating design reuse, architectural patterns also facilitate verification reuse via association of property templates with these patterns. Effectiveness of EADL has been demonstrated by its successful application in integrating component-based co-design, cosimulation, co-verification, and system synthesis. © 2008 IEEE.

关键词： Semantics

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26th IFIP WG 6.1 international conference on Formal Methods for Networked and Distributed systems, FORTE 2006

26th IFIP WG 6.1 International Conference on Formal Methods ...

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2nd international conference on Autonomous Infrastructure, Management and Security, AIMS 2008

ISBN: (纸本)3540705864

The proceedings contain 23 papers. The special focus in this conference is on Invited talks, Services, Middleware, Composition and synthesis, Logics, Symbolic verification - slicing, Unified modeling languages, Petri nets, Parameterized verification, Real time, Testing, . The topics include: Modelling of complex software systems: a reasoned overview;semantic-based development of service-oriented systems;JSCL: a middleware for service coordination;analysis of realizability conditions for web service choreographies;web cube;presence interaction management in SIP SOHO architecture;formal analysis of dynamic, distributed file-system access controls;analysing the MUTE anonymous file-sharing system using the pi-calculus;towards fine-grained automated verification of publish-subscribe architectures;a LOTOS framework for middleware specification;automatic synthesis of assumptions for compositional model checking;refined interfaces for compositional verification;on distributed program specification and synthesis in architectures with cycles;generalizing the submodule construction techniques for extended state machine models;decidable extensions of hennessy-milner logic;symbolic verification of communicating systems with probabilistic message losses: liveness and fairness;a new approach for concurrent program slicing;reducing software architecture models complexity: a slicing and abstraction approach;branching time semantics for UML 2.0 sequence diagrams;formalizing collaboration goal sequences for service choreography;composition of use cases using synchronization and model checking;PN standardisation: a survey;optimized colored nets unfolding;liveness by invisible invariants;extending EFSMs to specify and test timed systems with action durations and timeouts;and scenario-based timing consistency checking for time petri nets.

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embedded systems week

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IEEE Design and Test of Computers 2007年第1期24卷 102+1页

作者： Bergamaschi, Reinaldo A. IBM T.J. Watson Research Center

This report discusses embedded systems Week 2006, which took place 22-27 October in Seoul. ESWEEK 2006 included three parallel conferences: CODES+ISSS (the international conference on Hardware/Software Codesign and System synthesis), EMSOFT (the international conference on embedded Software), and cases (the international conference on compilers, architecture, and synthesis for embedded systems). Almost 500 people attended. ESWEEK 2007 will be held in Salzburg, Austria, from 30 September to 5 October. © 2007 IEEE.

关键词： embedded systems

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Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems

Performance evaluation and optimization of dual-port SDRAM a...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Yang, Hoeseok Kim, Sungchan Park, Hae-Woo Kim, Jinwoo Ha, Soonhoi School of EECS Seoul National University Korea Republic of

ISBN: (纸本)9781595938268

Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to keep memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target application: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we enable simultaneous accesses to different blocks and achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result that we achieve about 20-50% performance gain compared to the base DPSDRAM architecture. Copyright 2007 ACM.

关键词： Random access storage

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Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs

Light-weight synchronization for inter-processor communicati...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Yang, Chengmo Orailoglu, Alex Computer Science and Engineering Department Unversity of California San Diego 9500 Gilman Drive San Diego CA 92093 United States

ISBN: (纸本)9781595938268

The advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of the ample hardware resources requires applications to be decomposed into finegrained threads, engendering in turn a large amount of interprocessor communications. While finegrained on-chip interconnects can reduce the data transfer overhead, the traditional synchronization mechanisms, such as spin locks and barriers, still cause significant contention in polling shared variables. To overcome this issue, in this paper we propose a lightweight distributed synchronization mechanism which statically encodes the semantically correct order of accesses to each shared variable. A sharp reduction in the number of code bits is attained through a reference coloring algorithm, which furthermore enables an implementation within negligible hardware overhead. Copyright 2007 ACM.

关键词： Synchronization

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