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embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Duerr, Marco Von Der Brueggen, Georg Chen, Kuan-Hsun Chen, Jian-Jia TU Dortmund Univ Dortmund Germany

A cause-effect chain is used to define the logical order of data dependent tasks, which is independent from the execution order of the jobs of the (periodic/sporadic) tasks. Analyzing the worst-case End-to-End timing behavior, associated to a cause-effect chain, is an important problem in embedded control systems. For example, the detailed timing properties of modern automotive systems are specified in the AUTOSAR Timing Extensions. In this paper, we present a formal End-to-End timing analysis for distributed systems. We consider the two most important End-to-End timing semantics, i.e., the button-to-action delay (termed as the maximum reaction time) and the worst-case data freshness (termed as the maximum data age). Our contribution is significant due to the consideration of the sporadic behavior of job activations, whilst the results in the literature have been mostly limited to periodic activations. The proof strategy shows the (previously unexplored) connection between the reaction time (data age, respectively) and immediate forward ( backward, respectively) job chains. Our analytical results dominate the state of the art for sporadic task activations in distributed systems and the evaluations show a clear improvement for synthesized task systems as well as for a real world automotive benchmark setting.

关键词： End-to-End timing analysis distributed systems sporadic cause-effect chains embedded control systems

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cases 2023 Program Committee

CASES 2023 Program Committee

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

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Deriving Equations from Sensor Data Using Dimensional Function synthesis

Deriving Equations from Sensor Data Using Dimensional Functi...

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作者： Wang, Youchao Willis, Sam Tsoutsouras, Vasileios Stanley-Marbell, Phillip Univ Cambridge 9 JJ Thomson Ave Cambridge CB3 0FA England

We present a new method for deriving functions that model the relationship between multiple signals in a physical system. The method, which we call dimensional function synthesis, applies to data streams where the dimensions of the signals are known. The method comprises two phases: a compile-time synthesis phase and a subsequent calibration using sensor data. We implement dimensional function synthesis and use the implementation to demonstrate efficiently summarizing multi-modal sensor data for two physical systems using 90 laboratory experiments and 10 000 synthetic idealized measurements. We evaluate the performance of the compile-time phase of dimensional function synthesis as well as the calibration phase overhead, inference latency, and accuracy of the models our method generates. The results show that our technique can generate models in less than 300 ms on average across all the physical systems we evaluated. When calibrated with sensor data, our models outperform traditional regression and neural network models in inference accuracy in all the cases we evaluated. In addition, our models perform better in training latency (over 8660x improvement) and required arithmetic operations in inference (over 34x improvement). These significant gains are largely the result of exploiting information on the physics of signals that has hitherto been ignored.

关键词： Machine learning dimensional analysis sensor data fusion

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Revisiting Level-0 Caches in embedded Processors

Revisiting Level-0 Caches in Embedded Processors

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ACM international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Duong, Nam Kim, Taesu Zhao, Dali Veidenbaum, Alexander V. Univ Calif Irvine Dept Comp Sci Irvine CA 92717 USA

ISBN: (纸本)9781450314244

Level-0 (L0) caches have been proposed in the past as an inexpensive way to improve performance and reduce energy consumption in resource-constrained embedded processors. This paper proposes new L0 data cache organizations using the assumption that an L0 hit/miss determination can be completed prior to the L1 access. This is a realistic assumption for very small L0 caches that can nevertheless deliver significant miss rate and/or energy reduction. The key issue for such caches is how and when to move data between the L0 and L1 caches. The first new cache, a flow cache, targets a conflict miss reduction in a direct-mapped L1 cache. It offers a simpler hardware design and uses on average 10% less dynamic energy than the victim cache with nearly identical performance. The second new cache, a hit cache, reduces the dynamic energy consumption in a set-associative L1 cache by 30% without impacting performance. A variant of this policy reduces the dynamic energy consumption by up to 50%, with 5% performance degradation.

关键词： cache design level-0 cache migration policy conflict misses dynamic energy

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Message from the cases 2023 Program Chairs

Message from the CASES 2023 Program Chairs

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

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From ESL 2010 to ESL 2015 10

From ESL 2010 to ESL 2015

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Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

作者： Jeremiassen, Tor Martin, Grant Kogel, Tim Donlin, Adam Takach, Andres Chatha, Karam Texas Instruments United States Tensilica United States Synopsys United States Xilinx United States Mentor Graphics United States Arizona State University United States

ISBN: (纸本)9781605589053

In 2010, a wave of consolidation swept over the Electronic System Level (ESL) design industry. It brought ESL providers together with mainstream EDA houses and created opportunities for new ESL ventures. This paper contains short summaries of presentations in a special session focusing on the future of ESL. The session has two goals: the first is to present the state of the art in ESL tools and practice and, second, share a vision of the technical challenges that the next generation of ESL companies should address. The session includes a mix of perspectives from both ESL solution vendors and end-users and touches all all four ESL use cases: software virtual platforms, performance analysis, high level synthesis and verification.

关键词： High level synthesis

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Will My Program Break on This Faulty Processor?: Formal Analysis of Hardware Fault Activations in Concurrent embedded Software

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 1-21页

作者： Bajczi, Levente Voros, Andras Molnar, Vince Budapest Univ Technol & Econ Fault Tolerant Syst Res Grp Dept Measurement & Informat Syst POB 91 H-1521 Budapest Hungary MTA BME Lendulet Cyber Phys Syst Res Grp Budapest Hungary

Formal verification is approaching a point where it will be reliably applicable to embedded software. Even though formal verification can efficiently analyze multi-threaded applications, multi-core processors are often considered too dangerous to use in critical systems, despite the many benefits they can offer. One reason is the advanced memory consistency model of such CPUs. Nowadays, most software verifiers assume strict sequential consistency, which is also the naive view of programmers. Modernmulti-core processors, however, rarely guarantee this assumption by default. In addition, complex processor architectures may easily contain design faults. Thanks to the recent advances in hardware verification, these faults are increasingly visible and can be detected even in existing processors, giving an opportunity to compensate for the problem in software. In this paper, we propose a generic approach to consider inconsistent behavior of the hardware in the analysis of software. Our approach is based on formal methods and can be used to detect the activation of existing hardware faults on the application level and facilitate their mitigation in software. The approach relies heavily on recent results of model checking and hardware verification and offers new, integrative research directions. We propose a partial solution based on existing model checking tools to demonstrate feasibility and evaluate their performance in this context.

关键词： Fault analysis memory consistency model concurrent litmus test

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ILP-based Modulo Scheduling for High-level synthesis

ILP-based Modulo Scheduling for High-level Synthesis

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international conference on Compliers, architectures, and synthesis of embedded systems (cases)

作者： Oppermann, Julian Koch, Andreas Reuter-Oppermann, Melanie Sinnen, Oliver Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany Karlsruhe Inst Technol Discrete Optimizat & Logist Grp Karlsruhe Germany Univ Auckland Parallel & Reconfigurable Comp Grp Auckland New Zealand

ISBN: (纸本)9781450344821

In high-level synthesis, loop pipelining is a technique to improve the throughput and utilisation of hardware datapaths by starting new loop iterations after a fixed amount of time, called the initiation interval (II), allowing to overlap subsequent iterations. The problem is to find the smallest II and corresponding operation schedule that fulfils all data dependencies and resource constraints, both of which are usually found by modulo scheduling. We propose Moovac', a novel integer linear program (ILP) formulation of the modulo scheduling problem based on overlap variables to model exact resource constraints. Given enough time, Moovac will find a mimimum-II solution. This is in contrast to Canis' state-of-the-art Modulo SDC approach, which requires heuristic simplifications of the resource constraints. Moovac can thus be used as a reference to evaluate heuristics, or in a time-limited mode as a heuristic itself to provide a best-so-far solution. We schedule kernels from the CHStone and MachSuite benchmarks for loop pipelining with Moovac, Modulo SDC and a prior exact formulation by Eichenberger. Moovac has competitive performance in its time-limited mode, and delivers better results faster than the Modulo SDC scheduler for some loops. Often its structure leads to quicker solution times than Eichenberger's formulation. Using the Moovac-computed optimal solutions as a reference, we can confirm that the Modulo SDC heuristic is indeed capable of finding optimal or near-optimal solutions for the majority of small-to medium-sized loops. However, for larger loops the two algorithms begin to diverge, with Moovac often being significantly faster to prove the infeasibility of a candidate II. This can be exploited by running both schedulers synergistically, leading to a quicker convergence to the final II.

关键词： High level synthesis

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Special Session-Non-Volatile Memories: Challenges and Opportunities for embedded System architectures with Focus on Machine Learning Applications

Special Session-Non-Volatile Memories: Challenges and Opport...

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2023 international conference on compilers, architecture, and synthesis for embedded systems, cases 2023

作者： Henkel, Jorg Siddhu, Lokesh Bauer, Lars Teich, Jurgen Wildermann, Stefan Tahoori, Mehdi Mayahinia, Mahta Castrillon, Jeronimo Khan, Asif Ali Farzaneh, Hamid De Lima, Joao Paulo C. Chen, Jian-Jia Hakert, Christian Chen, Kuan-Hsun Yang, Chia-Lin Cheng, Hsiang-Yun Germany Friedrich-Alexander-Universität Erlangen-Nürnberg Germany TU Dresden Germany TU Dortmund University Germany Lamarr Inst. for ML and AI Germany University of Twente Netherlands National Taiwan University Taiwan Academia Sinica Taiwan

ISBN: (纸本)9798400702907

This paper explores the challenges and opportunities of integrating non-volatile memories (NVMs) into embedded systems for machine learning. NVMs offer advantages such as increased memory density, lower power consumption, non-volatility, and compute-in-memory capabilities. The paper focuses on integrating NVMs into embedded systems, particularly in intermittent computing, where systems operate during periods of available energy. NVM technologies bring persistence closer to the CPU core, enabling efficient designs for energy-constrained scenarios. Next, computation in resistive NVMs is explored, highlighting its potential for accelerating machine learning algorithms. However, challenges related to reliability and device non-idealities need to be addressed. The paper also discusses memory-centric machine learning, leveraging NVMs to overcome the memory wall challenge. By optimizing memory layouts and utilizing probabilistic decision tree execution and neural network sparsity, NVM-based systems can improve cache behavior and reduce unnecessary computations. In conclusion, the paper emphasizes the need for further research and optimization for the widespread adoption of NVMs in embedded systems presenting relevant challenges, especially for machine learning applications. © 2023 ACM.

关键词： embedded systems

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Fine-grain Dynamic Instruction Placement for L0 Scratch-Pad Memory

Fine-grain Dynamic Instruction Placement for L0 Scratch-Pad ...

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6th embedded systems Week (ESWEEK)

作者： Park, Jongsoo Balfour, James Dally, William J. Stanford Univ Stanford CA 94305 USA NVIDIA Res Santa Clara CA USA

ISBN: (纸本)9781605589039

We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm captures a large fraction of instruction reuse missed by coarse-grain placement algorithms whose unit of transfer is restricted to loops or functions within the capacity of spms. Evaluation of L0 spms with our fine-grain algorithm in 17 applications shows that the energy consumed by instruction storage hierarchy is reduced by 38% and 31% compared to that of L0 instruction caches and L0 spms with an ideal coarse-grain algorithm, respectively.

关键词： Code Placement compilers embedded systems Scratch-Pad Memory

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