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Performance-driven syntax-directed synthesis of asynchronous processors

Performance-driven syntax-directed synthesis of asynchronous...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Plana, Luis A. Edwards, Doug Taylor, Sam Tarazona, Luis A. Bardsley, Andrew Advanced Processor Technologies Group School of Computer Science University of Manchester Manchester M13 9PL United Kingdom

ISBN: (纸本)9781595938268

The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthesis paradigm that compiles transparently a system specification written in a high-level language into a network of pre-designed handshaking modules. The transparency is provided by a one-to-one mapping from language constructs to the module networks that implement them. This gives the designer flexibility, at the language level, to optimise the resulting circuit in terms of performance, area or power. This paper introduces new techniques that exploit this flexibility to improve the performance of synthesised asynchronous systems. The results of a series of transistor level simulations show that these techniques, combined with optimised handshake module implementations, can produce close to a ten-fold improvement in the performance of a 32-bit, ARM-compatible, asynchronous processor used in an experimental smartcard SoC, without introducing any changes to the original processor architecture. Copyright 2007 ACM.

关键词： Program processors

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Fragment cache management for dynamic binary translators in embedded systems with scratchpad

Fragment cache management for dynamic binary translators in ...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Baiocchi, José Childers, Bruce R. Davidson, Jack W. Hiser, Jason D. Misurda, Jonathan Department of Computer Science University of Pittsburgh Department of Computer Science University of Virginia

ISBN: (纸本)9781595938268

Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for embedded systems. However, a challenge to DBT in this domain is stringent constraints on memory and performance. The translated code buffer used by DBT may occupy too much memory space. This paper proposes novel schemes to manage this buffer with scratchpad memory. We use footprint reduction to minimize the space needed by the translated code, victim compression to reduce the cost of retranslating previously seen code, and fragment pinning to avoid evicting needed code. We comprehensively evaluate our techniques to demonstrate their effectiveness. Copyright 2007 ACM.

关键词： Cache memory

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A low power front-end for embedded processors using a block-aware instruction set

A low power front-end for embedded processors using a block-...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Zmily, Ahmad Kozyrakis, Christos Electrical Engineering Department Stanford University Stanford CA 94305 United States

ISBN: (纸本)9781595938268

Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since instruction fetching happens on nearly every cycle and involves accesses to large memory arrays such as instruction and branch target caches. The use of small front-end arrays leads to significant power and area savings, but typically results in significant performance degradation. This paper evaluates and compares optimizations that improve the performance of embedded processors with small front-end caches. We examine both software techniques, such as instruction re-ordering and selective caching, and hardware techniques, such as instruction prefetching, tagless instruction cache, and unified caches for instruction and branch targets. We demonstrate that, building on top of a block-aware instruction set, these optimizations can eliminate the performance degradation due to small front-end caches. Moreover, selective combinations of these optimizations lead to an embedded processor that performs significantly better than the large cache design while maintaining the area and energy efficiency of the small cache design. Copyright 2007 ACM.

关键词： Program processors

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Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems

Eliminating inter-process cache interference through cache r...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Reddy, Rakesh Petrov, Peter University of Maryland College Park United States

ISBN: (纸本)9781595938268

We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to provide the required memory bandwidth. However, caches introduce two important problems for embedded systems. Cache outcomes in multi-tasking environments are notoriously difficult to predict, if not impossible, thus resulting in poor real-time guarantees. Additionally, caches contribute to a significant amount of power. These issues are key factors for many embedded systems. We study the effect of multiple tasks on the data cache, and propose a technique which leverages configurable cache architectures to eliminate inter-task cache interference. By mapping tasks to different cache partitions, interference is completely eliminated with only a minimal impact on performance. Furthermore, dynamic and leakage power are significantly reduced as only a subset of the cache is active at any moment. We introduce a profile-based, static analysis algorithm, which identifies a beneficial cache partitioning. The OS configures the data cache during context-switch by activating the corresponding *** experiments on a large set of multitasking benchmarks demonstrate that our technique not only efficiently eliminates inter-task interference but also significantly reduces both dynamic and leakage power. Copyright 2007 ACM.

关键词： embedded systems

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Software controlled memory layout reorganization for irregular array access patterns

Software controlled memory layout reorganization for irregul...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Cho, Doosan Issenin, Ilya Dutt, Nikil Yoon, Jonghee W. Paek, Yunheung School of EECS Seoul National University Center for Embedded Computer Systems University of California Irvine CA 92697

ISBN: (纸本)9781595938268

Many embedded array-intensive applications have irregular access patterns that are not amenable to static analysis for extraction of access patterns, and thus prevent efficient use of a Scratch Pad Memory (SPM) hierarchy for performance and power improvement. We present a profiling based strategy that generates a memory access trace which can be used to identify data elements with fine granularity that can profitably be placed in the SPMs to maximize performance and energy gains. We developed an entire toolchain that allows incorporation of the code required to profitably move data to SPMs;visualization of the extracted access pattern after profiling;and evaluation/exploration of the generated application code to steer mapping of data to the SPM to yield performance and energy *** present a heuristic approach that efficiently exploits the SPM using the profiler-driven access pattern behaviors. Experimental results on EEMBC and other industrial codes obtained with our framework show that we are able to achieve 36% energy reduction and reduce execution time by up to 22% compared to a cache based system. Copyright 2007 ACM.

关键词： Computer software

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Application driven embedded system design: A face recognition case study

Application driven embedded system design: A face recognitio...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Ramani, Karthik Davis, Al School of Computing University of Utah Salt Lake City UT 84112 United States

ISBN: (纸本)9781595938268

The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core specialization has been employed in the embedded space and is likely to play an important role in future heterogeneous multi-core architectures as well. In this paper, the face recognition application domain is employed as a case study to showcase an architectural design methodology which generates a specialized core with high performance and very low powercharacteristics. Specifically, we create "ASIC-like" execution flows to sustain the high memory parallelism generated within the core. The price of this benefit is a significant increase in compilation complexity. The crux of the problem is the need to co-schedule the often conflicting constraints of data access, data movement, and computation. A modular compiler approach that employs integer linear programming (ILP) based "interconnect- aware" instruction and data scheduling techniques to solve this problem is then described. The resulting core running the compiled code delivers a 1.65x throughput improvement over a high performance processor (Pentium 4) while simultaneously achieving an 80x energy-delay improvement over an energy-efficient processor (XScale) and performs real-time face recognition at embedded power budgets. Copyright 2007 ACM.

关键词： embedded systems

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A group-based wear-leveling algorithm for large-capacity flash memory storage systems

A group-based wear-leveling algorithm for large-capacity fla...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Jung, Dawoon Chae, Yoon-Hee Jo, Heeseung Kim, Jin-Soo Lee, Joonwon 335 Gwahangno Yuseong-gu Daejeon 305-701 Korea Republic of

ISBN: (纸本)9781595938268

Although NAND flash memory has become one of the most popular storage media for portable devices, it has a serious problem with respect to lifetime. Each block of NAND flash memory has a limited number of program/erase cycles, usually 10,000-100,000, and data in a block become unreliable after the limit. For this reason, distributing erase operations evenly across the whole flash memory media is an important concern in designing flash memory storage *** this paper, we propose a memory-efficient group-based wear-leveling algorithm. Our group-based algorithm achieves a small memory footprint by grouping several logically sequential blocks and managing only the summary information for each group. We also propose an effective group summary structure and a method to reduce unnecessary wear-leveling operations in order to enhance the wear-leveling performance. The evaluation results show that our group-based algorithm consumes only 8.75% of memory space compared to the previous scheme that manages per-block information, while showing roughly the same wear-leveling performance. Copyright 2007 ACM.

关键词： embedded systems

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Performance optimal processor throttling under thermal constraints

Performance optimal processor throttling under thermal const...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Rao, Ravishankar Vrudhula, Sarma Consortium for Embedded Systems Arizona State University Tempe AZ 85281 United States

ISBN: (纸本)9781595938268

We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature constant requires an exponential speed curve. Earlier works that propose constant throttling only keep the package/case temperature constant, and are hence suboptimal. We develop high-level thermal and power models that are simple enough for analysis, yet account for important effects like the power-density variation across a chip (hotspots), leakage dependence on temperature (LDT), and differing thermal characteristics of the silicon die and the thermal solution. We use a piecewise-linear approximation for the exponential leakage dependence on temperature, and devise a method to remove the circular dependency between leakage power and temperature. To solve the multi-task speed control problem, we first solve analytically, the single task problem with a constraint on the final package temperature using optimal control theory. We then find the optimum final package temperature of each task by dynamic programming. We compared the total execution time of several randomly generated task sequences using the optimal control policy against a constant speed throttling policy, and found significantly smaller total execution times. We compared the thermal profiles predicted by the proposed high-level thermal model to that of the Hotspot thermal model, and found them to be in good agreement. Copyright 2007 ACM.

关键词： Program processors

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A simplified java bytecode compilation system for resource-constrained embedded processors

A simplified java bytecode compilation system for resource-c...

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cases'07: 2007 international conference on compilers, architecture, and synthesis for embedded systems

作者： Badea, Carmen Nicolau, Alexandru Veidenbaum, Alexander V. Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)9781595938268

embedded platforms are resource-constrained systems in whichperformance and memory requirements of executed code are ofcritical importance. However, standard techniques such as full just-in-time(JIT) compilation and/or adaptive optimization (AO) may not be appropriate for this type of systems due to memory and compilation overheads. The research presented in this paper proposes a technique that combines some of the main benefits of JIT compilation, superoperators(SOs) and profile-guided optimization, in order to deliver a lightweight Java bytecode compilation system, targeted for resource-constrained environments, that achieves runtime performance similar to that of state-of-the-art JIT/AO systems, while having a minimal impact on runtime memory *** key ideas are to use profiler-selected, extended bytecode basic blocks as superoperators (new bytecode instructions) and to perform few, but very targeted, JIT/AO-like optimizations at compile time only on the superoperators. bytecode, as directed by compilation .hints. encoded as annotations. As such, our system achieves competitive performance to a JIT/AO system, but witha much lower impact on runtime memory consumption. Moreover,it is shown that our proposed system can further improveprogram performance by selectively inlining method calls embedded in the chosen superoperators, as directed by runtime profiling data and with minimal impact on classfile size. For experimental evaluation, we developed three Virtual Machines(VMs) that employ the ideas presented above. The customized VMs are first compared (w.r.t. runtime performance) to a simple, fast-to-develop VM (baseline) and then to a VM that employs JIT/AO. Our best-performing system attains speedups ranging from a factor of 1.52 to a factor of 3.07, w.r.t. to the baseline VM. When compared to a state-of-the-art JIT/AO VM, our proposed system performs better for three of the benchmarks and worse by less than a factor of 2 for three others. But our SO-ext

关键词： embedded systems

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Generic architecture description for retargetable compilation and synthesis of application-specific pipelined IPs

Generic architecture description for retargetable compilatio...

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24th international conference on Computer Design

作者： Gorjiara, Bita Reshadi, Mehrdad Gajski, Daniel Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92717 USA

ISBN: (纸本)9780780397064

Constraints of embedded systems and the shrinking time-to-market have elevated the importance of designer productivity and design predictability more than ever. To improve productivity, in ASIP approaches the system is designed with software and executed on a customized processor. In ASIP design flow, the processor is described in an architecture Description Language (ADL) and the toolset is generated from that ADL automatically. However, in these approaches design predictability is low because the designer has little or no control over the quality of the final implementation. In this paper, we present a new design approach where the target processor or Intellectual Property (IT) does not have any predefined instruction-set and its datapath component netlist is described in a Generic Netlist Representation (GNR). The GNR is used by the toolset to generate the controller of the IP and the RTL of the design. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. We have also developed a web-based interface for our toolset, so that users can upload and evaluate new IPs described in GNR.

关键词： Productivity

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