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Message from the cases 2009 conference Chairs

Embedded Systems Week 2009 - 2009 International Conference o...

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embedded systems Week 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09 2009年 iii页

作者： Henkel, Joerg Parameswaran, Sri

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IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of embedded systems

IGOR, Get Me the Optimum! Prioritizing Important Design Deci...

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embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Smirnov, Fedor Pourmohseni, Behnaz Glass, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Cauerstr 11 D-91058 Erlangen Germany Univ Ulm Albert Einstein Allee 11 D-89081 Ulm Germany

Design Space Exploration (DSE) techniques for complex embedded systems must cope with a huge variety of applications and target architectures as well as a wide spectrum of objectives and constraints. In particular, existing design automation approaches are either problem-independent, in that they do not exploit any knowledge about the optimization problem at hand, or are tailored to specific a priori assumptions about the problem and/or a specific set of design objectives. While the latter are only applicable within a very limited scope of design problems, the former may struggle to deliver high-quality solutions for problems with large design spaces and/or complex design objectives. As a remedy, we propose Importance-Guided Order Rearrangement (IGOR) as a novel approach for DSE of embedded systems. Instead of relying on an a priori problem knowledge, IGOR uses a machine-learning-inspired technique to dynamically analyze the importance of design decisions, i.e., the impact that these decisions-within the specific problem that is being optimized-have on the quality of explored problem solutions w.r.t. the given design objectives. Throughout the DSE, IGOR uses this information to guide the optimization towards the most promising regions of the design space. Experimental results for a variety of applications from different domains of embedded computing and for different optimization scenarios give evidence that the proposed approach is both scalable and adaptable, as it can be used for the optimization of systems described by several thousands constraints, where it outperforms both problem-specific and problem-independent optimization approaches and achieves e-dominance improvements of up to 95%.

关键词： Design space exploration constrained combinatorial problems multi-objective optimization embedded systems

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High-Level synthesis of Approximate Designs under Real-Time Constraints

High-Level Synthesis of Approximate Designs under Real-Time ...

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作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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Special Session-Non-Volatile Memories: Challenges and Opportunities for embedded System architectures with Focus on Machine Learning Applications

Special Session-Non-Volatile Memories: Challenges and Opport...

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2023 international conference on compilers, architecture, and synthesis for embedded systems, cases 2023

作者： Henkel, Jorg Siddhu, Lokesh Bauer, Lars Teich, Jurgen Wildermann, Stefan Tahoori, Mehdi Mayahinia, Mahta Castrillon, Jeronimo Khan, Asif Ali Farzaneh, Hamid De Lima, Joao Paulo C. Chen, Jian-Jia Hakert, Christian Chen, Kuan-Hsun Yang, Chia-Lin Cheng, Hsiang-Yun Germany Friedrich-Alexander-Universität Erlangen-Nürnberg Germany TU Dresden Germany TU Dortmund University Germany Lamarr Inst. for ML and AI Germany University of Twente Netherlands National Taiwan University Taiwan Academia Sinica Taiwan

ISBN: (纸本)9798400702907

This paper explores the challenges and opportunities of integrating non-volatile memories (NVMs) into embedded systems for machine learning. NVMs offer advantages such as increased memory density, lower power consumption, non-volatility, and compute-in-memory capabilities. The paper focuses on integrating NVMs into embedded systems, particularly in intermittent computing, where systems operate during periods of available energy. NVM technologies bring persistence closer to the CPU core, enabling efficient designs for energy-constrained scenarios. Next, computation in resistive NVMs is explored, highlighting its potential for accelerating machine learning algorithms. However, challenges related to reliability and device non-idealities need to be addressed. The paper also discusses memory-centric machine learning, leveraging NVMs to overcome the memory wall challenge. By optimizing memory layouts and utilizing probabilistic decision tree execution and neural network sparsity, NVM-based systems can improve cache behavior and reduce unnecessary computations. In conclusion, the paper emphasizes the need for further research and optimization for the widespread adoption of NVMs in embedded systems presenting relevant challenges, especially for machine learning applications. © 2023 ACM.

关键词： embedded systems

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ILP-based Modulo Scheduling for High-level synthesis

ILP-based Modulo Scheduling for High-level Synthesis

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international conference on Compliers, architectures, and synthesis of embedded systems (cases)

作者： Oppermann, Julian Koch, Andreas Reuter-Oppermann, Melanie Sinnen, Oliver Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany Karlsruhe Inst Technol Discrete Optimizat & Logist Grp Karlsruhe Germany Univ Auckland Parallel & Reconfigurable Comp Grp Auckland New Zealand

ISBN: (纸本)9781450344821

In high-level synthesis, loop pipelining is a technique to improve the throughput and utilisation of hardware datapaths by starting new loop iterations after a fixed amount of time, called the initiation interval (II), allowing to overlap subsequent iterations. The problem is to find the smallest II and corresponding operation schedule that fulfils all data dependencies and resource constraints, both of which are usually found by modulo scheduling. We propose Moovac', a novel integer linear program (ILP) formulation of the modulo scheduling problem based on overlap variables to model exact resource constraints. Given enough time, Moovac will find a mimimum-II solution. This is in contrast to Canis' state-of-the-art Modulo SDC approach, which requires heuristic simplifications of the resource constraints. Moovac can thus be used as a reference to evaluate heuristics, or in a time-limited mode as a heuristic itself to provide a best-so-far solution. We schedule kernels from the CHStone and MachSuite benchmarks for loop pipelining with Moovac, Modulo SDC and a prior exact formulation by Eichenberger. Moovac has competitive performance in its time-limited mode, and delivers better results faster than the Modulo SDC scheduler for some loops. Often its structure leads to quicker solution times than Eichenberger's formulation. Using the Moovac-computed optimal solutions as a reference, we can confirm that the Modulo SDC heuristic is indeed capable of finding optimal or near-optimal solutions for the majority of small-to medium-sized loops. However, for larger loops the two algorithms begin to diverge, with Moovac often being significantly faster to prove the infeasibility of a candidate II. This can be exploited by running both schedulers synergistically, leading to a quicker convergence to the final II.

关键词： High level synthesis

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Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs

Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI I...

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作者： Restuccia, Francesco Pagani, Marco Biondi, Alessandro Marinoni, Mauro Buttazzo, Giorgio Scuola Super Sant Anna Via Moruzzi 1 I-56127 Pisa Italy Scuola Super Sant Anna Area CNR Pisa Italy Univ Lille CRIStAL CNRS Cent LilleUMR 9189 Lille France

AMBA AXI is a popular bus protocol that is widely adopted as the medium to exchange data in field-programmable gate array system-on-chips (FPGA SoCs). The AXI protocol does not specify how conflicting transactions are arbitrated and hence the design of bus arbiters is left to the vendors that adopt AXI. Typically, a round-robin arbitration is implemented to ensure a fair access to the bus by the master nodes, as for the popular SoCs by Xilinx. This paper addresses a critical issue that can arise when adopting the AXI protocol under round-robin arbitration;specifically, in the presence of bus transactions with heterogeneous burst sizes. First, it is shown that a completely unfair bandwidth distribution can be achieved under some configurations, making possible to arbitrarily decrease the bus bandwidth of a target master node. This issue poses serious performance, safety, and security concerns. Second, a low-latency (one clock cycle) module named AXI burst equalizer (ABE) is proposed to restore fairness. Our investigations and proposals are supported by implementations and tests upon three modern SoCs. Experimental results are reported to confirm the existence of the issue and assess the effectiveness of the ABE with bus traffic generators and hardware accelerators from the Xilinx's IP library.

关键词： FPGA AXI BUS arbitration embedded systems

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Fine-grain Dynamic Instruction Placement for L0 Scratch-Pad Memory

Fine-grain Dynamic Instruction Placement for L0 Scratch-Pad ...

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6th embedded systems Week (ESWEEK)

作者： Park, Jongsoo Balfour, James Dally, William J. Stanford Univ Stanford CA 94305 USA NVIDIA Res Santa Clara CA USA

ISBN: (纸本)9781605589039

We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm captures a large fraction of instruction reuse missed by coarse-grain placement algorithms whose unit of transfer is restricted to loops or functions within the capacity of spms. Evaluation of L0 spms with our fine-grain algorithm in 17 applications shows that the energy consumed by instruction storage hierarchy is reduced by 38% and 31% compared to that of L0 instruction caches and L0 spms with an ideal coarse-grain algorithm, respectively.

关键词： Code Placement compilers embedded systems Scratch-Pad Memory

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A holistic approach to network-on-chip synthesis 10

A holistic approach to network-on-chip synthesis

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Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

作者： Leary, Glenn Chatha, Karam S. Department of CSE Arizona State University P.O. Box 875406 Tempe AZ 85287-5406 United States

ISBN: (纸本)9781605589053

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

关键词： Network-on-chip

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Message from the cases 2010 program chairs

Embedded Systems Week 2010 - Proceedings of the 2010 Interna...

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