检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

350 篇 会议
31 篇 期刊文献

馆藏范围

381 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

266 篇 工学
- 259 篇 计算机科学与技术...
- 173 篇 软件工程
- 67 篇 电气工程
- 48 篇 电子科学与技术（可...
- 33 篇 信息与通信工程
- 23 篇 动力工程及工程热...
- 20 篇 控制科学与工程
- 6 篇 机械工程
- 5 篇 材料科学与工程（可...
- 4 篇 化学工程与技术
- 3 篇 力学（可授工学、理...
- 3 篇 光学工程
- 3 篇 生物工程
- 2 篇 仪器科学与技术
- 2 篇 生物医学工程（可授...
- 1 篇 建筑学
- 1 篇 土木工程
- 1 篇 测绘科学与技术
- 1 篇 石油与天然气工程
74 篇 理学
- 59 篇 数学
- 12 篇 系统科学
- 7 篇 物理学
- 5 篇 统计学（可授理学、...
- 3 篇 化学
- 3 篇 生物学
43 篇 管理学
- 36 篇 管理科学与工程(可...
- 29 篇 工商管理
- 9 篇 图书情报与档案管...
6 篇 经济学
- 6 篇 应用经济学
5 篇 法学
- 5 篇 社会学

主题

115 篇 embedded systems
29 篇 computer archite...
27 篇 hardware
18 篇 embedded system
16 篇 program processo...
10 篇 memory managemen...
9 篇 system-on-chip
8 篇 application soft...
8 篇 throughput
8 篇 random access me...
8 篇 high level synth...
8 篇 field programmab...
7 篇 energy consumpti...
7 篇 computational mo...
7 篇 computer aided s...
7 篇 energy efficienc...
6 篇 runtime
6 篇 reliability
6 篇 real time system...
6 篇 space exploratio...

机构

3 篇 department of co...
3 篇 tech univ denmar...
3 篇 center for embed...
3 篇 embedded systems...
3 篇 department of el...
3 篇 tech univ darmst...
2 篇 friedrich alexan...
2 篇 univ michigan 22...
2 篇 tu dresden
2 篇 center for embed...
2 篇 univ new south w...
2 篇 university of tw...
2 篇 instituto tecnol...
2 篇 school of comput...
2 篇 advanced compute...
2 篇 budapest univ te...
2 篇 univ new south w...
2 篇 univ lille crist...
2 篇 lamarr inst. for...
2 篇 center for embed...

作者

8 篇 dutt nikil
7 篇 shrivastava avir...
7 篇 barua rajeev
6 篇 palem krishna v.
5 篇 dean alexander g...
5 篇 jörg henkel
5 篇 henkel joerg
4 篇 raghunathan anan...
4 篇 ienne paolo
4 篇 madsen jan
4 篇 pozzi laura
4 篇 vahid frank
4 篇 pop paul
4 篇 andreas koch
3 篇 ha soonhoi
3 篇 homayoun houman
3 篇 koch andreas
3 篇 parameswaran sri
3 篇 hu xiaobo sharon
3 篇 marwedel peter

语言

380 篇 英文
1 篇 中文

检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是221-230 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Generic architecture Description for Retargetable Compilation and synthesis of Application-Specific Pipelined IPs

Generic Architecture Description for Retargetable Compilatio...

引用

IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Bita Gorjiara Mehrdad Reshadi Daniel Gajski Center for Embedded Computer Systems University of California Irvine USA

Constraints of embedded systems and the shrinking time-to-market have elevated the importance of designer productivity and design predictability more than ever. To improve productivity, in ASIP approaches the system is designed with software and executed on a customized processor. In ASIP design flow, the processor is described in an architecture Description Language (ADL) and the toolset is generated from that ADL automatically. However, in these approaches design predictability is low because the designer has little or no control over the quality of the final implementation. In this paper, we present a new design approach where the target processor or Intellectual Property (IP) does not have any predefined instruction-set and its datapath component netlist is described in a Generic Netlist Representation (GNR). The GNR is used by the toolset to generate the controller of the IP and the RTL of the design. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. We have also developed a web-based interface for our toolset, so that users can upload and evaluate new IPs described in GNR.

关键词： Productivity Application specific processors Computer architecture embedded system Time to market Software design Process design architecture description languages Automatic control Intellectual property

来源：评论

学校读者我要写书评

暂无评论

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

CASES 2005: International Conference on Compilers, Architect...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

ISBN: (纸本)159593149X

The proceedings contain 32 papers. The topics discussed include: exploiting pipelining to relax register-file port constraints of instruction-set extensions;exploring the design space of LUT-based transparent accelerators;automating custom-precision function validation for embedded processors;energy management for commodity short-bit-width microcontrollers;anomalous path detection with hardware support;hardware support for code integrity in embedded processors;segment protection for embedded systems using run-time checks;compilation techniques for energy reduction in horizontally partitioned cache architectures;verfiable annotations for embedded Java environment;and optimizing stream programs using linear state space analysis.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

Code transformation strategies for extensible embedded processors

Code transformation strategies for extensible embedded proce...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Bonzini, Paolo Pozzi, Laura Switzerland

ISBN: (纸本)1595935436

embedded application requirements, including high performance, low power consumption and fast time to market, are uncommon in the broader domain of general purpose applications. In order to satisfy these demands, chip manufacturers often provide developers with the possibility to define application-specific Instruction Set Extensions (ISEs). Many techniques have been proposed that automatically identify the most beneficial ISEs from source code, so that compilers can identify the 'best' instruction set for the underlying machine. However, can we simply retrofit these techniques into a traditional compiler, or does ISE identification demand different tuning of the heuristics utilized throughout the optimization pipeline? In this paper, we show why compilers should sometimes make different decisions when targeting customized processors, and we show how traditional ISE identification techniques can improve significantly if the code is properly transformed in order to expose more beneficial extensions. The proposed approach was validated using the SimpleScalar simulator for the ARM processor, augmented with the possibility to define additional *** benchmarks taken from the MiBench suite,we show that the proposed transformations improve state of the art ISE identi cation techniques by 55% on average and 4x maximum. Copyright 2006 ACM.

关键词： Program compilers

来源：评论

学校读者我要写书评

暂无评论

Methods for power optimization in distributed embedded systems with real-time requirements

Methods for power optimization in distributed embedded syste...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Racu, Razvan Hamann, Arne Ernst, Rolf Mochocki, Bren Hu, Xiaobo Sharon IDA Technical University of Braunschweig D-38106 Braunschweig Germany Department of CSE University of Notre Dame Notre Dame IN 46556 United States

ISBN: (纸本)1595935436

Dynamic voltagescaling and sleep state control have been shown to be extremely effective in reducing energy consumption in CMOS circuits. Though plenty of research papers have studied the application of these techniques in real-time embedded system design through intelligent task and/or voltage scheduling, most of these results are limited to relatively simple real-time application models. In this paper, a comprehensive real-time application model including periodic, sporadic and bursty tasks as well as distributed real-time constraints such as end-to-end delays is considered. Two methods are presented for reducing energy consumption while satisfying complex real-time constraints for this model. Experimental results show that the methods achieve significant energy savings without violating any deadlines. Copyright 2006 ACM.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

A case study of multi-threading in the embedded space

A case study of multi-threading in the embedded space

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Hoover, Greg Brewer, Forrest Sherwood, Timothy University of California Santa Barbara Engineering I Santa Barbara CA 93106

ISBN: (纸本)1595935436

The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net processors are tasked with the job of handling a disparate set of interrupt driven activity, from networks to timers to the sensors *** this paper,we demonstrate the advantages of a tiny multi-threaded microcontroller design which targets embedded applications that need to respond to events at high speed. While multi-threading is typically used to improve resource utilization, in the embedded space it can provide zero-cycle context switching and interrupt service threads (IST), enabling complex programmable control in latency constrained environments. To explore the advantages of multi-threading on these embedded problems, we have implemented in hardware a family of controllers supporting eight dynamically interleaved threads and executing the AVR instruction set. This allows us to carefully quantify the effects of threading on interrupt latency, code size, overall processor throughput, cycle time, and design area for complete designs with different numbers of threads. Copyright 2006 ACM.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

Dances with multimedia: embedded video codec design

Dances with multimedia: Embedded video codec design

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Chen, Liang-Gee Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)1595935436

The rapid progress of semiconductor technology enables the rising and flourishing of digital multimedia. Fancy terms such as ubiquitous multimedia, mobile multimedia, embedded video, etc., and hot products such as iPod, Camera phone, Portable Multimedia Player, etc., mark our colorful life, now and future. In this talk, I attempt to review the past and present developments of video coding, and to explore some future trends. Then, this talk will discuss the challenging optimization tasks that video codec architects have to face under the stringent time-to-market pressure for applications ranged from low-power mobile multimedia to high definition video. Design issues, optimization techniques, and case studies are presented. What we have learned is that multimedia SOC design is a beautiful but challenging dance among video codec HW/SW designers, transistors and video bits.

关键词： Multimedia systems

来源：评论

学校读者我要写书评

暂无评论

Adaptive and flexible dictionary code compression for embedded applications

Adaptive and flexible dictionary code compression for embedd...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Brorsson, Mats Collin, Mikael KTH ICT Dept. of Electronic Computer and Software Systems Electrum 229 SE-164 40 Kista Sweden

ISBN: (纸本)1595935436

Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions. We present a new view of dictionary code compression for moderately high-performance processors for embedded applications. Previous work with dictionary code compression has shown decent performance and energy savings results which we verify with our own measurement that are more thorough than previously published. We also augment previous work with a more thorough analysis on the effects of cache and line size changes. In addition, we introduce the concept of aggregated profiling to allow for two or more programs to share the same dictionary contents. Finally, we also introduce dynamic dictionaries where the dictionary contents is considered to be part of the context of a process and show that the performance overhead of reloading the dictionary contents on a context switch is negligible while on the same time we can save considerable energy with a more specialized dictionary contents. Copyright 2006 ACM.

关键词： Codes (symbols)

来源：评论

学校读者我要写书评

暂无评论

Compiler optimization of embedded applications for an adaptive SoC architecture

Compiler optimization of embedded applications for an adapti...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Hardnett, Charles R. Palem, Krishna V. Chobe, Yogesh Spelman College Computer Science Department Atlanta GA 30314 United States Center for Research on Embedded Systems and Technology Georgia Institute of Technology Atlanta GA 30308 United States

ISBN: (纸本)1595935436

Adaptive Explicitly Parallel Instruction Computing (AEPIC) is a stylized form of a reconfigurable system-on-a-chip that is designed to enable compiler control of reconfigurable resources. In this paper, and for the first time, we validate the viability of automating two key optimizations proposed in the AEPIC compilation framework: configuration allocation and configuration scheduling. The AEPIC architecture is comprised of an Explicitly Parallel Instruction Computing (EPIC) core coupled with an adaptive fabric and architectural features to support dynamic management of the fabric. We show that this approach to compiler-centric hardware customization, originally proposed by Palem, Talla, Devaney and Wong ([26],[27]), yields speedups with factors from 150% to over 600% for embedded applications, when compared with general purpose and digital signal processor solutions. We also provide a normalized cost analysis for our performance gains, where the normalization is based on the area of silicon required. In addition, we provide an analysis of the AEPIC architectural space, where we identify the "sweet-spot" of performance on the AEPIC architecture by examining the performance across benchmarks and computational resource configurations. Finally, we have a preliminary result for how our compiler-based approach impacts productivity metrics in the development of ardware/software partitioned custom solutions. Our implementation and validation platform is based on the well-known TRIMARAN optimizing compiler infrastructure [13]. Copyright 2006 ACM.

关键词： Program compilers

来源：评论

学校读者我要写书评

暂无评论

Automated compile-time and run-time techniques to increase usable memory in MMU-less embedded systems

Automated compile-time and run-time techniques to increase u...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Bai, Lan S. Yang, Lei Dick, Robert P. Electrical Engineering and Computer Science Department Northwestern University 2145 Sheridan Road Evanston IL 60208

ISBN: (纸本)1595935436

Random access memory (RAM) is tightly-constrained in many embedded systems. This is especially true for the least expensive, lowest-power embedded systems, such as sensor network nodes and portable consumer electronics. The most widely-used sensor network nodes have only 4-10 KB of RAM and do not contain memory management units (MMUs). It is very difficult to implement increasingly complex applications under such tight memory constraints. Nonetheless, price and power consumption constraints make it unlikely that increases in RAM in these systems will keep pace with the requirements of *** propose the use of automated compile-time and run-time techniques to increase the amount of usable memory in MMU-less embedded systems. The proposed techniques do not increase hardware cost, and are designed to require few or no changes to existing applications. We have developed a fast compression algorithm well suited to this application, as well as run-time library routines and compiler transformations to control and optimize the automatic migration of application data between compressed and uncompressed memory regions. These techniques were experimentally evaluated on Crossbow TelosB sensor network nodes running a number of data collection and signal processing applications. The results indicate that available memory can be increased by up to 50% with less than 10% performance degradation for most benchmarks. Copyright 2006 ACM.

关键词： Program compilers

来源：评论

学校读者我要写书评

暂无评论

Reaching fast code faster: Using modeling for efficient software thread integration on a VLIW DSP

Reaching fast code faster: Using modeling for efficient soft...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： So, Won Dean, Alexander G. Center for Embedded Systems Research Department of Electrical and Computer Engineering North Carolina State University Raleigh NC 27695-7256

ISBN: (纸本)1595935436

When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be aligned and integrated, and which regions should be left alone. This problem grows even worse on a modern VLIW DSP due to complicating factors in both the hardware and compiler: software pipelining, predication, branch delay slots, load delay slots and limited resources. As a result, finding an effective integration strategy requires extensive iteration through the integrate/compile/analyze *** this paper we introduce methods to quantitatively estimate the performance benefit from the integration of multiple software threads. We use resource modeling, consider register pressure and compensate for compiler optimizations. This enables different scenarios to be compared and ranked. We then use these estimates to guide integration by concentrating on the most beneficial scenario. Information from each iteration of compilation is used to update the rankings of scenarios. We find that our modeling methods combined with limited compilation quickly find the best integration scenario without requiring exhaustive integration. Copyright 2006 ACM.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共39页 << < 19 20 21 22 23 24 25 26 27 28 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：