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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是221-230 订阅

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IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of embedded systems

IGOR, Get Me the Optimum! Prioritizing Important Design Deci...

引用

embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Smirnov, Fedor Pourmohseni, Behnaz Glass, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Cauerstr 11 D-91058 Erlangen Germany Univ Ulm Albert Einstein Allee 11 D-89081 Ulm Germany

Design Space Exploration (DSE) techniques for complex embedded systems must cope with a huge variety of applications and target architectures as well as a wide spectrum of objectives and constraints. In particular, existing design automation approaches are either problem-independent, in that they do not exploit any knowledge about the optimization problem at hand, or are tailored to specific a priori assumptions about the problem and/or a specific set of design objectives. While the latter are only applicable within a very limited scope of design problems, the former may struggle to deliver high-quality solutions for problems with large design spaces and/or complex design objectives. As a remedy, we propose Importance-Guided Order Rearrangement (IGOR) as a novel approach for DSE of embedded systems. Instead of relying on an a priori problem knowledge, IGOR uses a machine-learning-inspired technique to dynamically analyze the importance of design decisions, i.e., the impact that these decisions-within the specific problem that is being optimized-have on the quality of explored problem solutions w.r.t. the given design objectives. Throughout the DSE, IGOR uses this information to guide the optimization towards the most promising regions of the design space. Experimental results for a variety of applications from different domains of embedded computing and for different optimization scenarios give evidence that the proposed approach is both scalable and adaptable, as it can be used for the optimization of systems described by several thousands constraints, where it outperforms both problem-specific and problem-independent optimization approaches and achieves e-dominance improvements of up to 95%.

关键词： Design space exploration constrained combinatorial problems multi-objective optimization embedded systems

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Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs

Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI I...

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作者： Restuccia, Francesco Pagani, Marco Biondi, Alessandro Marinoni, Mauro Buttazzo, Giorgio Scuola Super Sant Anna Via Moruzzi 1 I-56127 Pisa Italy Scuola Super Sant Anna Area CNR Pisa Italy Univ Lille CRIStAL CNRS Cent LilleUMR 9189 Lille France

AMBA AXI is a popular bus protocol that is widely adopted as the medium to exchange data in field-programmable gate array system-on-chips (FPGA SoCs). The AXI protocol does not specify how conflicting transactions are arbitrated and hence the design of bus arbiters is left to the vendors that adopt AXI. Typically, a round-robin arbitration is implemented to ensure a fair access to the bus by the master nodes, as for the popular SoCs by Xilinx. This paper addresses a critical issue that can arise when adopting the AXI protocol under round-robin arbitration;specifically, in the presence of bus transactions with heterogeneous burst sizes. First, it is shown that a completely unfair bandwidth distribution can be achieved under some configurations, making possible to arbitrarily decrease the bus bandwidth of a target master node. This issue poses serious performance, safety, and security concerns. Second, a low-latency (one clock cycle) module named AXI burst equalizer (ABE) is proposed to restore fairness. Our investigations and proposals are supported by implementations and tests upon three modern SoCs. Experimental results are reported to confirm the existence of the issue and assess the effectiveness of the ABE with bus traffic generators and hardware accelerators from the Xilinx's IP library.

关键词： FPGA AXI BUS arbitration embedded systems

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Message from the cases 2009 conference Chairs

Embedded Systems Week 2009 - 2009 International Conference o...

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embedded systems Week 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09 2009年 iii页

作者： Henkel, Joerg Parameswaran, Sri

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Power Agnostic Technique for Efficient Temperature Estimation of Multicore embedded systems

Power Agnostic Technique for Efficient Temperature Estimatio...

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ACM international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Rai, Devendra Yang, Hoeseok Bacivarov, Iuliana Thiele, Lothar ETH Comp Engn & Networks Lab CH-8092 Zurich Switzerland

ISBN: (纸本)9781450314244

Temperature plays an increasingly important role in the overall performance and reliability of a computing system. Multi- and many-core systems provide an opportunity to manage the overall temperature profile by cleverly designing the application-to-core mapping and the associated scheduling policies. An uncontrolled temperature profile may lead to an unplanned performance loss, since the system activates protective mechanisms such as voltage and/or frequency scaling to cool itself. Similarly, deep thermal cycles with high frequency lead to severe deterioration in the overall reliability of the system. Design space exploration tools are often used to optimize binding and scheduling choices based on a given set of constraints and objectives, thus motivating the need for fast and accurate temperature estimation techniques. We argue that the currently available techniques are not an ideal fit to design space exploration tools, and suggest a system level technique which is based on application fingerprinting. It does not need any information about the processor floorplan, the physical and thermal structure, or about power consumption. Instead, its temperature estimation is based on a set of application-specific calibration runs and associated temperature measurements using available built-in sensors. We show that a given application possesses a unique thermal signature on the system it executes on, which provides a computationally fast method to calculate accurate temperature traces. Extensive experimental studies show that our technique can estimate temperature on all cores of a system to within 5 degrees C, and is three orders of magnitude faster than state of the art numerical simulators like Hotspot.

关键词： power temperature modeling

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A holistic approach to network-on-chip synthesis 10

A holistic approach to network-on-chip synthesis

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Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

作者： Leary, Glenn Chatha, Karam S. Department of CSE Arizona State University P.O. Box 875406 Tempe AZ 85287-5406 United States

ISBN: (纸本)9781605589053

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

关键词： Network-on-chip

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D-PUF: An Intrinsically Reconfigurable DRAM PUF for Device Authentication in embedded systems

D-PUF: An Intrinsically Reconfigurable DRAM PUF for Device A...

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international conference on Compliers, architectures, and synthesis of embedded systems (cases)

作者： Sutar, Soubhagya Raha, Arnab Raghunathan, Vijay Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781450344821

Physically Unclonable Functions (PUFs) have proved to be an effective and low-cost measure against counterfeiting by providing device authentication and secure key storage services. Memory based PUF implementations are an attractive option due to the ubiquitous nature of memory in electronic devices and the requirement of minimal (or no) additional circuitry. DRAM based PUFs are particularly advantageous due to their large address space and multiple controllable parameters during response generation. However, prior works on DRAM PUFs use a static response generation mechanism making them vulnerable to security attacks. Further, they result in very slow device authentication, are not applicable to off-the-shelf DRAM modules, or require DRAM power cycling prior to authentication. In this paper, we propose D-PUF, an intrinsically reconfigurable DRAM PUF based on refresh pausing. A key feature of the proposed DRAM PUF is that it can be reconfigured by varying the refresh-pause interval, which changes it's challenge-response behavior, making it robust against various attacks. We use the PUF to design a secure, low-overhead methodology for performing device authentication. The design is implemented and validated using an Altera Stratix IV GX FPGA based Terasic TR4-230 development board and several off-the-shelf 1GB DDR3 DRAM modules. Our experimental results demonstrate a 4.3X-6.4X reduction in authentication time, compared to previous work. Using controlled temperature and accelerated aging tests, we also demonstrate the robustness of our authentication mechanism to temperature variations and aging effects.

关键词： Hardware Security Physically Unclonable Function Memory PUF Authentication

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WCET-driven Cache-aware Code Positioning

WCET-driven Cache-aware Code Positioning

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14th Confernece on compilers, architectures and synthesis for embedded systems (cases)

作者： Falk, Heiko Kotthaus, Helena Univ Ulm Inst Embedded Systems Real Time Syst D-89069 Ulm Germany Tech Univ Dortmund Comp Sci 12 D-44221 Dortmund Germany

ISBN: (纸本)9781450307130

Code positioning is a well-known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of code fragments in memory avoids overlapping of cache sets and thus decreases the number of cache conflict misses. We present a novel cache-aware code positioning optimization driven by worst-case execution time (WCET) information. For this purpose, we introduce a formal cache model based on a conflict graph which is able to capture a broad class of cache architectures. This cache model is combined with a formal WCET timing model, resulting in a cache conflict graph weighted with WCET data. This conflict graph is then exploited by heuristics for code positioning of both basic blocks and entire functions. Code positioning is able to decrease the accumulated cache misses for a total of 18 real-life benchmarks by 15.5% on average for an automotive processor featuring a 2-way set-associative cache. These cache miss reductions translate to average WCET reductions by 6.1%. For direct-mapped caches, even larger savings of 18.8% (cache misses) and 9.0% (WCET) were achieved.

关键词： WCET Cache Code Positioning Locality Cache Miss

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Message from the cases 2010 program chairs

Embedded Systems Week 2010 - Proceedings of the 2010 Interna...

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embedded systems Week 2010 - Proceedings of the 2010 international conference on compilers, architecture and synthesis for embedded systems, cases'10 2010年 v页

作者： Tatge, Reid Kathail, Vinod

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Message from the cases 2014 program co-chairs

2014 International Conference on Compilers, Architecture and...

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2014 international conference on compilers, architecture and synthesis for embedded systems, cases 2014 2014年

作者： Iyer, Ravi Raghunathan, Anand

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High-Level synthesis of Approximate Designs under Real-Time Constraints

High-Level Synthesis of Approximate Designs under Real-Time ...

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作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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