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Cost-efficient soft error protection for embedded microprocessors

Cost-efficient soft error protection for embedded microproce...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Blome, Jason A. Gupta, Shantanu Feng, Shuguang Mahlke, Scott Bradley, Daryl Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI ARM Ltd. Cambridge United Kingdom

ISBN: (纸本)1595935436

Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety critical applications, ranging from automobiles to pacemakers, compounds the importance of addressing the soft error problem. Historically, soft error tolerance techniques have been targeted mainly at high-end server markets, leading to solutions such as coarse-grained modular redundancy and redundant multithreading. However, these techniques tend to be prohibitively expensive to implement in the embedded design space. To address this problem, we first present a thorough analysis of the effects of soft errors on a production-grade, fully synthesized implementation of an ARM926EJ-S embedded microprocessor. We then leverage this analysis in the design of two orthogonal low-costs of terror protection techniques that can be tuned to achieve variable levels of fault coverage as a function of area and power constraints. The first technique uses a small cache of live register values in order to provide nearly twice the fault coverage of a register file protected using traditional error correcting codes at little or no additional area cost. The second technique is a statistical method used to significantly reduce the overhead of deploying time-delayed shadow latches for low-latency fault detection. Copyright 2006 ACM.

关键词： Error detection

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Power efficient branch prediction through early identification of branch addresses

Power efficient branch prediction through early identificati...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Yang, Chengmo Orailoglu, Alex Computer Science and Engineering Department University of California San Diego 9500 Gilman Drive San Diego CA 92093

ISBN: (纸本)1595935436

Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic branch prediction subsystems to hide the execution latency of control-altering instructions. In this paper a low power early branch identification technique which enables the design of extremely power-efficient branch predictors and BTBs is proposed. Through static extraction of program information regarding the distance to subsequent branches, this technique enables the calculation of the next branch address as soon as the direction of the current branch has been predicted. Early identification of branch addresses enables a complete elimination of the power hungry BTB lookups normally occurring at every execution cycle, as well as a just-in-time wake-up mechanism when accessing "hibernating" entries in complex predictors, switched to power-saving mode to reduce leakage power dissipation. A cost-efficient Branch Identification Unit (BIU) to calculate branch addresses is presented and analyzed in terms of power and timing characteristics. The effectiveness of the proposed BTB access policy and predictor wake-up mechanism is also confirmed by the simulation results of the SPECint 2000 and Media-bench benchmarks. Copyright 2006 ACM.

关键词： embedded systems

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Supporting precise garbage collection in Java Bytecode-to-C ahead-of-time compiler for embedded systems

Supporting precise garbage collection in Java Bytecode-to-C ...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Jung, Dong-Heon Bae, Sung-Hwan Lee, Jaemok Moon, Soo-Mook Park, Jongkuk School of Electrical Engineering and Computer Science Seoul National University Seoul 151-742 Korea Republic of

ISBN: (纸本)1595935436

A Java bytecode-to-C ahead-of-time compiler (AOTC) can improve the performance of a Java virtual machine (JVM) by translating bytecode into C code, which is then compiled into machine code via an existing C compiler. Although AOTC is effective in embedded Java systems, a bytecode-to-C AOTC could not easily employ precise garbage collection (GC) due to a difficulty in making a GC map, which keeps information on where each root live object is located when GC occurs. This is one of the reasons why all previous JVMs using a bytecode-to-C AOTC employed conservative GC, which can lead to poorer GC performance with more frequent memory shortage, especially in embedded systems where memory is *** this paper, we propose a way of allowing precise GC in a bytecode-to-C AOTC by generating additional C code which collects GC map-equivalent information at runtime. In order to reduce this runtime overhead, we also propose two optimization techniques which remove unnecessary C code. Our experimental results on Sun's CVM indicate that we can support precise GC for bytecode-to-C AOTC with a relatively low overhead. Copyright 2006 ACM.

关键词： Learning systems

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Modulo graph embedding: Mapping applications onto coarse-grained reconfigurable architectures

Modulo graph embedding: Mapping applications onto coarse-gra...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Park, Hyunchul Fan, Kevin Kudlur, Manjunath Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595935436

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing the potential for high computation throughput, scalability, low cost and energy efficiency. CGRAs consist of an array of function units and register files generally organized as a two dimensional grid. The most difficult challenge with deploying CGRAs is compiler scheduling technology that can map software implementations of compute intensive loops onto the array. Traditional schedulers are not suitable because they do not take into account the explicit routing of operand values that is necessary. In essence, the problem of binding operations to time slots and resources is extended to also include explicit routing of operands from producers to consumers. To tackle this problem, this paper introduces a software pipelining technique for mapping loop bodies onto CGRAs, referred to as modulo graph embedding. We leverage graph embedding from graph theory, which is used to draw graphs onto a target space. The loop body is essentially drawn onto the CGRA mesh, subject to modulo resource usage constraints. Modulo graph embedding is effective because it can take into account the communication structure of the loop body during mapping. On average, a compute utilization of 56-68% is achieved for a set of loop kernels across three 4x4 CGRA designs. Copyright 2006 ACM.

关键词： embedded systems

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Automatic performance model construction for the fast software exploration of new hardware designs

Automatic performance model construction for the fast softwa...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Cavazos, John Dubach, Christophe Agakov, Felix Bonilla, Edwin O'Boyle, Michael F. P. Fursin, Grigori Temam, Olivier School of Informatics University of Edinburgh United Kingdom ALCHEMY Group INRIA Futurs Paris-Sud University France HiPEAC

ISBN: (纸本)1595935436

Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requires running many experiments in order to understand how different optimizations interact. Given that simulators are orders of magnitude slower than real processors, such experiments are highly restricted. This paper develops a technique to automatically build a performance model for predicting the impact of program transformations on any architecture, based on a limited number of automatically selected runs. As a result, the time for evaluating the impact of any compiler optimization in early design stages can be drastically reduced such that all selected potential compiler optimizations can be evaluated. This is achieved by first evaluating a small set of sample compiler optimizations on a prior set of benchmarks in order to train a model, followed by a very small number of evaluations, or probes, of the target *** show that by training on less than 0. 7% of all possible transformations (640 samples collected from 10 benchmarks out of 880000 possible samples, 88000 per training benchmark) and probing the new program on only 4 transformations, we can predict the performance of all program transformations with an error of just 7. 3% on average. As each prediction takes almost no time to generate, this scheme provides an accurate method of evaluating compiler performance, which is several orders of magnitude faster than current approaches. Copyright 2006 ACM.

关键词： embedded systems

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Improving the performance and power efficiency of shared helpers in CMPs

Improving the performance and power efficiency of shared hel...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Shayesteh, Anahita Reinman, Glenn Jouppi, Norm Sherwood, Tim Sair, Suleyman Comp. Science Dept. UCLA HP Labs. Palo Alto Comp. Science Dept. UCSB Electrical Eng. Dept. NCSU

ISBN: (纸本)1595935436

Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alternative is a small, simple core that can be augmented with latency tolerant helpers. As the demands placed on the processor core varies between applications, and even between phases of an application, the benefit seen from any set of helpers will vary tremendously. If there is a single core, these auxiliary structures can be turned on and off dynamically to tune the energy/performance of the machine to the needs of the running *** more of the processor is broken down into helpers, and additional cores are added to a single chip that can potentially share helpers, the decisions that are made about these structures become increasingly important. In this paper we describe the need for methods that effectively manage these helpers. Our counter-based approach can dynamically turn off three helpers on average while staying within 2% of the performance when running with all helpers. In a multicore environment, our intelligent and exible sharing of helper provides an average 24% speedup compared to static sharing in conjoined cores. Furthermore we show a benefit from constructively sharing helpers among multiple cores running the same application. Copyright 2006 ACM.

关键词： embedded systems

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Probabilistic arithmetic and energy efficient embedded signal processing

Probabilistic arithmetic and energy efficient embedded signa...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： George, J. Marr, B. Akgul, B.E.S. Palem, K.V. CREST School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA 30332-0250 United States

ISBN: (纸本)1595935436

Probabilistic arithmetic, where the ith output bit of addition and multiplication is correct with a probability pi, is shown to be a vehicle for realizing extremely energy-efficient, embedded computing. Specifically, probabilistic adders and multipliers, realized using elements such as gates that are in turn probabilistic, are shown to form a natural basis for primitives in the signal processing (dsp) domain. In this paper, we show that probabilistic arithmetic can be used to compute the fft in an extremely energy-efficient manner, yielding energy savings of over 5.6X in the context of the widely used synthetic aperture radar (sar) application [1]. Our results are derived using novel probabilistic cmos (pcmos) technology, characterized and applied in the past to realize ultra-efficient architectures for probabilistic applications [2, 3, 4]. When applied to the dsp domain, the resulting error in the output of a probabilistic arithmetic primitive, such as an adder for example, manifests as degradation in the signal-to-noise ratio (snr) of the sar image that is reconstructed through the fft algorithm. In return for this degradation that is enabled by our probabilistic arithmetic primitives - degradation visually indistinguishable from an image reconstructed using conventional deterministic approaches-significant energy savings and performance gains are shown to be possible per unit of snr degradation. These savings stem from a novel method of voltage scaling, which we refer to as biased voltage scaling (or bivos), that is the major technical innovation on which our probabilistic designs are based. Copyright 2006 ACM.

关键词： Probabilistic logics

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Limitations of special-purpose instructions for similarity measurements in media SIMD extensions

Limitations of special-purpose instructions for similarity m...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Shahbahrami, Asadollah Juurlink, Ben Vassiliadis, Stamatis Computer Engineering Laboratory Faculty of Electrical Engineering Mathematics and Computer Science Delft University of Technology Netherlands

ISBN: (纸本)1595935436

Microprocessor vendors have provided special-purpose instructions such as psadbw and pdist to accelerate the sum-of-absolute differences (SAD) similarity measurement. The usefulness of these special-purpose instructions is limited except for the motion estimation kernel. This has several drawbacks. First, if the SAD becomes obsolete because a different similarity metric is going to be employed, then those special-purpose instructions are no longer useful. Second, these special instructions process 8-bit subwords only. This precision is not su cient for some kernels such as motion estimation in the transform domain. In addition, when employing other n-way parallel SIMD instructions to implement the SAD and sum-of-squared differences (SSD),the obtained speedup is much less than n. This is because there is a mismatch between the storage and the computational format. In this paper, we design and evaluate a variety of SIMD instructions for different data types. We synthesize special-purpose instructions using a few general-purpose SIMD instructions. In addition, we employ the extended subwords technique to avoid conversion overhead and to increase parallelism. In this technique there are four extra bits for every byte of register. The results show that using different SIMD instructions and extended subwords achieve a speedup ranging from 10.39 to 14.57 over C performance for SAD, SSD with interpolation, and SSD functions in the motion estimation kernel. While, MMX achieves a speedup ranging from 4.61 to 7.42. Additionally,the proposed SIMD instructions improve the performance of similarity measurement for image histograms by a factor ranging from 8.69 (1-way)to 11.70 (4-way) over *** for MMX speedup is between 2.90 (1-way) and 4.33 (4-way). Copyright 2006 ACM.

关键词： embedded systems

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An optimized design approach for squaring large integers using embedded hardwired multipliers

An optimized design approach for squaring large integers usi...

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4th IEEE/ACS international conference on Computer systems and Applications (AICCSA-06)

作者： Gao, Shuli Chabini, Noureddine Al-Khalili, Dhamin Langlois, Pierre Royal Mil Coll Canada Dept Elect & Comp Engn Kingston ON Canada Ecole Polytech Dept Comp Engn Montreal PQ Canada

ISBN: (纸本)1424402115

This paper presents an efficient design methodology and a systematic approach for the implementation of squaring functions with large integers, using small-size embedded multipliers. A general architecture of the squarer and a set of equations are derived to aid in the realization. The inputs of the squarer are split into several segments leading to an efficient utilization of the small-size embedded multipliers and reduced number of required addition operations. Various benchmarks were tested for different segments ranging from 2 to 5 targeting Xilinx Spartan-3 FPGA. The synthesis was performed with the aid of the Xilinx ISE 7.1 XST tool. Our approach was compared with the traditional technique using the same tool. The results illustrate that our design approach is very efficient in terms of both timing and area saving. The combinational delay is reduced by an average of 15.8%, and the area saving is about 50% in terms of number of slices and number of 4-input LUTs. Also, the number of required embedded multipliers is reduced by an average of 32.3% compared to the traditional technique.

关键词： Multiplying circuits

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TLM/network design space exploration for networked embedded systems

TLM/network design space exploration for networked embedded ...

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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Bombieri, N. Fummi, F. Quaglia, D. Dipartimento di Informatica Università di Verona 15 Strada le Grazie I-37134 Verona Italy

ISBN: (纸本)1595933700

This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design dimension is added to the traditional TLM refinement process to represent network configuration alternatives. Each network configuration can be used both to drive architecture refinement and exploration and to validate the system after each refinement step. A general criterion to map functionalities to System and Network models is presented. As a case study, the proposed methodology is applied to the design of a Voice-over-IP client. © Copyright 2006 ACM.

关键词： embedded systems

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