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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是241-250 订阅

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Streamroller: Automatic synthesis of prescribed throughput accelerator pipelines

Streamroller: Automatic synthesis of prescribed throughput a...

引用

CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Kudlur, Manjunath Fan, Kevin Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements. © Copyright 2006 ACM.

关键词： Pipeline processing systems

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System-level power-performance trade-offs in bus matrix communication architecture synthesis

System-level power-performance trade-offs in bus matrix comm...

引用

CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Pasricha, Sudeep Park, Young-Hwan Kurdahi, Fadi J. Dutt, Nikil Center for Embedded Computer Systems University of California Irvine CA

ISBN: (纸本)1595933700

System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multi-processor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power-performance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macro-models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macro-models incur less than 5% average absolute error compared to gate-level models. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach. © Copyright 2006 ACM.

关键词： Communication systems

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Semi-automatic reliability assessment of safety related embedded systems

Semi-automatic reliability assessment of safety related embe...

引用

18th IASTED international conference on Parallel and Distributed Computing and systems

作者： Kucera, Markus Mauser, Hans Univ Appl Sci Regensburg Regensburg Germany

ISBN: (纸本)9780889866386

Complexity is one major challenge to face when dealing with future automotive systems. Meeting dependability requirements whilst meeting cost targets and time schedule is the second major challenge to combat in that area. To accept these challenges this paper presents an approach which combines simulative and analytic techniques. We propose an approach that makes use of a COTS GUI (Matlab/Simulink) and a proprietary dependability module. For dependability evaluation we make use of classical Markov theory. The common known problem of state space explosion is tackled by making use of structured modelling and an algorithm for locality traversing. The presented approach not only allows to derive reliability figures for a given system architecture and given use cases. Furthermore, it also supports the process of developing new systems or optimise existing systems. All possible failure sequences of up to ten simultaneous failures are automatically generated and analyzed. The approach presented in this paper is generally applicable for safety related embedded systems.

关键词： fault-tolerance reliability safety embedded system automotive

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An on-chip diagnosis methodology for embedded cores with replaceable modules

An on-chip diagnosis methodology for embedded cores with rep...

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19th international conference on VLSI Design held jointly with 5th international conference on embedded systems Design

作者： Tekumalla, Ramesh C. ATI Research Inc. 62 Forest St. Marlborough MA 01752

ISBN: (纸本)0769525024

We propose a design for test and diagnosis architecture that simplifies the process of identifying failures within a failing sub-module, without explicitly identifying the faults responsible for that failure. The extra hardware eliminates the post-processing step needed to process the failure logs from the tester and automatically determines the sub-modules inside a core that must be replaced. The proposed methodology reduces the turnaround time for locating a failing module or sub-module and also facilitates testing and diagnosis at the same time. Experimental results are presented using industrial test-cases to validate the effectiveness of the proposed method. © 2006 IEEE.

关键词： embedded systems

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A new high resolution frequency and phase synthesis method based on 'Flying-Adder' architecture

A new high resolution frequency and phase synthesis method b...

引用

IEEE international conference on Semiconductor Electronics

作者： Gharaee, Hossein Tathesari, Elham Tarbiat Modares Univ Tehran Iran Shariati Univ Tehran Iran

ISBN: (纸本)9780780397309

High speed electronic systems demand frequency synthesizer of high resolution, wide bandwidth and fast switching speed. The "Flying-Adder" architecture is a frequency and phase synthesis technique that is based on a VCO of multiple delay stages. This Flying-Adder is implemented in Quartus software which its result shows that the highest frequency is about 83 MHz, when VCO oscillates at 5.2 MHz. In some cases, this architecture has a barrier of inherent jitter on the output frequency. In this brief, a new method is proposed for eliminating such jitter problem. This method is caused to achieve exact phase and frequency. This design is implemented in Quartus software with EPIK30QC208-1 device from ACEX 1K series. When VCO is running at 0.651-10 MHz high resolution output frequency is achieved.

关键词： Adders

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Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications

Data reuse driven energy-aware MPSoC co-synthesis of memory ...

引用

CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Issenin, Ilya Dutt, Nikil University of California Irvine CA 92697

ISBN: (纸本)1595933700

The memory subsystem of a complex multiprocessor systems-on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of the design. In this paper we propose a novel approach that enables energy-aware co-synthesis of both memory and communication architecture for streaming applications. As opposed to earlier techniques, we employ a powerful compile-time analysis of memory access behavior that adds flexibility in selecting memory architectures. Additionally, we target TDMA bus-based communication architectures, which not only guarantee performance, but also greatly reduce the design time and allow us to find the energy optimal system configuration. We propose and compare three techniques: an optimal mixed ILP-based co-synthesis technique, a mixed ILP-based traditional two-step synthesis approach where memory and communication synthesis is performed sequentially, and a co-synthesis heuristic that synthesizes energy-efficient hierarchical bus-based communication architectures with guaranteed throughput. Our experimental results on a number of streaming applications show that both the traditional two-step synthesis approach and heuristic result in up to 50% worse power consumption in comparison with proposed co-synthesis approach. However, on some of the streaming benchmarks, our co-synthesis heuristic approach was able to find optimal or near-optimal results in a much shorter time than the MILP co-synthesis approach. © Copyright 2006 ACM.

关键词： Multiprocessing systems

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2006 international conference on Computer Engineering and systems, ICCES' 06

2006 International Conference on Computer Engineering and Sy...

引用

2006 international conference on Computer Engineering and systems, ICCES'06

ISBN: (纸本)1424402719

The proceedings contain 80 papers. The topics discussed include: a tutorial on quantum computation and communication;global false coupling interaction-aware hierarchical timing analysis;quadrature direct digital frequency synthesizer using FPGA;evolutionary synthesis of synchronous finite state machines;adaptive fuzzy decentralized control for a class of large-scale nonlinear systems with MIMO subsystems;hierarchical fuzzy controller for robot manipulator;indirect adaptive fuzzy coordinated excitation and SVC control for multi-machine power system;discrete-time averaging of converters with PWM DC-DC feedback;IP encapsulation: approach and case study;monitoring serial communications in microcontroller based embedded systems;and interface architecture generation for IP integration in SoC design.

关键词： Decentralized control

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Continuous and embedded Learning for multi-agent systems

Continuous and Embedded Learning for multi-agent systems

引用

IEEE/RSJ international conference on Intelligent Robots and systems

作者： Kira, Zsolt Schultz, Alan C. Georgia Inst Technol Mobile Robot Lab Atlanta GA 30332 USA USN Res Lab Navy Ctr Appl Res AI Washington DC 20375 USA

ISBN: (纸本)9781424402588

This paper describes multi-agent strategies for applying Continuous and embedded Learning (CEL). In the CEL architecture [1], an agent maintains a simulator based on its current knowledge of the world and applies a learning algorithm that obtains its performance measure using this simulator. The simulator is updated to reflect changes in the environment or robot state that can be detected by a monitor, such as sensor failures. In this paper, we adapt this architecture to a multi-agent setting in which the monitor is communicated among the team members effectively creating a distributed monitor. The parameters of the current control algorithm (in our case rulebases learned by Genetic Algorithms) used by all of the agents are added to the monitor as well, allowing for cooperative learning. We show that communication of agent status (e.g. failures) among the team members allows the agents to dynamically adapt to team properties, in this case team size. Furthermore, we show that an agent is able to switch between specializing within a section of the domain when there are many team members and generalizing to other parts of the domain when the rest of the team members are disabled. Finally, we also discuss future potential of this method, most notably in the creation of a Distributed Case Based Reasoning system in which the cases are actual Genetic Algorithm population members that can be swapped among team members.

关键词： genetic algorithms multi-agent coevolutionary systems cooperative coevolution multi-agent communication

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Automatic generation of transaction level models for rapid design space exploration

Automatic generation of transaction level models for rapid d...

引用

CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Shin, Dongwan Gerstlauer, Andreas Peng, Junyu Dömer, Rainer Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine CA 92697 United States

ISBN: (纸本)1595933700

Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate such transaction-level models from abstract input descriptions. Designers have to write such models manually, which is a tedious and error-prone task, and one of bottlenecks in improving designer's productivity. In this paper, we propose a method to generate transaction-level models from virtual architecture models where components communicate via abstract message-passing channels. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness and benefits of our approach for rapid, early exploration of communication design space. © Copyright 2006 ACM.

关键词： Logic design

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Validation and certification of safety-critical embedded systems -: The DECOS test bench

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25th international conference on Computer Safety, Security and Reliability

作者： Schoitsch, Erwin Althammer, Egbert Eriksson, Henrik Vinter, Jormy Goenczy, Laszlo Pataricza, Andras Csertan, Gyoergy ARC Seibersdorf Research Austria SP Swedish National Testing and Research Institute Sweden Budapest University of Technology and Economics Hungary

ISBN: (纸本)3540457623

The integrated EU-project DECOS (Dependable embedded Components and systems) aims at developing an integrated architecture for embedded systems to reduce life-cycle costs and to increase dependability of embedded applications. To facilitate the certification process of DECOS-based applications, the DECOS Test Bench constitutes a framework to support Validation & Verification. By implementing a modular approach, an application safety case merely contains the application-specific issues and re-uses the safety arguments of the "generic" safety cases of the DECOS platform. The Test Bench covers the complete life cycle from the platform-independent models to deployment, including model validation and transformations. The safety cases are based on validation-plans (v-plans) comprising the steps to validate the safety requirements. The Test Bench provides a methods/tools repository, guidelines to generate and execute v-plans, and integration of tools and of remotely distributed test beds.

关键词： embedded systems

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