This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embeddedsystems. As a result, a new design dimension is added to the traditional TL...
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Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the basic functions for biochemical analysis. The "digital" microfluidic biochips are manipul...
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ISBN:
(纸本)9781605589039
Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the basic functions for biochemical analysis. The "digital" microfluidic biochips are manipulating liquids not as a continuous flow, but as discrete droplets on a two-dimensional array of electrodes. Basic microfluidic operations, such as mixing and dilution, are performed on the array, by routing the corresponding droplets on a series of electrodes. So far, researchers have assumed that these operations are executed on rectangular virtual devices, formed by grouping several adjacent electrodes. One drawback is that all electrodes are considered occupied during the operation execution, although the droplet uses only one electrode at a time. Moreover, the operations can actually execute by routing the droplets on any sequence of electrodes on the array. Hence, in this paper, we eliminate the concept of virtual modules and allow the droplets to move on the chip on any route during operation execution. Thus, the synthesis problem is transformed into a routing problem. We propose an approach derived from a Greedy Randomized Adaptive Search Procedure (GRASP) and we show that by considering routing-based synthesis, significant improvements can be obtained in the application completion time.
GeMS is a customisable, open-source toolkit for generating random, yet constrained, modulo scheduling problems with a known optimal initiation interval. These can then be used to evaluate the behavior of different sch...
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GeMS is a customisable, open-source toolkit for generating random, yet constrained, modulo scheduling problems with a known optimal initiation interval. These can then be used to evaluate the behavior of different scheduling algorithms under controlled conditions.
conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover...
ISBN:
(数字)9781728191928
ISBN:
(纸本)9781728191935
conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original conference proceedings.
Generating an optimal execution plan for a given convolutional neural network (CNN) and a parameterizable hardware accelerator is a challenge. We present a framework that finds an execution plan that maximizes through...
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Generating an optimal execution plan for a given convolutional neural network (CNN) and a parameterizable hardware accelerator is a challenge. We present a framework that finds an execution plan that maximizes throughput for a given network and a specific configuration of our parameterizable accelerator. The framework first generates tiled dataflows for each layer, then maps the dataflows to the different independent hardware units using techniques borrowed from traditional list scheduling. Evaluated with a number of different networks and different hardware configurations, the presented framework clearly outperforms existing approaches in terms of speedup or schedule generation time.
As a benefactor of the proliferation of large scale integration, traditionally simple and unintelligent devices such as cameras have been transformed into key components of rich and engaging smart environments. By int...
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As a benefactor of the proliferation of large scale integration, traditionally simple and unintelligent devices such as cameras have been transformed into key components of rich and engaging smart environments. By integrating machine perception algorithms, these cognitive cameras have the ability to perceive and understand their environments. A principal barrier to realizing the potential of cognitive cameras has been the absence of sufficient computing power within the device. This is especially true in wearable devices which are limited by both compute capability and energy. Hardware customization and specialization present effective solutions to the power and performance bottlenecks that have limited ubiquitous adoption. This work details the architecture, design, and evaluation of a cognitive camera system that employs custom hardware to meet both power and performance constraints. Furthermore we illustrate its use as an assistance system for the visually impaired.
Automatic parallelization of sequential applications is the key for efficient use and optimization of current and future embedded multi-core systems. However, existing approaches often fail to achieve efficient balanc...
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Automatic parallelization of sequential applications is the key for efficient use and optimization of current and future embedded multi-core systems. However, existing approaches often fail to achieve efficient balancing of tasks running on heterogeneous cores of an MPSoC. A reason for this is often insufficient knowledge of the underlying architecture's performance. In this paper, we present a novel parallelization approach for embedded MPSoCs that combines pipeline parallelization for loops with knowledge about different execution times for tasks on cores with different performance properties. Using Integer Linear Programming, an optimal solution with respect to the model used is derived implementing tasks with a well-balanced execution behavior. We evaluate our pipeline parallelization approach for heterogeneous MPSoCs using a set of standard embedded benchmarks and compare it with two existing state-of-the-art approaches. For all benchmarks, our parallelization approach obtains significantly higher speedups than either approach on heterogeneous MPSoCs.
We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/software codesign and system synthesis community. Citations, meaning non-self-ci...
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ISBN:
(纸本)9781605584706
We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/software codesign and system synthesis community. Citations, meaning non-self-citations only, were considered from all papers known to Google Scholar, as well as only from subsequent CODES/ISSS papers. We list the most-cited CODES/ISSS papers of each year, summarizing their topics, and discussing common features of those papers. For comparison purposes, we also measured citations for the computer architecture community's ISCA and MICRO conferences, and for the field-programmable gate array community's FPGA and FCCM conferences. We point out several interesting differences among the citation patterns of the three communities. Copyright 2008 ACM.
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