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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"
381 条 记 录,以下是251-260 订阅
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Hardware cryptography-embedded multimedia mobile system
Hardware cryptography-embedded multimedia mobile system
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10th World Multi-conference on Systemics, Cybernetics and Informatics/12th international conference on Information systems Analysis and synthesis
作者: Fukase, Masa-aki Akaoka, Ryo Sato, Tomoaki Hirosaki Univ Dept Elect & Informat Syst Engn Hirosaki Aomori 0368561 Japan Hirosaki Univ Comp & Network Syst Ctr Hirosaki Aomori 0368561 Japan
Security aware multimedia mobility is crucial for the further progress of ubiquitous environment. Java has been promising in view of multimedia mobile features and easy treating, but this lacks simplicity in language ... 详细信息
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Protothreads: Simplifying event-driven programming of memory-constrained embedded systems  06
Protothreads: Simplifying event-driven programming of memory...
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SenSys'06: 4th international conference on embedded Networked Sensor systems
作者: Dunkels, Adam Schmidt, Oliver Voigt, Thiemo Ali, Muneeb Swedish Institute of Computer Science Box 1263 SE-16429 Kista Sweden TU Delft Mekelweg 4 2628 CD Delft Netherlands
Event-driven programming is a popular model for writing programs for tiny embedded systems and sensor network nodes. While event-driven programming can keep the memory overhead down, it enforces a state machine progra... 详细信息
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Architectural support for safe software execution on embedded processors
Architectural support for safe software execution on embedde...
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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis
作者: Arora, Divya Raghunathan, Anand Ravi, Srivaths Jha, Niraj K. Dept. of Electrical Engineering Princeton University Princeton NJ 08544 NEC Laboratories America Princeton NJ 08540
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and more recently, system security. A major ... 详细信息
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Cutting across layers of abstraction: Removing obstacles from the advancement of embedded systems
Cutting across layers of abstraction: Removing obstacles fro...
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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis
作者: Flautner, Krisztián ARM Ltd.
Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with steady improvements of performance and power consumption at each technology generation. This st... 详细信息
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SHAPES: A tiled scalable software hardware architecture platform for embedded systems
SHAPES: A tiled scalable software hardware architecture plat...
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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis
作者: Paolucci, Pier S. Jerraya, Ahmed A. Leupers, Rainer Thiele, Lothar Vicini, Piero ATMEL Roma INFN INFN Dip. Fisica Univ. Roma Italy TIMA INPG 46 Av. Félix Viallet 38031 Grenoble Cedex France Inst. for Integrated Signal Proc. Syst. Aachen Univ. of Technology Germany Zürich Switzerland INFN C/o Dip. Fisica Univ. Roma la Sapienza P.le Aldo Moro 5 00185 Roma Italy
Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" proces... 详细信息
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GigaNetIC - A scalable embedded O-chip multiprocessor architecture for network applications
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19th international conference on architecture of Computing systems, ARCS 2006
作者: Niemann, Jörg-Christian Puttmann, Christoph Porrmann, Mario Rückert, Ulrich Heinz Nixdorf Institute University of Paderborn Germany
In this paper, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a ... 详细信息
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26th IFIP WG 6.1 international conference on Formal Methods for Networked and Distributed systems, FORTE 2006
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26th IFIP WG 6.1 international conference on Formal Methods for Networked and Distributed systems, FORTE 2006
The proceedings contain 35 papers. The special focus in this conference is on Invited talks, Services, Middleware, Composition and synthesis, Logics, Symbolic verification - slicing, Unified modeling languages, Petri ...
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Hybrid custom instruction and co-processor synthesis methodology for extensible processors
Hybrid custom instruction and co-processor synthesis methodo...
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19th international conference on VLSI Design held jointly with 5th international conference on embedded systems Design
作者: Sun, Fei Ravi, Srivaths Raghunathan, Anand Jha, Niraj K. Tensilica Inc. Santa Clara CA 95054 NEC Laboratories America Princeton NJ 08540 Department of Electrical Engineering Princeton University Princeton NJ 08544
Classical hardware/software partitioning techniques, recent advances in application-specific instruction set architecture (ISA) design tools, etc., provide avenues to address the individual problems of co-processor ge... 详细信息
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synthesis of adaptive and controllable compliant systems with embedded actuators and sensors
Synthesis of adaptive and controllable compliant systems wit...
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2006 ASME international Design Engineering Technical conferences and Computers and Information In Engineering conference, DETC2006
作者: Trease, Brian P. Kota, Sridhar University of Michigan Department of Mechanical Engineering Ann Arbor MI 48109 United States
This paper presents a framework for the design of a compliant system;that is, the concurrent design of a compliant mechanism with embedded actuators and embedded sensors. We focus on methods that simultaneously synthe... 详细信息
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ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2006年 第7期14卷 754-762页
作者: Biswas, Partha Banerjee, Sudarshan Dutt, Nikil D. Pozzi, Laura Ienne, Paolo MathWorks Inc Natick MA 01760 USA Univ Calif Irvine Donald Bren Sch Informat & Comp Sci Ctr Embedded Syst Irvine CA 92697 USA Univ Lugano Dept Informat CH-6900 Lugano Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Processor Architecture Lab CH-1015 Lausanne Switzerland
Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to ... 详细信息
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