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Hardware cryptography-embedded multimedia mobile system

Hardware cryptography-embedded multimedia mobile system

10th World Multi-conference on Systemics, Cybernetics and Informatics/12th international conference on Information systems Analysis and synthesis

作者： Fukase, Masa-aki Akaoka, Ryo Sato, Tomoaki Hirosaki Univ Dept Elect & Informat Syst Engn Hirosaki Aomori 0368561 Japan Hirosaki Univ Comp & Network Syst Ctr Hirosaki Aomori 0368561 Japan

ISBN: (纸本)9789806560680

Security aware multimedia mobility is crucial for the further progress of ubiquitous environment. Java has been promising in view of multimedia mobile features and easy treating, but this lacks simplicity in language processing and platform organization. This has resulted in the saturation of increasing the overall performance of ubiquitous network. On the other hand, user security has been really threatened due to diversified open access to the ubiquitous network, while the diversity from small devices to large machines brings about easy access anytime anywhere. Thus, ever growing ubiquitous community makes overall demands for security, speed, and power consciousness in processing large quantity of multimedia data. The key technology to answer these requirements will be a single VLSI (very large scale integration) chip processor and its software support system, We have exploited the H/S (hardware/software) codesign of a hardware cryptography-embedded multimedia mobile processor and its language processing. The processor named HCgorilla is a devised interpreter type Java CPU (central processing unit) with less power and higher throughput for multimedia cryptographic streaming. The language processing for HCgorilla includes a Java interface and parallelizing compilers. We describe in this article our recent results about the overall system of HCgorilla.

关键词： processor hardware cryptography multimedia mobile Java byte code

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Protothreads: Simplifying event-driven programming of memory-constrained embedded systems 06

Protothreads: Simplifying event-driven programming of memory...

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SenSys'06: 4th international conference on embedded Networked Sensor systems

作者： Dunkels, Adam Schmidt, Oliver Voigt, Thiemo Ali, Muneeb Swedish Institute of Computer Science Box 1263 SE-16429 Kista Sweden TU Delft Mekelweg 4 2628 CD Delft Netherlands

ISBN: (纸本)1595933433

Event-driven programming is a popular model for writing programs for tiny embedded systems and sensor network nodes. While event-driven programming can keep the memory overhead down, it enforces a state machine programming style which makes many programs difficult to write, maintain, and debug. We present a novel programming abstraction called protothreads that makes it possible to write event-driven programs in a thread-like style, with a memory overhead of only two bytes per protothread. We show that protothreads significantly reduce the complexity of a number of widely used programs previously written with event-driven state machines. For the examined programs the majority of the state machines could be entirely removed. In the other cases the number of states and transitions was drastically decreased. With protothreads the number of lines of code was reduced by one third. The execution time overhead of protothreads is on the order of a few processor cycles. Copyright 2006 ACM.

关键词： embedded systems

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Architectural support for safe software execution on embedded processors

Architectural support for safe software execution on embedde...

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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Arora, Divya Raghunathan, Anand Ravi, Srivaths Jha, Niraj K. Dept. of Electrical Engineering Princeton University Princeton NJ 08544 NEC Laboratories America Princeton NJ 08540

ISBN: (纸本)1595933700

The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and more recently, system security. A major portion of known security attacks against software systems can be attributed to this shortcoming, including the well-known stack overflow, heap overflow, and format string attacks. Despite their limitations, the flexibility, performance, and ease of use of these languages have made them the choice of most embedded software developers. Researchers have proposed various techniques to enhance programs for memory safety;however, they are all subject to severe performance penalties, making their use impractical in most scenarios. In this paper, we present architectural enhancements to enable efficient, memory-safe execution of software on embedded processors. The key insight behind our approach is to extend embedded processors with hardware that significantly accelerates the execution of the additional computations involved in memory-safe execution. Specifically, we design custom instructions to perform various kinds of memory-safety checks and augment the instruction set of a state-of-the-art extensible processor (Xtensa from Tensilica, Inc.) to implement them. We demonstrate the application of the proposed architectural enhancements using CCured, an existing tool for type-safe retrofitting of C programs. The tool uses a type-inferencing engine that is built around strong type-safety theory and is provably safe. Simulations of memory-safe versions of popular embedded benchmarks on a cycle-accurate simulator modeling a typical embedded system configuration indicate an average performance improvement of 2.3x, and a maximum of 4.6x when using the proposed architecture. These enhancements entail minimal (less than 10%) hardware overhead to the base processor. Our approach is completely automated, and applicable to any C program, making it a promising and practi

关键词： embedded systems

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Cutting across layers of abstraction: Removing obstacles from the advancement of embedded systems

Cutting across layers of abstraction: Removing obstacles fro...

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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Flautner, Krisztián ARM Ltd.

ISBN: (纸本)1595933700

Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with steady improvements of performance and power consumption at each technology generation. This steady progress has created a sense of entitlement for the riches that future process generations would bring. Today, however, classical process scaling seems to be dead and living up to technology expectations requires continuous innovation at many levels, which comes at steadily progressing implementation and design costs. Solutions to problems need to cut across layers of abstractions and require coordination between software, architecture and circuit *** multiprocessor clusters are increasingly used to deliver the required compute power for high-end applications. Heterogeneity ensures that the necessary processing power can be delivered at high levels of efficiency at reasonable implementation cost, while the use of processors endow these systems with large degrees of flexibility. One of the key challenges with these systems is system-level programming. Traditional compiler technologies are strong at programming individual cores but leave the task of parallelization to a team of experts. The first part of this talk will describe the coupling of the compiler to the system architecture on a multi-core signal-processing cluster and illustrate how compiler technology can enable the writing of portable parallel programs for it using little more than *** claimed above, close coupling of abstraction layers can be beneficial. This can also be illustrated at the microarchitecture - circuit boundary. The second part of the talk will describe a prototype microarchitecture which is designed explicitly to deal with issues such as silicon variation and soft errors. These features in return enable system designers to focus on the typical-case performance of their implementations without having to be over-constrained by worst-case conditions. © Co

关键词： Abstracting

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SHAPES: A tiled scalable software hardware architecture platform for embedded systems

SHAPES: A tiled scalable software hardware architecture plat...

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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Paolucci, Pier S. Jerraya, Ahmed A. Leupers, Rainer Thiele, Lothar Vicini, Piero ATMEL Roma INFN INFN Dip. Fisica Univ. Roma Italy TIMA INPG 46 Av. Félix Viallet 38031 Grenoble Cedex France Inst. for Integrated Signal Proc. Syst. Aachen Univ. of Technology Germany Zürich Switzerland INFN C/o Dip. Fisica Univ. Roma la Sapienza P.le Aldo Moro 5 00185 Roma Italy

ISBN: (纸本)1595933700

Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires". A typical SHAPES tile contains a VLIW floating-point DSP, a RISC, a DNP (Distributed Network Processor), distributed on chip memory, the POT (a set of Peripherals On Tile) plus an interface for DXM (Distributed External Memory). The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbours engineering methodologies is adopted for off-chip networking and maximum system density. The SW challenge is to provide a simple and efficient programming environment for tiled architectures. SHAPES will investigate a layered system software, which does not destroy algorithmic and distribution info provided by the programmer and is fully aware of the HW paradigm. For efficiency and QoS, the system SW manages intra-tile and inter-tile latencies, bandwidths, computing resources, using static and dynamic profiling. The SW accesses the on-chip and off-chip networks through a homogeneous interface. © Copyright 2006 ACM.

关键词： embedded systems

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GigaNetIC - A scalable embedded O-chip multiprocessor architecture for network applications

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19th international conference on architecture of Computing systems, ARCS 2006

作者： Niemann, Jörg-Christian Puttmann, Christoph Porrmann, Mario Rückert, Ulrich Heinz Nixdorf Institute University of Paderborn Germany

ISBN: (纸本)3540327657

In this paper, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before we are going to fabricate the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with disparate performance and throughput requirements at high reliability. Furthermore, the composition from predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators. © Springer-Verlag Berlin Heidelberg 2006.

关键词： Multiprocessing systems

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26th IFIP WG 6.1 international conference on Formal Methods for Networked and Distributed systems, FORTE 2006

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26th IFIP WG 6.1 international conference on Formal Methods for Networked and Distributed systems, FORTE 2006

ISBN: (纸本)3540462198

The proceedings contain 35 papers. The special focus in this conference is on Invited talks, Services, Middleware, Composition and synthesis, Logics, Symbolic verification - slicing, Unified modeling languages, Petri nets, Parameterized verification, Real time and Testing . The topics include: Modelling of Complex Software systems: A Reasoned Overview, Semantic-Based Development of Service-Oriented systems, JSCL: A Middleware for Service Coordination, Analysis of Realizability Conditions for Web Service Choreographies, Web Cube, Presence Interaction Management in SIP SOHO architecture, Formal Analysis of Dynamic, Distributed File-System Access Controls, Analysing the MUTE Anonymous File-Sharing System Using the Pi-Calculus, Towards Fine-Grained Automated Verification of Publish-Subscribe architectures, A LOTOS Framework for Middleware Specification, Automatic synthesis of Assumptions for Compositional Model Checking, Refined Interfaces for Compositional Verification, On Distributed Program Specification and synthesis in architectures with Cycles, Generalizing the Submodule Construction Techniques for Extended State Machine Models, Decidable Extensions of Hennessy-Milner Logic, Symbolic Verification of Communicating systems with Probabilistic Message Losses: Liveness and Fairnes, A New Approach for Concurrent Program Slicing, Reducing Software architecture Models Complexity: A Slicing and Abstraction Approach, Branching Time Semantics for UML 2.0 Sequence Diagrams, Formalizing Collaboration Goal Sequences for Service Choreography, Composition of Use cases Using Synchronization and Model Checking, PN Standardisation: A Survey, Optimized Colored Nets Unfolding, Liveness by Invisible Invariants and Extending EFSMs to Specify and Test Timed systems with Action Durations and Timeouts.

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Hybrid custom instruction and co-processor synthesis methodology for extensible processors

Hybrid custom instruction and co-processor synthesis methodo...

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19th international conference on VLSI Design held jointly with 5th international conference on embedded systems Design

作者： Sun, Fei Ravi, Srivaths Raghunathan, Anand Jha, Niraj K. Tensilica Inc. Santa Clara CA 95054 NEC Laboratories America Princeton NJ 08540 Department of Electrical Engineering Princeton University Princeton NJ 08544

ISBN: (纸本)0769525024

Classical hardware/software partitioning techniques, recent advances in application-specific instruction set architecture (ISA) design tools, etc., provide avenues to address the individual problems of co-processor generation and custom instruction addition for extensible processors. However, we argue that there is a need for hybrid synthesis techniques by demonstrating that a combination of custom instructions and co-processors is often the better solution in many applications. We propose a systematic methodology that builds on basic observations and trade-offs associated with co-processors and custom instructions: co-processors are good for performing coarse-grained tasks that require minimal intervention or support from the processor, while custom instructions are efficient solutions for fine-grained tasks that are best integrated into a processor's pipeline. We have developed a hierarchical synthesis How that incorporates a muti-objective evolutionary algorithm in order to handle diverse design dimensions such as area, performance. We have implemented the proposed methodology in the context of a commercial extensible processor based platform (Xtensa™ from Tensilica). Our design flow incorporates a commercial behavioral synthesis tool and an automatic custom instruction generation engine. Our experiments with several applications show that simultaneous custom instruction and co-processor synthesis can achieve significantly better area/performance trade-offs than using only one of them. © 2006 IEEE.

关键词： Program processors

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synthesis of adaptive and controllable compliant systems with embedded actuators and sensors

Synthesis of adaptive and controllable compliant systems wit...

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2006 ASME international Design Engineering Technical conferences and Computers and Information In Engineering conference, DETC2006

作者： Trease, Brian P. Kota, Sridhar University of Michigan Department of Mechanical Engineering Ann Arbor MI 48109 United States

ISBN: (纸本)079183784X

This paper presents a framework for the design of a compliant system;that is, the concurrent design of a compliant mechanism with embedded actuators and embedded sensors. We focus on methods that simultaneously synthesize optimal structural topology and placement of actuators and sensors for maximum energy efficiency and adaptive performance, while satisfying various weight and performance constraints. The goal of this research is to lay a scientific foundation and a mathematical framework for distributed actuation and sensing within a compliant active structure. Key features of the methodology include (1) the simultaneous optimization of the location, orientation, and size of actuators concurrent with the compliant transmission topology and (2) the concepts of controllability and observability that arise from the consideration of control, and their implementation in compliant systems design. The methods used include genetic algorithms, graph searches for connectivity, and multiple load cases implemented with linear finite element analysis. Actuators, modeled as both force generators and structural compliant elements, are included as topology variables in the optimization. Results are provided for several studies, including: (1) concurrent actuator placement and topology design for a compliant amplifier and (2) a shape-morphing aircraft wing demonstration with three controlled output nodes. Central to this method is the concept of structural orthogonality, which refers to the unique system response for each actuator it contains. Finally, the results from the controllability problem are used to motivate and describe the analogous extension to observability for sensing Copyright © 2006 by ASME.

关键词： Adaptive systems

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ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2006年第7期14卷 754-762页

作者： Biswas, Partha Banerjee, Sudarshan Dutt, Nikil D. Pozzi, Laura Ienne, Paolo MathWorks Inc Natick MA 01760 USA Univ Calif Irvine Donald Bren Sch Informat & Comp Sci Ctr Embedded Syst Irvine CA 92697 USA Univ Lugano Dept Informat CH-6900 Lugano Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Processor Architecture Lab CH-1015 Lausanne Switzerland

Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Experimental results on a number of MediaBench, EEMBC, and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20 x faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application by effectively exploiting its regular structure.

关键词： application-specific processors hardware-software partitioning instruction set extensions

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