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Formal Techniques for Networked and Distributed systems - FORTE 2006 - 26th IFIP WG 6.1 international conference, Proceedings

引用

26th IFIP WG 6.1 international conference

ISBN: (纸本)3540462198

The proceedings contain 33 papers. The topics discussed include: analysis of realizability conditions for web service chreographics;web cube;presence interaction management in SIP SOHO architecture;formal analysis of dynamic, distributed file-system access controls;analyzing the MUTE anonymous file-sharing system using the pi-calculus;towards fine-grained automated verification of publish-subscribe architectures;a LOTOS framework for middleware specification;automatic synthesis of assumptions for compositional model checking;refined interfaces for compositional verification;on distributed program specification and synthesis in architectures with cycles;generalizing the submodule construction techniques for extended state machine models;decidable extensions of Hennessy-Milner logic;a new approach for concurrent program slicing;formalizing collaboration goal sequences for service choreography;and composition of use cases using synchronization and model checking.

关键词： Distributed computer systems

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Proceedings. 19th international conference on VLSI Design held jointly with 5th international conference on embedded systems and Design

Proceedings. 19th International Conference on VLSI Design he...

引用

international conference on VLSI Design

The following topics are dealt with: analog and mixed-signal design; VLSI technology; interconnect design; test and diagnosis; communications module architecture; formal verification; FPGAs; crosstalk analysis; high-level and logic synthesis; distribution and noise modeling; multimedia and arithmetic architecture; test algorithms; emerging technologies; synthesis and partitioning; memory and logic design; multimedia architecture; RF design; embedded systems; VLSI design tools; MEMS; low power design; design for testability.

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Multi-objective Optimal Controller synthesis for Heterogeneous embedded systems

Multi-objective Optimal Controller Synthesis for Heterogeneo...

引用

international conference on embedded Computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Lech Jozwiak Dominik Gawlowski Aleksander Slusarczyk Faculty of Electrical Engineering Eindhoven University of Technology MB Eindhoven The Netherlands

The recent spectacular progress in modern microelectronics created a big stimulus towards development of mobile, autonomous, embedded and re-configurable systems, but also resulted in many difficult to solve issues, as power and energy crisis or increased leakage power, that are especially serious for this sort of systems. What prevents the (re-)configurable heterogeneous embedded systems from becoming one of the main practically used paradigms is mainly inadequate support of the development methodologies and EDA-tools for efficient mapping of applications and producing power, energy, and speed optimized systems. As a part of our research that aims at development of effective methods and EDA-tools for the heterogeneous (re-)configurable embedded system synthesis, we performed a comparative analysis of several representative commercial and academic synthesis methods and tools for the FPGA-targeted controller synthesis. In this paper, the automatic hardware synthesis for the heterogeneous embedded systems is considered, when focusing on the efficient multi-objective controller synthesis. In particular, a part of results and conclusions from our analysis, and effective solutions of some problems observed are discussed

关键词： Optimal control Control system synthesis embedded system Microelectronics Hardware CMOS technology Automatic control Physics computing Computer architecture Appropriate technology

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ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors

ISEGEN: An iterative improvement-based ISE generation techni...

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2nd international conference on Hardware/Software Codesign and systems synthesis

作者： Biswas, Partha Banerjee, Sudarshan Dutt, Nikil D. Pozzi, Laura Ienne, Paolo MathWorks Inc Natick MA 01760 USA Univ Calif Irvine Donald Bren Sch Informat & Comp Sci Ctr Embedded Syst Irvine CA 92697 USA Univ Lugano Dept Informat CH-6900 Lugano Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Processor Architecture Lab CH-1015 Lausanne Switzerland

Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Experimental results on a number of MediaBench, EEMBC, and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20 x faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application by effectively exploiting its regular structure.

关键词： application-specific processors hardware-software partitioning instruction set extensions

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Dynamic template generation for resource sharing in control and data flow graphs

Dynamic template generation for resource sharing in control ...

引用

international conference on VLSI Design

作者： D.C. Zaretsky G. Mittal R.P. Dick P. Banerjee Department of Electrical Electrical & Computer Science Northwestern University Evanston IL USA College of Engineering University of Illinois Chicago Chicago IL USA

High-level synthesis compilers often produce reoccurring patterns in intermediate CDFGs during translation. By identifying large reoccurring patterns, one may reduce area and communication overhead by efficiently reusing hardware for multiple operations. This paper presents an algorithm for dynamically generating templates of reoccurring patterns for resource sharing in CDFGs. Results show 40-80% resource reduction using small, incremental template growth, and variations within a 5% margin among varying look-ahead depths.

关键词： Resource management Flow graphs Hardware Field programmable gate arrays Libraries Cost function High level synthesis Routing Data flow computing Computer science

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An Area-Efficient Reed-Solomon Decoder for HDTV Channel Demodulation

An Area-Efficient Reed-Solomon Decoder for HDTV Channel Demo...

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IEEE/ASME international conference on Mechtronic and embedded systems and Applications, MESA

作者： Yan Fei Guo Zhan Cai Li Qin Wang Information Engineering School University of Science and Technology Beijing China

In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for Reed-Solomon (RS) decoding. The proposed architecture is exploited based on the features of vector operations of the decoding algorithm. By pipelining and folding, the proposed architecture can improve the reuse rate of the main computation unit, reduce the hardware complexity and delete the redundant circuits. Synthesized by the Cadence Ambittrade tool using the TSMC 0.25 mum standard cell library, the implemented RS decoder consists of about 27,000 gates, which is about 39% smaller than the same kind of conventional ones. It has been integrated in a channel demodulation chip for high-definition television (HDTV) and has been tested successfully in practice

关键词： Reed-Solomon codes Decoding HDTV Demodulation Computer architecture Very large scale integration Pipeline processing Hardware Integrated circuit synthesis Libraries

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TLM/network design space exploration for networked embedded systems

TLM/network design space exploration for networked embedded ...

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international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： D. Quaglia F. Fummi N. Bombieri Dipartimento di Informatica Universitá di Verona Verona Italy

This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design dimension is added to the traditional TLM refinement process to represent network configuration alternatives. Each network configuration can be used both to drive architecture refinement and exploration and to validate the system after each refinement step. A general criterion to map functionalities to System and Network models is presented. As a case study, the proposed methodology is applied to the design of a Voice-over-IP client.

关键词： Space exploration embedded system Internet telephony Computational modeling Computer simulation Permission Computer networks Computer architecture Mobile handsets Wireless sensor networks

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Proceedings of the 2006 international conference on Computer-Aided Design

Proceedings of the 2006 International Conference on Computer...

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IEEE international conference on Computer-Aided Design

The following topics are dealt with: parasitic simulation; parasitic modeling; post-placement optimization; variation modeling; multicore systems; embedded systems; UML; systemC; industrial ESL design; delay test generation; power grid analysis and design; floorplanning; digital testing; RF testing; reliability; statistical timing analysis; system level design; analog simulation; analog verification; high level synthesis; CAD; analog design automation; system level interconnection; placement optimization; power analysis; mixed signal design; global routing; signal integrity; fault tolerant energy minimization; real-time systems; clock synthesis; buffer synthesis; thermal analysis; nanoelectronics; technology driven layout; nanoscale architecture; dynamic power management; model checking; biotechnology; MEMS; NEMS; accelerating verification; model order reduction; parametric analysis; and molecular scale systems

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Energy Efficient Statistical On-Chip Communication Bus synthesis for a Reconfigurable architecture

Energy Efficient Statistical On-Chip Communication Bus Synth...

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international conference on Field Programmable Logic and Applications

作者： Sujan Pandey Manfred Glesner Institute of Microelectronic Systems Darmstadt University of Technology Darmstadt Germany

In a reconfigurable computing system, some of the on-chip modules can be configured partially to run several applications in a single chip. Due to this feature of partial reconfiguration, the size of data to be transferred among the on-chip modules is random in nature. This paper proposes a method to synthesize an energy efficient on-chip communication bus width and number buses for a reconfigurable architecture. The randomness of data for such an architecture is modeled as a normally distributed random variable. The slack is exploited to maximize sharing of buses and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of communication bus. The resulting synthesis problem is relaxed to the quadratic optimization problem and is solved efficiently using a convex optimization tool. The experimental result shows the synthesis of bus width and number of buses with reduced communication energy for different variability of data size.

关键词： Energy efficiency Reconfigurable architectures System-on-a-chip Energy consumption Topology Libraries embedded system Voltage control Microelectronics Random variables

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Hardware-Software Codesign of Multimedia embedded systems: the PeaCE

Hardware-Software Codesign of Multimedia Embedded Systems: t...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Soonhoi Ha Choonseung Lee Youngmin Yi Seongnam Kwon Young-Pyo Joo The CAP Laboratory Seoul National University South Korea

Hardware/software codesign involves various design problems including system specification, design space exploration, hardware/software co-verification, and system synthesis. A codesign environment is a software tool that facilitates capabilities to solve these design problems. This paper presents the peace codesign environment mainly targeting for multimedia applications with real-time constraints. Peace specifies the system behavior with a heterogeneous composition of three models of computation. The Peace environment provides seamless co-design flow from functional simulation to system synthesis, utilizing the features of the formal models maximally during the whole design process. Preliminary experiments with real examples prove the viability of the proposed technique

关键词： Multimedia systems embedded system Hardware Computer architecture Space exploration Algorithm design and analysis Software tools Computational modeling Software design Software performance

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