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An approach to architectural enhancement for embedded speech applications

An approach to architectural enhancement for embedded speech...

引用

international conference on VLSI Design

作者： S. Dey S. Biswas A. Mukhopadhyay A. Basu Department of Computer Science and Engineering Indian Institute of Technology Kharagpur Kharagpur West Bengal India

Advances in human computer interaction (HCI) technology has resulted in widespread development of natural language and speech applications. These applications are known to be computationally different from other end-user applications. In this paper, the architectural features of text to speech (TTS) and automatic speech recognition (ASR) applications have been evaluated and cost effective optimal architectural solutions have been suggested. The results have shown that low cost solutions such as ISA extension and feature addition to an existing embedded architecture can lead to appreciable improvement in performance for these applications. This work also presents a design space exploration to suggest an optimized VLIW architecture for TTS and ASR applications.

关键词： Speech enhancement Application software Speech synthesis Automatic speech recognition Human computer interaction Natural languages Cost function Instruction sets Space exploration Design optimization

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System-level power-performance trade-offs in bus matrix communication architecture synthesis

System-level power-performance trade-offs in bus matrix comm...

引用

international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： Young-Hwan Park Fadi J. Kurdahi Nikil Dutt Sudeep Pasricha Center for Embedded Computer Systems University of California Irvine CA USA

System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power- performance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macro- models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macro- models incur less than 5% average absolute error compared to gate-level models. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach.

关键词： Energy consumption Computer architecture System-on-a-chip Space exploration Bandwidth Integrated circuit synthesis Network-on-a-chip embedded computing Multiprocessing systems Application software

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A New High Resolution Frequency and Phase synthesis Method based on `Flying-Adder' architecture

A New High Resolution Frequency and Phase Synthesis Method b...

引用

IEEE international conference on Semiconductor Electronics (ICSE)

作者： Hossein Gharaee Elham Tathesari Tarbiat Modares University Shariati University Iran

High speed electronic systems demand frequency synthesizer of high resolution, wide bandwidth and fast switching speed. The "Flying-Adder" architecture is a frequency and phase synthesis technique that is based on a VCO of multiple delay stages. This Flying-Adder is implemented in Quartus software which its result shows that the highest frequency is about 83 MHz, when VCO oscillates at 5.2 MHz. In some cases, this architecture has a barrier of inherent jitter on the output frequency. In this brief, a new method is proposed for eliminating such jitter problem. This method is caused to achieve exact phase and frequency. This design is implemented in Quartus software with EP1K30QC208-1 device from ACEX IK series. When VCO is running at 0.651-10 MHz high resolution output frequency is achieved.

关键词： Frequency synthesizers Voltage-controlled oscillators Jitter Computer architecture Delay Clocks Signal resolution Signal synthesis Phase locked loops High-speed electronics

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architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays

Architecture Exploration and Tools for Pipelined Coarse-Grai...

引用

international conference on Field Programmable Logic and Applications

作者： Florian Stock Andreas Koch Department for Integrated Technical University of Braunschweig Brunswick Germany Embedded Systems and Applications Group (ESA) Technical University of Darmstadt Darmstadt Germany

The paper presents a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools perform a simultaneous mapping and pipelining-aware placement, which is then followed by a congestion-avoiding router. Initial experiments show that this flow can succeed in implementing applications with smaller track count and reduced connectivity than existing commercial tools, suggesting changes to the original array architecture. The placer can reduce pipeline latency mismatches on converging paths, simplifying the problem for a pipelining-aware routing step

关键词： Delay Tiles Computer architecture Throughput Switches Fabrics Target tracking Integrated circuit synthesis Integrated circuit modeling Reconfigurable architectures

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Resource virtualization in real-time CORBA middleware

Resource virtualization in real-time CORBA middleware

引用

international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： Christopher D. Gill Department of Computer Science and Engineering Washington University Saint Louis MO USA

Middleware for parallel and distributed systems is designed to virtualize computation and communication resources so that a more abstract and consistent view of those resources is presented to the applications that use them. Providing such a consistent virtualization in distributed real-time and embedded systems becomes increasingly challenging due to application constraints such as timeliness and resource constraints such as CPU speed, power, memory, and bandwidth limitations, which also must be considered. This paper describes several examples of real-time CORBA middleware and examines how different constraints impact the way in which resources are virtualized in each case. Particular attention is paid to which details are hidden from users of the middleware, which details are exposed in the middleware's programming model, and how the hidden and exposed details interact to shape middleware design and implementation choices.

关键词： Resource virtualization Middleware Real time systems Application virtualization Distributed computing Concurrent computing embedded system Programming profession Application software Computer architecture

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Equivalence checking: a rule-based approach

Equivalence checking: a rule-based approach

引用

ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： M. Fujita S. Shankar S. Shunsuke University of Tokyo Japan CUNY City University of New York USA

A well-known problem in the design of embedded systems is checking for equivalence of two systems, and the traditional approach constructs and proves equivalence of finite state models of the two systems. Although widely and successfully used, the main problem is state space explosion, and other forms of higher-level analysis are also needed typically. Many typical system level design/synthesis tools and methodologies basically transform the control structures among function calls and/or sets of statements, with little modification to statements themselves. For example, the systems might differ only in statement order, dataflows (for differing amounts of parallelism), or abstraction levels. For such cases, we have developed an approach based on higher level static code analysis, and we have implemented a tool targeted at the SpecC language

关键词： Control systems Discrete transforms embedded system State-space methods Explosions System-level design Control system synthesis Data mining Prototypes Very large scale integration

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An on-chip diagnosis methodology for embedded cores with replaceable modules

An on-chip diagnosis methodology for embedded cores with rep...

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international conference on VLSI Design

作者： R.C. Tekumalla ATI Research Inc. Marlborough MA USA

We propose a design for test and diagnosis architecture that simplifies the process of identifying failures within a failing sub-module, without explicitly identifying the faults responsible for that failure. The extra hardware eliminates the post-processing step needed to process the failure logs from the tester and automatically determines the sub-modules inside a core that must be replaced. The proposed methodology reduces the turnaround time for locating a failing module or sub-module and also facilitates testing and diagnosis at the same time. Experimental results are presented using industrial test-cases to validate the effectiveness of the proposed method.

关键词： Fault diagnosis Circuit testing Pins Circuit faults Compaction Bandwidth Hardware Automatic testing Design methodology Combinational circuits

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Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus synthesis

Energy Conscious Simultaneous Voltage Scaling and On-chip Co...

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IFIP international conference on Very Large Scale Integration (VLSI-SoC)

作者： Sujan Pandey Tudor Murgan Manfred Glesner Institute of Microelectronics Systems Darmstadt University of Technology Darmstadt Germany

Due to the ever increasing trend of system complexity and technology scaling, synthesizing on-chip communication architecture appears to be a challenging task for the system designers. The traditional approaches are mostly based on the simulation of an entire system. However, the resulting architecture may not fulfil the requirements such as the performance, energy, size etc. and the computational cost of simulation based techniques is infeasible when exploring a large design space. This paper presents a simultaneous on-chip communication bus synthesis and voltage scaling approach, which is modeled in NLP (nonlinear programming) and finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The voltages (supply and body bias) are scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 57.1% by scaling its supply and body bias voltages

关键词： Voltage Computer architecture Topology System-on-a-chip Computational modeling Energy consumption Energy efficiency Computational efficiency Libraries embedded system

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A Coordinated Method Based on Hybrid Intelligent Control Agent for Multi-AUVs Control

A Coordinated Method Based on Hybrid Intelligent Control Age...

引用

international conference on Information and Automation (ICIA)

作者： Zheping Yan Shuping Hou School of Automation Harbin Engineering of Technology Harbin Heilongjiang China School of Mechanics & Electronics Engineering Harbin Engineering of Technology Harbin Heilongjiang China

There are both continuous-valued and discrete-event characteristics in multiple autonomous underwater vehicles (AUVs) at the same time. A new architecture based on hybrid intelligent control agent is developed for the control system modeling and coordinating of multi-mode dynamical systems. The hybrid intelligent control agent is an intelligent agent which has an embedded hybrid control system in its structural core. The result shows that AUVs cooperate well after using proposed method through the simulation of a whole scanning procedure.

关键词： Intelligent control Control systems Underwater vehicles Intelligent agent Automatic control Control system synthesis Vehicle dynamics Path planning Intelligent robots Automotive engineering

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Automatic run-time extraction of communication graphs from multithreaded applications

Automatic run-time extraction of communication graphs from m...

引用

international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： Robert P. Dick Ai-Hsin Liu Electrical Engineering and Computer Science Department Northwestern University Evanston IL USA

embedded system synthesis, multiprocessor synthesis, and thread assignment policy design all require detailed knowledge of the runtime communication patterns among different threads or processes. Researchers have commonly relied on manual estimation, compile- time analysis, or synthetic benchmarks when developing and evaluating synthesis algorithms and thread assignment policies. In a more ideal world, it would be possible to quickly and easily determine the run-time communication properties of large commercial and academic multithreaded applications. This article describes a fully-automated method of extracting run-time communication graphs from multithreaded applications. The resulting graphs may be used to better understand, design, and synthesize application-specific hardware-software systems. The proposed graph extraction method is implemented as a module within the Simics multiprocessor simulator. It presently supports the analysis of arbitrary multithreaded applications running on the Linux operating system. This software is called CETA. It is freely available for academic and non-profit use.

关键词： Runtime embedded system Application software Yarn Operating systems Data mining Algorithm design and analysis Computational modeling Computer architecture Linux

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