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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是271-280 订阅

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Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies

Simultaneously optimizing DRAM cache hit latency and miss ra...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Fazal Hameed Lars Bauer Jörg Henkel Chair for Embedded Systems (CES) Karlsruhe Institute of Technology (KIT) Germany

Two key parameters that determine the performance of a DRAM cache based multi-core system are DRAM cache hit latency (HL) and DRAM cache miss rate (MR), as they strongly influence the average DRAM cache access latency. Recently proposed DRAM set mapping policies are either optimized for HL or for MR. None of these policies provides a good HL and MR at the same time. This paper presents a novel DRAM set mapping policy that simultaneously targets both parameters with the goal of achieving the best of both to reduce the overall DRAM cache access latency. For a 16-core system, our proposed set mapping policy reduces the average DRAM cache access latency (depends upon HL and MR) compared to state-of-the-art DRAM set mapping policies that are optimized for either HL or MR by 29.3% and 12.1%, respectively.

关键词： Random access memory Arrays Organizations Memory management Round robin Multicore processing Electric breakdown

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Optimization of multi-channel BCH error decoding for common cases

Optimization of multi-channel BCH error decoding for common ...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Russ Dill Aviral Shrivastava Hyunok Oh Arizona State University Hanyang University

This paper proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. We break the BCH decoding process into its three basic blocks: syndrome calculation, the error locator polynomial generation, and the roots of the error locator polynomial computation. While an existing multi-channel BCH decoder consists of several single-channel BCH decoders operating in parallel, this paper utilizes a pooled group of shared decoding blocks. By considering the frequency of errors, the proposed pooled group approach requires fewer hardware blocks than in a traditional multi-channel configuration with a negligible impact on performance. Combined with a specialized root finding unit for blocks with only 1 error, our scheme reduces hardware area by 47%-71% and dynamic power by 44%-59% with 2% performance degradation in typical NAND flash systems. With a constant hardware area, the proposed scheme can improve throughput by 3x-5x or NAND flash lifetime by 1.4x-4.5x.

关键词： Force Error correction codes Polynomials Throughput Clocks

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A new high resolution frequency and phase synthesis method based on 'Flying-Adder' architecture

A new high resolution frequency and phase synthesis method b...

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IEEE international conference on Semiconductor Electronics

作者： Gharaee, Hossein Tathesari, Elham Tarbiat Modares Univ Tehran Iran Shariati Univ Tehran Iran

ISBN: (纸本)9780780397309

High speed electronic systems demand frequency synthesizer of high resolution, wide bandwidth and fast switching speed. The "Flying-Adder" architecture is a frequency and phase synthesis technique that is based on a VCO of multiple delay stages. This Flying-Adder is implemented in Quartus software which its result shows that the highest frequency is about 83 MHz, when VCO oscillates at 5.2 MHz. In some cases, this architecture has a barrier of inherent jitter on the output frequency. In this brief, a new method is proposed for eliminating such jitter problem. This method is caused to achieve exact phase and frequency. This design is implemented in Quartus software with EPIK30QC208-1 device from ACEX 1K series. When VCO is running at 0.651-10 MHz high resolution output frequency is achieved.

关键词： Adders

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Platform-dependent code generation for embedded real-time software

Platform-dependent code generation for embedded real-time so...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： BaekGyu Kim Linh T. X. Phan Oleg Sokolsky Lnsup Lee University of Pennsylvania

Code generation for embedded systems is challenging, since the generated code (e.g., C code) is expected to run on a heterogeneous set of target platforms with different characteristics, such as hardware/software architectures and programming interfaces. We propose a code generation framework that provides the flexibility to generate different source code that is executable on each target platform. In our framework, the platform-dependent characteristics of a target platform are explicitly specified by an Architectural Analysis Description Language (AADL) model and a code snippet repository. The AADL model captures hardware/software architectural aspects of the platform, such as periodic/aperiodic threads and their interactions with sensors and actuators. The code snippet repository contains platform-dependent code snippets that are categorized according to the functions required to implement the components of the AADL model. These two elements of the platform capability are then used by the code generation algorithm to generate platform-dependent code for the given platform. We demonstrate the applicability of our framework using a case study of code generation for two infusion pump systems.

关键词： Ports (Computers) Programming Instruction sets Hardware Message systems Semantics

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A Memory Interface for Multi-Purpose Multi-Stream Accelerators

A Memory Interface for Multi-Purpose Multi-Stream Accelerato...

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6th embedded systems Week (ESWEEK)

作者： Girbal, Sylvain Temam, Olivier Yehia, Sami Berry, Hugues Li, Zheng Thales Res & Technol Embedded Syst Lab Palaiseau France INRIA Saclay ALCHEMY Grp Orsay France

ISBN: (纸本)9781605589039

Power and programming challenges make heterogeneous multicores composed of cores and ASICs an attractive alternative to homogeneous multi-cores. Recently, multi-purpose loop-based generated accelerators have emerged as an especially attractive accelerator option. They have several assets: short design time (automatic generation), flexibility (multi-purpose) but low configuration and routing overhead (unlike FPGAs), computational performance (operations are directly mapped to hardware), and a focus on memory throughput by leveraging loop constructs. However, with multiple streams, the memory behavior of such accelerators can become at least as complex as that of superscalar processors, while they still need to retain the memory ordering predictability and throughput efficiency of DMAs. In this article, we show how to design a memory interface for multi-purpose accelerators which combines the ordering predictability of DMAs, retains key efficiency features of memory systems for complex processors, and requires only a fraction of their cost by leveraging the properties of streams references. We evaluate the approach with a synthesizable version of the memory interface for an example 9-task generated loop-based accelerator.

关键词： Memory interface Accelerators multi-stream

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Does customizing inexactness help over simplistic precision (bit-width) reduction? A case study

Does customizing inexactness help over simplistic precision ...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Ashutosh Ingole Biswaroop Maiti John Augustine Krishna Palem Dept. of Computer Science and Engineering IIT Madras Dept. of Computer Science Rice University

In the last two decades, energy has become a crucial resource whose consumption must be minimized while designing computing systems. This has affected every aspect of computing ranging from large scale supercomputers and data centers to small scale (but high volume) embedded systems comprising filters, digital signal processors (DSPs), and accelerators. Energy constraints play a particularly crucial role in battery operated devices (cell phones, wearables) and other energy constrained systems like unmanned aerial vehicles and sensor networks. In this backdrop of efforts to improve energy efficiency, a very interesting technique aimed at trading error for energy gains emerged over a decade ago. Typical computing systems are engineered to be exact. Energy gains have been achieved while compromising soft constraints like running time. This new technique called inexact computing or approximate computing aims push the envelope to achieve energy gains at the cost of an increased inexactness or error in the system. This radical shift has often yielded surprisingly significant energy gains with little to no side effects because many algorithms and applications (like DSP applications, big data applications, large scale numerical models) are inherently tolerant to error.

关键词： Probabilistic logic Kalman filters embedded systems Computer science Computational modeling Computer architecture Context

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Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications

Data reuse driven energy-aware MPSoC co-synthesis of memory ...

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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Issenin, Ilya Dutt, Nikil University of California Irvine CA 92697

ISBN: (纸本)1595933700

The memory subsystem of a complex multiprocessor systems-on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of the design. In this paper we propose a novel approach that enables energy-aware co-synthesis of both memory and communication architecture for streaming applications. As opposed to earlier techniques, we employ a powerful compile-time analysis of memory access behavior that adds flexibility in selecting memory architectures. Additionally, we target TDMA bus-based communication architectures, which not only guarantee performance, but also greatly reduce the design time and allow us to find the energy optimal system configuration. We propose and compare three techniques: an optimal mixed ILP-based co-synthesis technique, a mixed ILP-based traditional two-step synthesis approach where memory and communication synthesis is performed sequentially, and a co-synthesis heuristic that synthesizes energy-efficient hierarchical bus-based communication architectures with guaranteed throughput. Our experimental results on a number of streaming applications show that both the traditional two-step synthesis approach and heuristic result in up to 50% worse power consumption in comparison with proposed co-synthesis approach. However, on some of the streaming benchmarks, our co-synthesis heuristic approach was able to find optimal or near-optimal results in a much shorter time than the MILP co-synthesis approach. © Copyright 2006 ACM.

关键词： Multiprocessing systems

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Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study

Instruction-set Selection for Multi-application based ASIP D...

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IEEE 6th international conference on Information and Automation for Sustainability (ICIAFS)

作者： Ragel, Roshan Radhakrishnan, Swarnalatha Ambrose, Angelo Univ Peradeniya Dept Comp Engn Peradeniya Sri Lanka Univ New SouthWales Sch Comp Sci & Engn Sydney NSW 2052 Australia

ISBN: (纸本)9781467319751;9781467319768

Efficiency in embedded systems is paramount to achieve high performance while consuming less area and power. Processors in embedded systems have to be designed carefully to achieve such design constraints. Application Specific Instruction set Processors (ASIPs) exploit the nature of applications to design an optimal instruction set. Despite being not general to execute any application, ASIPs are highly preferred in the embedded systems industry where the devices are produced to satisfy a certain type of application domain/s (either intra-domain or inter-domain). Typically, ASIPs are designed from a base-processor and functionalities are added for applications. This paper studies the multi-application ASIPs and their instruction sets, extensively analysing the instructions for inter-domain and intra-domain designs. Metrics analysed are the reusable instructions and the extra cost to add a certain application. A wide range of applications from various application benchmarks (MiBench, MediaBench and SPEC2006) and domains are analysed for two different architectures (ARM-Thumb and PISA). Our study shows that the intra-domain applications contain larger number of common instructions, whereas the inter-domain applications have very less common instructions, regardless of the architecture (and therefore the ISA).

关键词： application specific integrated circuits embedded systems instruction sets microprocessor chips network synthesis

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A high-level model of embedded flash energy consumption

A high-level model of embedded flash energy consumption

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： James Pallister Kerstin Eder Simon J. Hollis Jeremy Bennett University of Bristol Embecosm

The alignment of code in the flash memory of deeply embedded SoCs can have a large impact on the total energy consumption of a computation. We investigate the effect of code alignment in six SoCs and find that a large proportion of this energy (up to 15% of total SoC energy consumption) can be saved by changes to the alignment. A flexible model is created to predict the read-access energy consumption of flash memory on deeply embedded SoCs, where code is executed in place. This model uses the instruction level memory accesses performed by the processor to calculate the flash energy consumption of a sequence of instructions. We derive the model parameters for five SoCs and validate them. The error is as low as 5%, with a 11% average normalized RMS deviation overall. The scope for using this model to optimize code alignment is explored across a range of benchmarks and SoCs. Analysis shows that over 30% of loops can be better aligned. This can significantly reduce energy while increasing code size by less than 4%. We conclude that this effect has potential as an effective optimization, saving significant energy in deeply embedded SoCs.

关键词： Ash Energy consumption System-on-chip Memory management Random access memory Optimization Nonvolatile memory

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Effective Profiling for Data-Intensive GPU Programs: Work-in-Progress

Effective Profiling for Data-Intensive GPU Programs: Work-in...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Hwiwon Kim Hyunjun Kim Hwansoo Han Sungkyunkwan University Suwon Korea College of Computing Sungkyunkwan University Suwon Korea

ISBN: (数字)9781728191928

ISBN: (纸本)9781728191935

GPU profilers have been successfully used to analyze bottlenecks and slowdowns of GPU programs. Several instrumentation tools for profiling GPU binaries are introduced, but these tools take little consideration into GPU architectures. In this paper, we investigate common factors of performance degradation on existing GPU profilers and provide design guide to improve the performance.

关键词： Degradation embedded systems Computer aided software engineering Instruments Graphics processing units Tools

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