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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"
381 条 记 录,以下是271-280 订阅
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Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies
Simultaneously optimizing DRAM cache hit latency and miss ra...
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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)
作者: Fazal Hameed Lars Bauer Jörg Henkel Chair for Embedded Systems (CES) Karlsruhe Institute of Technology (KIT) Germany
Two key parameters that determine the performance of a DRAM cache based multi-core system are DRAM cache hit latency (HL) and DRAM cache miss rate (MR), as they strongly influence the average DRAM cache access latency... 详细信息
来源: 评论
Optimization of multi-channel BCH error decoding for common cases
Optimization of multi-channel BCH error decoding for common ...
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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)
作者: Russ Dill Aviral Shrivastava Hyunok Oh Arizona State University Hanyang University
This paper proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. We break the BCH decoding process into its three basic blocks: syndrome calculation, the error locator polyn... 详细信息
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A new high resolution frequency and phase synthesis method based on 'Flying-Adder' architecture
A new high resolution frequency and phase synthesis method b...
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IEEE international conference on Semiconductor Electronics
作者: Gharaee, Hossein Tathesari, Elham Tarbiat Modares Univ Tehran Iran Shariati Univ Tehran Iran
High speed electronic systems demand frequency synthesizer of high resolution, wide bandwidth and fast switching speed. The "Flying-Adder" architecture is a frequency and phase synthesis technique that is ba... 详细信息
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Platform-dependent code generation for embedded real-time software
Platform-dependent code generation for embedded real-time so...
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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)
作者: BaekGyu Kim Linh T. X. Phan Oleg Sokolsky Lnsup Lee University of Pennsylvania
Code generation for embedded systems is challenging, since the generated code (e.g., C code) is expected to run on a heterogeneous set of target platforms with different characteristics, such as hardware/software arch... 详细信息
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A Memory Interface for Multi-Purpose Multi-Stream Accelerators
A Memory Interface for Multi-Purpose Multi-Stream Accelerato...
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6th embedded systems Week (ESWEEK)
作者: Girbal, Sylvain Temam, Olivier Yehia, Sami Berry, Hugues Li, Zheng Thales Res & Technol Embedded Syst Lab Palaiseau France INRIA Saclay ALCHEMY Grp Orsay France
Power and programming challenges make heterogeneous multicores composed of cores and ASICs an attractive alternative to homogeneous multi-cores. Recently, multi-purpose loop-based generated accelerators have emerged a... 详细信息
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Does customizing inexactness help over simplistic precision (bit-width) reduction? A case study
Does customizing inexactness help over simplistic precision ...
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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)
作者: Ashutosh Ingole Biswaroop Maiti John Augustine Krishna Palem Dept. of Computer Science and Engineering IIT Madras Dept. of Computer Science Rice University
In the last two decades, energy has become a crucial resource whose consumption must be minimized while designing computing systems. This has affected every aspect of computing ranging from large scale supercomputers ... 详细信息
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Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
Data reuse driven energy-aware MPSoC co-synthesis of memory ...
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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis
作者: Issenin, Ilya Dutt, Nikil University of California Irvine CA 92697
The memory subsystem of a complex multiprocessor systems-on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both ... 详细信息
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Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study
Instruction-set Selection for Multi-application based ASIP D...
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IEEE 6th international conference on Information and Automation for Sustainability (ICIAFS)
作者: Ragel, Roshan Radhakrishnan, Swarnalatha Ambrose, Angelo Univ Peradeniya Dept Comp Engn Peradeniya Sri Lanka Univ New SouthWales Sch Comp Sci & Engn Sydney NSW 2052 Australia
Efficiency in embedded systems is paramount to achieve high performance while consuming less area and power. Processors in embedded systems have to be designed carefully to achieve such design constraints. Application... 详细信息
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A high-level model of embedded flash energy consumption
A high-level model of embedded flash energy consumption
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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)
作者: James Pallister Kerstin Eder Simon J. Hollis Jeremy Bennett University of Bristol Embecosm
The alignment of code in the flash memory of deeply embedded SoCs can have a large impact on the total energy consumption of a computation. We investigate the effect of code alignment in six SoCs and find that a large... 详细信息
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Effective Profiling for Data-Intensive GPU Programs: Work-in-Progress
Effective Profiling for Data-Intensive GPU Programs: Work-in...
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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)
作者: Hwiwon Kim Hyunjun Kim Hwansoo Han Sungkyunkwan University Suwon Korea College of Computing Sungkyunkwan University Suwon Korea
GPU profilers have been successfully used to analyze bottlenecks and slowdowns of GPU programs. Several instrumentation tools for profiling GPU binaries are introduced, but these tools take little consideration into G... 详细信息
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