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MNEMEE - A Framework for Memory Management and Optimization of Static and Dynamic Data in MPSoCs

MNEMEE - A Framework for Memory Management and Optimization ...

引用

6th embedded systems Week (ESWEEK)

作者： Mallik, Arindam Marwedel, Peter Soudris, Dimitrios Stuijk, Sander IMEC VZW B-3000 Leuven Belgium TU Dortmund Dortmund Germany Natl Tech Univ Athens GR-10682 Athens Greece Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781605589039

As embedded systems are becoming the center of our digital life, system design becomes progressively harder. The integration of multiple features on devices with limited resources requires careful and exhaustive exploration of the design search space in order to efficiently map modern applications to an embedded multi-processor platform. The MNEMEE project [1] addresses this challenge by offering a unique integrated tool flow that performs source-to-source transformations to automatically optimize the original source code and map it on the target platform. The optimizations aim at reducing the number of memory accesses and the required memory storage of both dynamically and statically allocated data. Furthermore, the MNEMEE tool flow performs optimal assignment of all data on the memory hierarchy of the target platform. Overall, the MNEMEE techniques embedded in it will lead to more cost efficient systems that offer a better performance and lower energy consumption. This tutorial gives an overview of the MNEMEE tool flow. The objective of the tutorial is to familiarize the audience with the tool framework and the optimizations used in the individual tools. The tutorial also features a demonstration of the tool flow. This demonstration shows that the tools developed in the MNEMEE project provide a user-friendly and efficient framework for MPSoC programming and memory management.

关键词： MPSoc Design embedded software Memory Management Automatic Parallelization

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Tutorial: Designing an Edge Inferencing Accelerator with High- Level synthesis

Tutorial: Designing an Edge Inferencing Accelerator with Hig...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Russell Klein Petri Solanti Siemens Wilsonville Oregon USA Siemens Munich Germany

Convolutional neural networks are computationally intensive. A single inference can require billions of multiply/accumulate operations. In the datacenter, where ample power, space, and cooling are available, high powered CPUs or GPUs can be used. However, in the embedded space, edge systems often do not have the power or compute capability to perform these calculations. Further, edge applications often have hard real-time requirements. This combination necessitates the use of hardware accelerators for performing inferencing calculations. A bespoke accelerator will deliver the highest performance and efficiency, outperforming configurable IP by an order of magnitude or more. But transforming an algorithm developed in a machine learning framework, often in Python, into silicon can be a daunting task. Traditional hardware design is performed at the register transfer level (RTL). When designing in RTL, hardware engineers describe every register, every operator, and every connection in the design. At this level of detail, it is impractical for the designer to explore significantly different implementation architectures. High-Level synthesis (HLS) allows a hardware engineer to operate at a higher level of abstraction – specifically, at the algorithmic level – and use the facilities of the HLS tool to automate the conversion of the algorithm description into synthesizable RTL. This enables a broad set of architectures to be created and evaluated. And at the algorithmic level, the description of the hardware is much closer to the original Python, making the conversion faster, easier, and more natural.

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Generic architecture description for retargetable compilation and synthesis of application-specific pipelined IPs

Generic architecture description for retargetable compilatio...

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24th international conference on Computer Design

作者： Gorjiara, Bita Reshadi, Mehrdad Gajski, Daniel Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92717 USA

ISBN: (纸本)9780780397064

Constraints of embedded systems and the shrinking time-to-market have elevated the importance of designer productivity and design predictability more than ever. To improve productivity, in ASIP approaches the system is designed with software and executed on a customized processor. In ASIP design flow, the processor is described in an architecture Description Language (ADL) and the toolset is generated from that ADL automatically. However, in these approaches design predictability is low because the designer has little or no control over the quality of the final implementation. In this paper, we present a new design approach where the target processor or Intellectual Property (IT) does not have any predefined instruction-set and its datapath component netlist is described in a Generic Netlist Representation (GNR). The GNR is used by the toolset to generate the controller of the IP and the RTL of the design. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. We have also developed a web-based interface for our toolset, so that users can upload and evaluate new IPs described in GNR.

关键词： Productivity

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Research Issues in Smart Phones, Notepads and Related Services 12

Research Issues in Smart Phones, Notepads and Related Servic...

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international conference on compilers, architectures and synthesis for embedded systems

作者： Petri Liuha Kari Pehkonen Juhani Rummukainen Veli-Pekka Vatula Tatu Koljonen (organizer) Nokia Finland Renesas Mobile Finland ST-Ericsson Finland Intel Finland VTT Finland

ISBN: (纸本)9781450314244

Networked embedded systems are building intelligence to everyplace. There are more and more incentives to open proprietary data and interfaces for free to third party service developers. This development called "ubiquitous communication" or "internet of things" requires new dominant design for user interfaces, interoperability and contextuality. In the user interface design, for example, we have witnessed the growth of the smartphone display, which today is at about 5 inches. Developing the new dominant designs is part of the "ecosystem war", where the most attractive platforms are getting the most developer, users and profits. The four speakers of today represent companies that have entered the competition with different platforms, assets and strategies and hence have different research challenges to be solved..

关键词： user interface design Smartphone embedded systems Interoperability Platform Companies Legal Services Internet of things Consumers Third party Hence User Interface Device Component

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Energy-interference-free system and toolchain support for energy-harvesting devices

Energy-interference-free system and toolchain support for en...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Alexei Colin Alanson P. Sample Brandon Lucia Carnegie Mellon University Disney Research Pittsburgh

Energy-harvesting computers eschew tethered power and batteries by harvesting energy from their environment. The devices gather energy into a storage element until they have enough energy to power a computing device. Once powered, the device functions until its energy is depleted, when it browns out and gathers more energy. Software on such computing devices executes intermittently, as power is available. An intermittent program execution may be interrupted by a power failure at any point and with each interruption, the volatile state of the device (e.g., register file, RAM) is erased, and its non-volatile state (e.g., FRAM) is retained. Recent work [3] defined and characterized the intermittent execution model, in which a program's execution spans periods of execution perforated by power failures. Our position is that designers of system and toolchain support for energy-harvesting devices should treat energy-interference-freedom and intermittence as first-class design concerns in future systems, methodologies, and techniques. From this position, we discuss the design of an energy-interference-free platform for monitoring and manipulating the energy and device state of an energy-harvesting device. We see our platform as an essential step toward a toolchain for energy-harvesting devices that supports debugging, testing, and analysis of realistic, intermittent executions.

关键词： Debugging Monitoring Computer bugs Energy states Nonvolatile memory Energy storage embedded systems

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cases 2021 message from the program chairs

Proceedings - 2021 International Conference on Compilers, Ar...

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Proceedings - 2021 international conference on compilers, architectures, and synthesis for embedded systems, cases 2021 2021年 VI页

作者： Ogras, Umit Panda, Preeti Ranjan

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2006 international conference on Computer Engineering and systems, ICCES' 06

2006 International Conference on Computer Engineering and Sy...

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2006 international conference on Computer Engineering and systems, ICCES'06

ISBN: (纸本)1424402719

The proceedings contain 80 papers. The topics discussed include: a tutorial on quantum computation and communication;global false coupling interaction-aware hierarchical timing analysis;quadrature direct digital frequency synthesizer using FPGA;evolutionary synthesis of synchronous finite state machines;adaptive fuzzy decentralized control for a class of large-scale nonlinear systems with MIMO subsystems;hierarchical fuzzy controller for robot manipulator;indirect adaptive fuzzy coordinated excitation and SVC control for multi-machine power system;discrete-time averaging of converters with PWM DC-DC feedback;IP encapsulation: approach and case study;monitoring serial communications in microcontroller based embedded systems;and interface architecture generation for IP integration in SoC design.

关键词： Decentralized control

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Predictable Dynamic embedded Data Processing

Predictable Dynamic Embedded Data Processing

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international conference on embedded Computer systems - architectures, Modeling and Simulation (IC-SAMOS)

作者： Geilen, Marc Stuijk, Sander Basten, Twan Eindhoven Univ Technol Dept Elect Engn NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781467322973;9781467322966

Cyber-physical systems interact with their physical environment. In this interaction, non-functional aspects, most notably timing, are essential to correct operation. In modern systems, dynamism is introduced in many different ways. The additional complexity threatens timely development and reliable operation. Applications often have different modes of operation with different resource requirements and different levels of required quality-of-service. Moreover, multiple applications in dynamically changing combinations share a platform and its resources. To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done. This requires a model-driven design approach in which timing of interaction with the physical environment is taken into consideration;formal models capture applications and their platforms in the physical environment. Moreover, platforms with resources and resource arbitration are needed that allow for predictable and reliable behavior to be realized. Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time. In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time management approach to deal with dynamic use-cases at run-time. A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use. The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient knapsack heuristic.

关键词： Runtime physical environment Platform resource requirements operation mode Time Management management of resources Surgery dynamism

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Continuous and embedded Learning for multi-agent systems

Continuous and Embedded Learning for multi-agent systems

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IEEE/RSJ international conference on Intelligent Robots and systems

作者： Kira, Zsolt Schultz, Alan C. Georgia Inst Technol Mobile Robot Lab Atlanta GA 30332 USA USN Res Lab Navy Ctr Appl Res AI Washington DC 20375 USA

ISBN: (纸本)9781424402588

This paper describes multi-agent strategies for applying Continuous and embedded Learning (CEL). In the CEL architecture [1], an agent maintains a simulator based on its current knowledge of the world and applies a learning algorithm that obtains its performance measure using this simulator. The simulator is updated to reflect changes in the environment or robot state that can be detected by a monitor, such as sensor failures. In this paper, we adapt this architecture to a multi-agent setting in which the monitor is communicated among the team members effectively creating a distributed monitor. The parameters of the current control algorithm (in our case rulebases learned by Genetic Algorithms) used by all of the agents are added to the monitor as well, allowing for cooperative learning. We show that communication of agent status (e.g. failures) among the team members allows the agents to dynamically adapt to team properties, in this case team size. Furthermore, we show that an agent is able to switch between specializing within a section of the domain when there are many team members and generalizing to other parts of the domain when the rest of the team members are disabled. Finally, we also discuss future potential of this method, most notably in the creation of a Distributed Case Based Reasoning system in which the cases are actual Genetic Algorithm population members that can be swapped among team members.

关键词： genetic algorithms multi-agent coevolutionary systems cooperative coevolution multi-agent communication

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NUVA: Architectural support for runtime verification of parametric specifications over multicores

NUVA: Architectural support for runtime verification of para...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Ahmed Nassar Fadi J. Kurdahi Wael Elsharkasy Center for Embedded and Cyber-physical Systems University of California Irvine CA USA

Runtime Verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification methods. To address the substantial performance and power overhead of pure software RV frameworks, this paper introduces NUVA, which stands for nonuniform verification architecture, a distributed automata-based RV architecture for parametric specifications in the form of parameterized finite-state automata, with a case study over a cache-coherent nonuniform-memory-access (ccNUMA) multiprocessor. The core of NUVA is a coherent distributed automata transactional memory (ATM) that efficiently maintains states of a dynamic population of automata checkers organized into a rooted dynamic directed acyclic graph (DAG) concurrently shared among all processor nodes. A cycle-accurate model of a ccNUMA multiprocessor confirms that performance slowdown is 1~3% and NoC message traffic increases by 10~15% at parametric event density 1 of 0.025 EPI for two compute-intensive scientific benchmarks having irregular concurrent data structures. The detailed architecture and implementation metrics in TSMC 40nm CMOS technology are presented. NUVA can be dimensioned to incur average total power overhead of less than 140mW and area overhead of 4mm 2 for a quad-core multiprocessor chip, at operating frequency of 250MHz. It is also estimated to incur 1.9~2.6% area overhead and 0.5~1% power overhead when integrated with Intel's family of high-end desktop and mobile quad-core processors operating at 1.6~3.2GHz. Our silicon implementation achieves average performance 2 of 1.5 MEPS/mW. For a processor core with 5 MIPS/mW, this corresponds to a 3.2% drop in energy efficiency at parametric event density of 0.01 EPI.

关键词： Monitoring Automata Runtime Hardware Computer bugs Cost accounting Semantics

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