The proceedings contain 21 papers. The topics discussed include: ILP-based modulo scheduling for high-level synthesis;handling large data sets for high-performance embedded applications in heterogeneous systems-on-chi...
ISBN:
(纸本)9781450344821
The proceedings contain 21 papers. The topics discussed include: ILP-based modulo scheduling for high-level synthesis;handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip;theoretical foundations for workload modeling with implications on power optimization;thermal-driven resource allocation and application mapping for complex many core systems;runtime management of adaptive MPSoCs for graceful degradation;towards the design of fault-tolerant mixed-criticality systems on multicores;COMET: communication-optimised multi-threaded error-detection technique;neural network transformation and co-design under neuromorphic hardware constraints;cambricon: an instruction set architecture for neural networks;RRAM based learning acceleration;a real-time digital-microfluidic platform for epigenetics;LOCUS: low-power customizable many-core architecture for wearables;D-PUF: an intrinsically reconfigurable DRAM PUF for device authentication in embeddedsystems;hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous Manycore platforms;matrix multiplication beyond auto-tuning: rewrite-based GPU code generation;and a jump-target identification method for multi-architecture static binary translation.
The proceedings contain 25 papers. The topics discussed include: low-overhead virtualization of mobile platforms;a method-based ahead-of-time compiler for android applications;studying optimal spilling in the light of...
ISBN:
(纸本)9781450307130
The proceedings contain 25 papers. The topics discussed include: low-overhead virtualization of mobile platforms;a method-based ahead-of-time compiler for android applications;studying optimal spilling in the light of SSA;an efficient heuristic for instruction scheduling on clustered VLIW processors;graph-coloring and treescan register allocation using repairing;a unified approach to eliminate memory accesses early;an evaluation of different modeling techniques for iterative compilation;a novel thread scheduler design for polymorphic embeddedsystems;realizing near-true voltage scaling in variation-sensitive L1 caches via fault buffers;FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation;smart cache cleaning: energy efficient vulnerability reduction in embedded processors;cost-effective safety and fault localization using distributed temporal redundancy;and stochastic computing: embracing errors in architecture and design of processors and applications.
The proceedings contain 2 papers. The topics discussed include: work-in-progress: fast generation of optimized execution plans for parameterizable CNN accelerators;and work-in-progress: multiple approximate instances ...
ISBN:
(纸本)9781450383783
The proceedings contain 2 papers. The topics discussed include: work-in-progress: fast generation of optimized execution plans for parameterizable CNN accelerators;and work-in-progress: multiple approximate instances in neural processing units for energy-efficient circuit synthesis.
The proceedings contain 23 papers. The topics discussed include: side channel attacks and the non volatile memory of the future;a cost-effective tag design for memory data authentication in embeddedsystems;static sec...
ISBN:
(纸本)9781450314244
The proceedings contain 23 papers. The topics discussed include: side channel attacks and the non volatile memory of the future;a cost-effective tag design for memory data authentication in embeddedsystems;static secure page allocation for light-weight dynamic information flow tracking;a hybrid just-in-time compiler for Android: comparing JIT types and the result of cooperation;power agnostic technique for efficient temperature estimation of multicore embeddedsystems;scenario-based design flow for mapping streaming applications onto on-chip many-core systems;the RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems;function inlining and loop unrolling for loop acceleration in reconfigurable processors;energy efficient hybrid display and predictive models for embedded and mobile systems;and energy efficient special instruction support in an embedded processor with compact ISA.
The proceedings contain 21 papers. The topics discussed include: special session: a quantifiable approach to approximate computing;special session: hardware approximate computing: how, why, when and where?;work-in-pro...
ISBN:
(纸本)9781450351843
The proceedings contain 21 papers. The topics discussed include: special session: a quantifiable approach to approximate computing;special session: hardware approximate computing: how, why, when and where?;work-in-progress: efficient pulsed-latch implementation for multiport register files;work-in-progress: a 'high resilience' mode to minimize so error vulnerabilities in arm Cortex-R CPU pipelines;work-in-progress: balanced cache bypassing for critical warp reduction;work-in-progress: incremental training of CNNs for user customization;work-in-progress: prediction based convolution neural network acceleration;and work-in-progress: optimizing DCNN FPGA accelerator design for handwritten Hangul character recognition.
This paper presents MLGOPerf;the first end-to-end framework capable of optimizing performance using LLVM's ML-Inliner. It employs a secondary ML model to generate rewards used for training a retargeted Reinforceme...
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ISBN:
(数字)9781665472968
ISBN:
(纸本)9781665472968
This paper presents MLGOPerf;the first end-to-end framework capable of optimizing performance using LLVM's ML-Inliner. It employs a secondary ML model to generate rewards used for training a retargeted Reinforcement learning agent, previously used as the primary model by MLGO. It does so by predicting the post-inlining speedup of a function under analysis and it enables a fast training framework for the primary model which otherwise wouldn't be practical. The experimental results show MLGOPerf is able to gain up to 1.8% with respect to LLVM's optimization at O3 when trained for performance on SPEC CPU2006. Furthermore, the proposed approach provides up to 26% increased opportunities to autotune code regions for our benchmarks which can be translated into an additional 3.7% speedup value.
Dynamic partial reconfiguration (DPR) enables the design and implementation of flexible, scalable and robust adaptive systems. We present an FPGA-based DPR flow for partially reconfigurable heterogeneous SoCs that use...
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ISBN:
(数字)9781665472968
ISBN:
(纸本)9781665472968
Dynamic partial reconfiguration (DPR) enables the design and implementation of flexible, scalable and robust adaptive systems. We present an FPGA-based DPR flow for partially reconfigurable heterogeneous SoCs that uses an incremental compilation technique to reduce the total FPGA compilation time.
This report discusses embeddedsystems Week 2006, which took place 22-27 October in Seoul. ESWEEK 2006 included three parallel conferences: CODES+ISSS (the internationalconference on Hardware/Software Codesign and Sy...
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GeMS is a customisable, open-source toolkit for generating random, yet constrained, modulo scheduling problems with a known optimal initiation interval. These can then be used to evaluate the behavior of different sch...
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ISBN:
(纸本)9781538655641
GeMS is a customisable, open-source toolkit for generating random, yet constrained, modulo scheduling problems with a known optimal initiation interval. These can then be used to evaluate the behavior of different scheduling algorithms under controlled conditions.
In this paper, we introduce Context-aware Adaptive embeddedsystems (CAES) and illustrate the complexity of early design space exploration (DSE) process using examples of two real systems that are being implemented in...
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ISBN:
(纸本)9781450369237
In this paper, we introduce Context-aware Adaptive embeddedsystems (CAES) and illustrate the complexity of early design space exploration (DSE) process using examples of two real systems that are being implemented in our group. Next, we give an overview of the proposed approach and present some preliminary results.
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