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Context-sensitive timing simulation of binary embedded software

Context-sensitive timing simulation of binary embedded softw...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Sebastian Ottlik Stefan Stattelmann Alexander Viehl Wolfgang Rosenstiel Oliver Bringmann FZI Research Center for Information Technolog Karlsruhe Germany ABB Corporate Research Research Area Software Wallstadter Straße Ladenburg Germany University of Tübingen Tuebingen Germany

We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the microarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional simulation.

关键词： Context Timing Analytical models Data models Software Databases Context modeling

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Enabling Energy-efficient AI Computing: Leveraging Application-specific Approximations : (Education Class)

Enabling Energy-efficient AI Computing: Leveraging Applicati...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Salim Ullah Siva Satyendra Sahoo Akash Kumar Chair of Embedded Systems Ruhr-Universität Bochum Bochum Germany Technology Enablement and Design Interuniversity Microelectronics Centre Leuven Belgium

ISBN: (数字)9798350356373

ISBN: (纸本)9798350356380

The widespread adoption of Artificial intelligence and Machine Learning (AI/ML) models across various fields, such as healthcare, autonomous vehicles, smart agriculture, and industrial automation, has led to a growing demand for efficient and scalable AI/ML solutions. However, as AI/ML algorithms grow more complex, their substantial memory requirements and high energy consumption pose significant challenges for deployment on resource-constrained embedded systems, such as wearable health monitors and IoT devices. To this end, various techniques, such as model pruning, knowledge distillation, quantization of model parameters, and employing approximate arithmetic operators, are commonly explored to overcome these challenges [1] .

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Page Reuse in Cyclic Thrashing of GPU Under Oversubscription: Work-in-Progress

Page Reuse in Cyclic Thrashing of GPU Under Oversubscription...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Dojin Park Hyunjun Kim Hwansoo Han Sungkyunkwan University Suwon Republic of Korea

ISBN: (数字)9781728191928

ISBN: (纸本)9781728191935

Nvidia GPUs can oversubscribe CPU-side RAM, elevating GPU programmability and enabling GPU to use data beyond the size of GPU memory. However, oversubsrciption accompanies overhead of constant exchange of pages between the GPU and the CPU. To this problem, while previous works implemented and experimented solutions overhead in GPU simulators, we propose a new method implemented in the driver, which runs actual GPU hardware. We developed algorithms that detect repeated page replacement of the pages and pin pages in GPU memory to be reused in the future without replacement.

关键词： embedded systems Computer aided software engineering Graphics processing units Random access memory Hardware Pins

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Implementing Dynamic Implied Addressing Mode for Multi-Output Instructions

Implementing Dynamic Implied Addressing Mode for Multi-Outpu...

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6th embedded systems Week (ESWEEK)

作者： Youn, Jonghee M. Lee, Jongwon Paek, Yunheung Kim, Jongwung Cho, Jeonghun Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul South Korea Kyungpook Natl Univ Sch Elect Engn & Comp Sci Daegu South Korea

ISBN: (纸本)9781605589039

The ever-increasing demand for faster execution time, smaller resource usage and lower energy consumption has compelled architects of embedded processors to adopt more specialized hardware features with irregular data paths and heterogeneous registers that are customized to the needs of their target applications. These processors consequently provide a rich set of specialized instructions in order to enable programmers to access these features. Such an instruction is typically a multi-output instruction (MOI), which outputs multiple results parallely in order to exploit inherent underlying hardware parallelism. Earlier study has exhibited that MOIs help to enhance performance in aspect of instruction counts and code size. However, as MOIs require more operands, they tend to increase not only the size of the instruction set but also the size of individual instructions. This can be a serious setback for embedded processors, which are mostly subject to strong resource limitations (particularly in this case, limited instruction encoding space). For this reason, these processors are often allowed to include only a very small subset of the total desired MOIs in their instruction sets, despite there can be sufficient silicon real estate to accommodate these specialized MOIs. To attack this problem, we introduce a novel instruction encoding scheme based on the dynamic implied addressing mode (DIAM). In this paper, we will discuss how we have overcome the encoding space problem for our target embedded processor whose instruction set has been augmented with a variety of MOIs. Our DIAM-based encoding scheme employs a small on-chip buffer to supplement extra encoding information for MOIs at run time. The empirical results are promising: the scheme allows us to encode many more MOIs for our processor;thereby helping us to achieve considerable reduction of code size as well as running time after the DIAM is additively implemented in the original architecture.

关键词： embedded Processor Compiler Optimization

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NUVA: Architectural support for runtime verification of parametric specifications over multicores

NUVA: Architectural support for runtime verification of para...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Ahmed Nassar Fadi J. Kurdahi Wael Elsharkasy Center for Embedded and Cyber-physical Systems University of California Irvine CA USA

Runtime Verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification methods. To address the substantial performance and power overhead of pure software RV frameworks, this paper introduces NUVA, which stands for nonuniform verification architecture, a distributed automata-based RV architecture for parametric specifications in the form of parameterized finite-state automata, with a case study over a cache-coherent nonuniform-memory-access (ccNUMA) multiprocessor. The core of NUVA is a coherent distributed automata transactional memory (ATM) that efficiently maintains states of a dynamic population of automata checkers organized into a rooted dynamic directed acyclic graph (DAG) concurrently shared among all processor nodes. A cycle-accurate model of a ccNUMA multiprocessor confirms that performance slowdown is 1~3% and NoC message traffic increases by 10~15% at parametric event density 1 of 0.025 EPI for two compute-intensive scientific benchmarks having irregular concurrent data structures. The detailed architecture and implementation metrics in TSMC 40nm CMOS technology are presented. NUVA can be dimensioned to incur average total power overhead of less than 140mW and area overhead of 4mm 2 for a quad-core multiprocessor chip, at operating frequency of 250MHz. It is also estimated to incur 1.9~2.6% area overhead and 0.5~1% power overhead when integrated with Intel's family of high-end desktop and mobile quad-core processors operating at 1.6~3.2GHz. Our silicon implementation achieves average performance 2 of 1.5 MEPS/mW. For a processor core with 5 MIPS/mW, this corresponds to a 3.2% drop in energy efficiency at parametric event density of 0.01 EPI.

关键词： Monitoring Automata Runtime Hardware Computer bugs Cost accounting Semantics

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Predictable Dynamic embedded Data Processing

Predictable Dynamic Embedded Data Processing

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international conference on embedded Computer systems - architectures, Modeling and Simulation (IC-SAMOS)

作者： Geilen, Marc Stuijk, Sander Basten, Twan Eindhoven Univ Technol Dept Elect Engn NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781467322973;9781467322966

Cyber-physical systems interact with their physical environment. In this interaction, non-functional aspects, most notably timing, are essential to correct operation. In modern systems, dynamism is introduced in many different ways. The additional complexity threatens timely development and reliable operation. Applications often have different modes of operation with different resource requirements and different levels of required quality-of-service. Moreover, multiple applications in dynamically changing combinations share a platform and its resources. To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done. This requires a model-driven design approach in which timing of interaction with the physical environment is taken into consideration;formal models capture applications and their platforms in the physical environment. Moreover, platforms with resources and resource arbitration are needed that allow for predictable and reliable behavior to be realized. Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time. In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time management approach to deal with dynamic use-cases at run-time. A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use. The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient knapsack heuristic.

关键词： Runtime physical environment Platform resource requirements operation mode Time Management management of resources Surgery dynamism

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Special Session - Non-Volatile Memories: Challenges and Opportunities for embedded System architectures with Focus on Machine Learning Applications

Special Session - Non-Volatile Memories: Challenges and Oppo...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Jörg Henkel Lokesh Siddhu Lars Bauer Jürgen Teich Stefan Wildermann Mehdi Tahoori Mahta Mayahinia Jeronimo Castrillon Asif Ali Khan Hamid Farzaneh João Paulo C. De Lima Jian-Jia Chen Christian Hakert Kuan-Hsun Chen Chia-Lin Yang Hsiang-Yun Cheng Karlsruhe Institute of Technology (KIT) Germany Friedrich-Alexander-Universität Erlangen-Nürnberg Germany TU Dresden Germany TU Dortmund University Germany Lamarr Inst. for ML and AI Germany University of Twente The Netherlands National Taiwan University Taiwan Academia Sinica Taiwan

This paper explores the challenges and opportunities of integrating non-volatile memories (NVMs) into embedded systems for machine learning. NVMs offer advantages such as increased memory density, lower power consumption, non-volatility, and compute-in-memory capabilities. The paper focuses on integrating NVMs into embedded systems, particularly in intermittent computing, where systems operate during periods of available energy. NVM technologies bring persistence closer to the CPU core, enabling efficient designs for energy-constrained scenarios. Next, computation in resistive NVMs is explored, highlighting its potential for accelerating machine learning algorithms. However, challenges related to reliability and device non-idealities need to be addressed. The paper also discusses memory-centric machine learning, leveraging NVMs to overcome the memory wall challenge. By optimizing memory layouts and utilizing probabilistic decision tree execution and neural network sparsity, NVM-based systems can improve cache behavior and reduce unnecessary computations. In conclusion, the paper emphasizes the need for further research and optimization for the widespread adoption of NVMs in embedded systems presenting relevant challenges, especially for machine learning applications.

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Team up: Cooperative memory management in embedded systems

Team up: Cooperative memory management in embedded systems

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Isabella Stilkerich Philip Taffner Christoph Erhardt Christian Dietrich Christian Wawersich Michael Stilkerich Friedrich-Alexander University Erlangen-Nuremberg Germany

The use of a managed, type-safe languages such as Java in realtime and embedded systems can offer productivity and, in particular, safety and dependability benefits over the dominating unsafe languages at reasonable costs. A JVM that has dynamic memory-management needs to provide an implicit memory-management strategy, that is, for example, a garbage collector (GC) or stack allocation provided by the escape analysis of the JVM's compiler: Explicit management of dynamically allocated memory (i.e., by use of functions such as C's malloc () and free()) is vulnerable to programming errors such as neglected or false memory release operations causing memory leaks or dangling pointers. Such operations have the potential to break the soundness of the type system and are therefore usually not available for strongly typed languages. Type-safe languages in combination with static analyses - which respect hardware as well as system-specific information - can efficiently be employed to provide a runtime system including memory management (MM) that is specifically suited to an embedded application on a particular hardware device. In the context of this paper, we present novel memory-management strategy we implemented in our KESO JVM. It is a latency-aware garbage-collection algorithm called LAGC. Also, we introduce the static analyses that can assist LAGC. The application developers have to ensure that there is enough time for the GCs to run. Hardware characteristics such as soft-error proneness of the hardware or the memory layout can also be taken into consideration as demanded by the system configuration. This is achieved by integrating the GCs in the design process of the whole system just as any other user application, which is the reason why this approach is called cooperative memory management. The suggested strategies require reasonably low overhead.

关键词： Memory management Runtime Hardware Java embedded systems Random access memory Resource management

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Automatic generation of transaction level models for rapid design space exploration

Automatic generation of transaction level models for rapid d...

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CODES+ISSS 2006: 4th international conference on Hardware Software Codesign and System synthesis

作者： Shin, Dongwan Gerstlauer, Andreas Peng, Junyu Dömer, Rainer Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine CA 92697 United States

ISBN: (纸本)1595933700

Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate such transaction-level models from abstract input descriptions. Designers have to write such models manually, which is a tedious and error-prone task, and one of bottlenecks in improving designer's productivity. In this paper, we propose a method to generate transaction-level models from virtual architecture models where components communicate via abstract message-passing channels. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness and benefits of our approach for rapid, early exploration of communication design space. © Copyright 2006 ACM.

关键词： Logic design

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Work in Progress: An Confidentiality and Integrity Scheme for the Distributed Shared Memory of embedded Multi-core System

Work in Progress: An Confidentiality and Integrity Scheme fo...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Pengfei Yang Quan Wang Xiaokun Huang Xin Mi School of Computer Science and Technology Xidian University Xi'an China

For the multi-core systems, the distributed shared memory(DSM) has become the mainstream for its scalability and portable. A new security policy needs to be designed to protect the data in the DSM. In this paper, a memory confidentiality protection method is designed based on the dynamic key and compression counter(CPS), The method improves the encryption efficiency significantly and solves the problem of the ciphertext re-encrypting when the counter overflows. A memory integrity protection method is proposed based on a multi-granularity incremental hash tree(MIT), to reduce the memory occupation and the amount of calculation. A secondary conversion method of the ciphertext is designed so that the data can be transmitted among the untrusted processing units without sharing the private keys. The optimized methods are quantitatively evaluated using the SimpleScalar architecture simulation tool. Experimental results show that the performance degradation of the proposed confidentiality protection method is 11.84% on average, which is better than the split counter mode(SPLIT) method and the block encryption method. The proposed integrity protection method has a 48.72% reduction in memory occupation and a 32.62% improvement in the performance reduction rate compared with the hash-tree method, it's better than the multi-grained hash tree(MGT) method and the Bonsai Merkle Tree(BMT) method too.

关键词： Encryption Memory management Indexes Micromechanical devices System-on-chip

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