检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

350 篇 会议
31 篇 期刊文献

馆藏范围

381 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

266 篇 工学
- 259 篇 计算机科学与技术...
- 173 篇 软件工程
- 67 篇 电气工程
- 48 篇 电子科学与技术（可...
- 33 篇 信息与通信工程
- 23 篇 动力工程及工程热...
- 20 篇 控制科学与工程
- 6 篇 机械工程
- 5 篇 材料科学与工程（可...
- 4 篇 化学工程与技术
- 3 篇 力学（可授工学、理...
- 3 篇 光学工程
- 3 篇 生物工程
- 2 篇 仪器科学与技术
- 2 篇 生物医学工程（可授...
- 1 篇 建筑学
- 1 篇 土木工程
- 1 篇 测绘科学与技术
- 1 篇 石油与天然气工程
74 篇 理学
- 59 篇 数学
- 12 篇 系统科学
- 7 篇 物理学
- 5 篇 统计学（可授理学、...
- 3 篇 化学
- 3 篇 生物学
43 篇 管理学
- 36 篇 管理科学与工程(可...
- 29 篇 工商管理
- 9 篇 图书情报与档案管...
6 篇 经济学
- 6 篇 应用经济学
5 篇 法学
- 5 篇 社会学

主题

115 篇 embedded systems
29 篇 computer archite...
27 篇 hardware
18 篇 embedded system
16 篇 program processo...
10 篇 memory managemen...
9 篇 system-on-chip
8 篇 application soft...
8 篇 throughput
8 篇 random access me...
8 篇 high level synth...
8 篇 field programmab...
7 篇 energy consumpti...
7 篇 computational mo...
7 篇 computer aided s...
7 篇 energy efficienc...
6 篇 runtime
6 篇 reliability
6 篇 real time system...
6 篇 space exploratio...

机构

3 篇 department of co...
3 篇 tech univ denmar...
3 篇 center for embed...
3 篇 embedded systems...
3 篇 department of el...
3 篇 tech univ darmst...
2 篇 friedrich alexan...
2 篇 univ michigan 22...
2 篇 tu dresden
2 篇 center for embed...
2 篇 univ new south w...
2 篇 university of tw...
2 篇 instituto tecnol...
2 篇 school of comput...
2 篇 advanced compute...
2 篇 budapest univ te...
2 篇 univ new south w...
2 篇 univ lille crist...
2 篇 lamarr inst. for...
2 篇 center for embed...

作者

8 篇 dutt nikil
7 篇 shrivastava avir...
7 篇 barua rajeev
6 篇 palem krishna v.
5 篇 dean alexander g...
5 篇 jörg henkel
5 篇 henkel joerg
4 篇 raghunathan anan...
4 篇 ienne paolo
4 篇 madsen jan
4 篇 pozzi laura
4 篇 vahid frank
4 篇 pop paul
4 篇 andreas koch
3 篇 ha soonhoi
3 篇 homayoun houman
3 篇 koch andreas
3 篇 parameswaran sri
3 篇 hu xiaobo sharon
3 篇 marwedel peter

语言

380 篇 英文
1 篇 中文

检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是301-310 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Developing embedded multi-threaded applications with CATAPULTS, a domain-specific language for generating thread schedulers

Developing embedded multi-threaded applications with CATAPUL...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Roper, Matthew D. Olsson, Ronald A. Department of Computer Science University of California Davis Davis CA 95616-8562 United States

ISBN: (纸本)159593149X

This paper describes CATAPULTS, a domain-specific language for creating and testing application-specific user level thread schedulers. Using a domain-specific language to write thread schedulers provides three advantages. First, it modularizes the thread scheduler, making it easy to plug in and experiment with different schedulers. Second, using a domain-specific language for scheduling code helps prevent several of the common programming mistakes that are easy to make when programming in low-level C or assembly. Finally, the CATAPULTS translator has multiple backends that generate code for different languages and libraries. This makes it easy to prototype an embedded application on a regular PC, and then develop the final version on the embedded hardware;the CATAPULTS translator will take care of generating the appropriate code for both the PC proto-type and the final embedded version of the program. Using our implementation of CATAPULTS for Z-World's embedded Rabbit processors, we obtained a performance gain of about 12.6% at the expense of about 12.7% increase in code size for a fairly typical embedded application. Copyright 2005 ACM.

关键词： Formal languages

来源：评论

学校读者我要写书评

暂无评论

Verifiable annotations for embedded Java environments

Verifiable annotations for embedded Java environments

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Chen, Guangyu Kandemir, Mahmut Department of Computer Science and Engineering Pennsylvania State University University Park PA 16802 United States

ISBN: (纸本)159593149X

Many implementations of Java Virtual Machine (JVM) use optimizing dynamic compilation for improving performance of Java applications. However, optimizing compilation is expensive in terms of both time and memory space complexity. Annotations are frequently used to reduce the dynamic compilation overhead in embedded Java environments where the memory budget and CPU speed are limited. However, some annotations can cause the dynamic compiler to generate code that violates the security policy of the JVM. These annotations present a safety problem if they are not verified before being used by the compiler. In this work, we present annotation schemes for three frequently used optimizations: null pointer check removal, value liveness analysis, and array bound check removal. All our annotations can be verified at low cost during dynamic compilation time to guarantee that they do not cause the compiler to generate code that violates the security policy of the JVM. Copyrighl 2005 ACM.

关键词： Java programming language

来源：评论

学校读者我要写书评

暂无评论

Energy management for commodity short-bit-width microcontrollers

Energy management for commodity short-bit-width microcontrol...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Ghattas, Rony Dean, Alexander G. Center for Embedded Systems Research Department of Electrical and Computer Engineering North Carolina State University Raleigh NC 27695 United States

ISBN: (纸本)159593149X

Dynamic frequency scaling and dynamic voltage scaling have been developed to save power and/or energy for general purpose computing platforms and high-end embedded systems. This paper examines the practicality of using these advanced techniques to save power and energy for commodity 8-bit microcontrollers while leveraging their built-in low-power modes. The benefits of the techniques are weighed against their complexity and cost. First, we mathematically model the power dissipation characteristics of 11 popular 8-bit microcontrollers. We then simulate their power dissipation with different power management techniques being applied. The role of the power scheduler, the power supply, and the frequency divider circuit are also described and analyzed. We find that although dynamic voltage scaling renders the lowest energy dissipation for most microcontrollers, it is not always dramatically better than using a combination of dynamic frequency scaling and the built in power down modes, which is much less expensive to implement. Copyright 2005 ACM.

关键词： Microcontrollers

来源：评论

学校读者我要写书评

暂无评论

Virtual Multiprocessor: An analyzable, high-performance microarchitecture for real-time computing

Virtual Multiprocessor: An analyzable, high-performance micr...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： El-Haj-Mahmoud, Ali Al-Zawawi, Ahmed S. Anantaraman, Aravindh Rotenberg, Eric Department of Electrical and Computer Engineering Center for Embedded Systems Research North Carolina State University Raleigh NC 27695

ISBN: (纸本)159593149X

The design of a real-time architecture is governed by a trade-off between analyzability necessary for real-time formalism and performance demanded by high-end embedded systems. We reconcile this trade-off with a novel Real-time Virtual Multiprocessor (RVMP). RVMP virtualizes a single in-order superscalar processor into multiple interference-free different-sized virtual processors. This provides a flexible spatial dimension, In the time dimension, the number and size of virtual processors can be rapidly reconfigured. A simple real-time scheduling approach concentrates scheduling within a small time interval, producing a simple repeating space/time schedule that orchestrates virtualization. RVMP successfully combines the analyzability (hence real-time formalism) of multiple processors with the flexibility (hence high performance) of simultaneous multithreading (SMT). Worst-case schedulability experiments show that more task-sets are provably schedulable on RVMP than on conventional rigid multiprocessors with equal aggregate resources, and the advantage only intensifies with more demanding task-sets. Run-time experiments show RVMP's statically-controlled coarser-grain space/time configurability is as effective as unsafe SMT. Moreover, RVMP provides a real-time formalism that SMT does not currently provide. Copyright 2005 ACM.

关键词： Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Automating custom-precision function evaluation for embedded processors

Automating custom-precision function evaluation for embedded...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Cheung, Ray C. C. Lee, Dong-U. Mencer, Oskar Department of Computing Imperial College London London United Kingdom EE Department University of California Los Angeles United States

ISBN: (纸本)159593149X

Due to resource and power constraints, embedded processors often cannot afford dedicated floating-point units. For instance, the IBM PowerPC processor embedded in Xilinx Virtex-II Pro FPGAs only supports emulated floating-point arithmetic, which leads to slow operation when floating-point arithmetic is desired. This paper presents a customizable mathematical library using fixed-point arithmetic for elementary function evaluation. We approximate functions via polynomial or rational approximations depending on the user-defined accuracy requirements. The data representation for the inputs and outputs are compatible with IEEE single-precision and double-precision floating-point formats. Results show that our 32-bit polynomial method achieves over 80 times speedup over the single-precision mathematical library from Xilinx, while our 64-bit polynomial method achieves over 30 times speedup. Copyright 2005 ACM.

关键词： Program processors

来源：评论

学校读者我要写书评

暂无评论

Segment protection for embedded systems using run-time checks

Segment protection for embedded systems using run-time check...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Simpson, Matthew Middha, Bhuvan Barua, Rajeev Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 United States

ISBN: (纸本)159593149X

The lack of virtual memory protection is a serious source of unreliability in many embedded systems. Without the segment-level protection it provides, these systems are subject to memory access violations, stemming from programmer error, whose results can be dangerous and catastrophic in safety-critical systems. The traditional method of testing embedded software before its deployment is an insufficient means of detecting and debugging all software errors, and the reliance on this practice is a severe gamble when the reliable performance of the embedded device is critical. Additionally, the use of safe languages and programming semantic restrictions as prevention mechanisms is often infeasible when considering the adoptability and compatibility of these languages since most embedded applications are written in C and C++. This work improves system reliability by providing a completely automatic software technique for guaranteeing segment protection for embedded systems lacking virtual memory. This is done by inserting optimized run-time checks before memory accesses that detect segmentation violations in cases in which there would otherwise be no error, enabling remedial action before system failure or corruption. This feature is invaluable for safety-critical embedded systems. Other advantages of our method include its low overhead, lack of any programming language or semantic restrictions, and ease of implementation. Our compile-time analysis, known as intended segment analysis, is a uniquely structured analysis that allows for the realization of optimizations used to reduce the number of required run-time checks and foster our technique into a truly viable solution for providing segment protection in embedded systems lacking virtual memory. Our experimental results show that these optimizations are effective at reducing the performance overheads associated with providing software segment protection to low, and in many cases, negligible levels. For the eight evalua

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

Equivalence Checking of Arithmetic Expressions using Fast Evaluation

Equivalence Checking of Arithmetic Expressions using Fast Ev...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Ghodrat, Mohammad Ali Givargis, Tony Nicolau, Alex Department of Computer Science Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)159593149X

Arithmetic expressions are the fundamental building blocks of hardware and software systems. An important problem in computational theory is to decide if two arithmetic expressions are equivalent. However, the general problem of equivalence checking, in digital computers, belongs to the NP Hard class of problems. Moreover, existing general techniques for solving this decision problem are applicable to very simple expressions and impractical when applied to more complex expressions found in programs written in high-level languages. In this paper we propose a method for solving;the arithmetic expression equivalence problem using partial evaluation. In particular, our technique is specifically designed to solve the problem of equivalence checking of arithmetic expressions obtained from high-level language descriptions of hardware/software systems, which consists of regular arithmetic operators (+, -, x) and logical operators (and, or, not). In our method, we use interval analysis to substantially prune the domain space of arithmetic expressions and limit the evaluation effort to a sufficiently limited set of subspaces. Our results show that the proposed method is fast enough to be of use in practice. Copyright 2005 ACM.

关键词： Digital arithmetic

来源：评论

学校读者我要写书评

暂无评论

Hardware support for code integrity in embedded processors

Hardware support for code integrity in embedded processors

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Milenković, Milena Milenković, Aleksandar Jovanov, Emil WBI Performance II IBM Austin TX 78758 United States Electrical and Computer Engineering Department University of Alabama in Huntsville Huntsville AL 35899 United States

ISBN: (纸本)159593149X

Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increase, the applications running on these systems also grow in size and complexity, and so does the number of security vulnerabilities. Attacks that impair code integrity by injecting and executing malicious code are one of the major security issues. This problem can be addressed at different levels, from more secure software and operating systems, down to solutions that require hardware support. Most of the existing techniques tackle the problem of security flaws at the software level, but this approach lacks generality and often induces prohibitive overhead in performance and cost, or generates a significant number of false alarms. On the other hand, a further increase in the number of transistors on a single chip enables integrated hardware support for functions that formerly were restricted to the software domain. Hardware-supported defense techniques have the potential to be more general and more efficient than solely software solutions. This paper proposes four new architectural extensions to ensure complete run-time code integrity using instruction block signature verification. The experimental analysis shows that the proposed techniques have low performance and energy overhead. In addition, the proposed mechanism has low hardware complexity, and does not impose either changes to the compiler or changes to the existing instruction set architecture. Copyright 2005 ACM.

关键词： Microprocessor chips

来源：评论

学校读者我要写书评

暂无评论

Anomalous path detection with hardware support

Anomalous path detection with hardware support

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Zhang, Tao Zhuang, Xiaotong Pande, Santosh Lee, Wenke College of Computing Georgia Institute of Technology Atlanta GA 30332-0280 United States

ISBN: (纸本)159593149X

embedded systems are being deployed as a part of critical infrastructures and are vulnerable to malicious attacks due to internet accessibility. Intrusion detection systems have been proposed to protect computer systems from unauthorized penetration. Detecting an attack early on pays off since further damage is avoided and in some cases, resilient recovery could be adopted. This is especially important for embedded systems deployed in critical infrastructures such as Power Grids etc. where a timely intervention could save catastrophes. An intrusion detection system monitors dynamic program behavior against normal program behavior and raises an alert when an anomaly is detected. The normal behavior is learnt by the system through training and profiling. However, all current intrusion detection systems are purely software based and thus suffer from large performance degradation due to constant monitoring operations inserted in application code. Due to the potential performance overheads, software based solutions cannot monitor program behavior at a very fine level of granularity, thus leaving potential security holes as shown in the literature. Another important drawback of such methods is that they are unable to detect intrusions in near real time and the time lag could prove disastrous in real time embedded systems. In this paper, we propose a hardware-based approach to verify program execution paths of target applications dynamically and to detect anomalous executions. With hardware support, our approach offers multiple advantages over software based solutions including minor performance degradation, much stronger detection capability (a larger variety of attacks get detected) and zero-latency reaction upon an anomaly for near real time detection and thus much better security. Copyright 2005 ACM.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

An esterel processor with full preemption support and its worst reaction time analysis

An esterel processor with full preemption support and its wo...

引用

cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Li, Xin Lukoschus, Jan Boldt, Marian Harder, Michael Von Hanxleden, Reinhard Real-Time and Embedded Systems Group Dept. of Computer Science and Applied Mathematics Christian-Albrechts-Universität zu Kiel Olshausenstr. 40 D-24098 Kiel Germany

ISBN: (纸本)159593149X

The concurrent synchronous language Esterel allows programmers to treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-synchronous high-level languages, such as VHDL or C, and then compiled further into hardware or software. Another approach that has been proposed recently is the direct execution of Esterel-like instructions with a customized processor, which promises the flexibility of a software solution with an efficiency close to a hardware implementation. However, the instruction sets and implementations of the processor architectures proposed so far still have some limitations regarding their completeness, efficiency, and adherence to the original Esterel semantics. This paper presents a novel reactive processor architecture, the Kiel Esterel Processor, which addresses these shortcomings. In particular, it provides a complete, semantically accurate implementation of the Esterel preemption primitives, most of which can be expressed directly with a single machine instruction. One advantage of the reactive processors - in addition to their high execution speed compared to traditional software implementations - is that control-flow is preserved while compiling Esterel into machine code, and that the execution platform has a very predictable timing behavior. This paper presents a precise and very efficient Worst Case Reaction Time (WCRT) analysis, which is geared towards the Kiel Esterel Processor, but which could be adapted to other reactive processors as well. Copyright 2005 ACM.

关键词： Program processors

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共39页 << < 27 28 29 30 31 32 33 34 35 36 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：