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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Shrivastava, Aviral Issenin, Ilya Dutt, Nikil Center for Embedded Computer Systems Department of Information and Computer Science University of California Irvine Irvine CA United States

ISBN: (纸本)159593149X

Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally partitioned caches help reduce cache pollution and thereby improve performance. Consequently most previous research has focused on exploiting horizontally partitioned data caches to improve performance, and achieve energy reduction only as a byproduct of performance improvement. In constrast, in this paper we show that optimizing for performance trades-off several opportunities for energy reduction. Our experiments on a HP iPAQ h4300-like memory subsystem demonstrate that optimizing for energy consumption results in up to 127% less memory subsystem energy consumption than the performance optimal solution. Furthermore, we show that energy optimal solution incurs on average only 1.7% performance penalty. Therefore, with energy consumption becoming a first class design constraint, there is a need for compilation techniques aimed at energy reduction. To achieve aforementioned energy savings we propose and explore several low-complexity algorithms aimed at reducing the energy consumption and show that very simple greedy heuristics achieve 97% of the possible memory subsystem energy savings. Copyright 2005 ACM.

关键词： Buffer storage

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Exploiting pipelining to relax register-file port constraints of instruction-set extensions

Exploiting pipelining to relax register-file port constraint...

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Pozzi, Laura Ienne, Paolo School of Computer and Communication Sciences CH-1015 Lausanne Switzerland

ISBN: (纸本)159593149X

Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). While these processors have become available, the state of the art on automatic ISE identification is improving;many algorithms are being proposed for choosing, given the application's source code, the best ISEs under various constraints. Read and write ports between the AFUs and the processor register file are an expensive asset, fixed in the microarchitecture - some processors indeed only allow two read and one write ports - and, on the other hand, a large availability of inputs and outputs to and from the AFUs exposes high speedup. This paper proposes a solution to the limitation of actual register file ports by serialising register file access and therefore addressing multi-cycle read and write. It does so in an innovative way for two reasons: (1) it exploits and brings forward the progress in ISE identification under constraint [1, 16, 4, 19], and (2) it combines register file access serialisation with pipelining in order to obtain the best global solution. This paper proposes an algorithm for scheduling graphs - corresponding to ISEs - under input/output constraint;experiments show that by using the proposed method applications can be sped-up tangibly: speedup for low I/O constraints is 32% better on average, and 65% better at best, than that obtained by state of the art techniques. Copyright 2005 ACM.

关键词： embedded systems

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Single Appearance Schedule with Dynamic Loop Count for Minimum Buffer from Synchronous Dataflow Graphs

Single Appearance Schedule with Dynamic Loop Count for Minim...

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Oh, Hyunok Dutt, Nikil Ha, Soonhoi Center for Embedded Computer Systems University of California Irvine Irvine CA 92697 United States School of EECS Seoul National University Seoul 151-742 Korea Republic of

ISBN: (纸本)159593149X

In this paper, we propose a new single appearance schedule for synchronous dataflow programs to minimize data memory and code memory size at the same time. When the software code is automatically synthesized from the dataflow program graphs, a single appearance schedule promises only one appearance of each node definition in the generated code. While several heuristics have been developed to find a single appearance schedule, they all have to pay significant amount of data memory overhead compared with a buffer optimal schedule. The key idea of the proposed technique is to make a dynamic decision of loop count to make a schedule quasi-static. The proposed quasi-static static schedule produces a single appearance schedule code with minimum data memory requirement. We prove that the proposed scheduling technique is optimal for a chain-structured graph in terms of data memory requirement while maintaining the single appearance schedule. The only penalty for the proposed technique is slight performance overhead of computing loop counts dynamically. Experimental results show that the proposed algorithm reduces 20% total memory with less than 1% performance overhead compared with the previous single appearance schedule algorithms for CD2DAT and non uniform filter bank applications. Copyright 2005 ACM.

关键词： Computer software

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Memory allocation for embedded systems with a compile-time-unknown scratch-pad size

Memory allocation for embedded systems with a compile-time-u...

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Nguyen, Nghi Dominguez, Angel Barua, Rajeev Electrical and Computer Engineering Department University of Maryland College Park MD 20742 United States

ISBN: (纸本)159593149X

This paper presents the first memory allocation scheme for embedded systems having scratch-pad memory whose size is unknown at compile time. A scratch-pad memory (SPM) is a fast compiler-managed SRAM that replaces the hardware-managed cache. Its uses are motivated by its better real-time guarantees as compared to cache and by its significantly lower overheads in energy consumption, area and access time. Existing data allocation schemes for SPM all require that the SPM size be known at compile-time. Unfortunately, the resulting executable is tied to that size of SPM and is not portable to processor implementations having a different SPM size. Such portability would be valuable in situations where programs for an embedded system are not burned into the system at the time of manufacture, but rather are downloaded onto it during deployment, either using a network or portable media such as memory sticks. Such post-deployment code updates are common in distributed networks and in personal hand-held devices. The presence of different SPM sizes in different devices is common because of the evolution in VLSI technology across years. The result is that SPM cannot be used in such situations with downloaded code. To overcome this limitation, this work presents a compiler method whose resulting executable is portable across SPMs of any size. The executable at run-time places frequently used objects in SPM;it considers code, global variables and stack variables for placement in SPM. The allocation is decided by modified loader software before the program is first run and once the SPM size can be discovered. The loader then modifies the program binary based on the decided allocation. To keep the overhead low, much of the pre-processing for the allocation is done at compile-time. Results show that our benchmarks average a 36% speed increase versus an all-DRAM allocation, while the optimal static allocation scheme, which knows the SPM size at compile-time and is thus an un-achievabl

关键词： Storage allocation (computer)

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MTSS: Multi task stack sharing for embedded systems

MTSS: Multi task stack sharing for embedded systems

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Middha, Bhuvan Simpson, Matthew Barua, Rajeev Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 United States

ISBN: (纸本)159593149X

Out-of-memory errors are a serious source of unreliability in most embedded systems [22]. Applications run out of main memory because of the frequent difficulty of estimating the memory requirement before deployment, either because it depends on input data, or because certain language features prevent estimation. The typical lack of disks and virtual memory in embedded systems has a serious consequence when an out-of-memory error occurs. Since there is no swap space for the application to grow into, the system crashes if its memory footprint is exceeded by even one byte. This work improves system reliability for multi-tasking embedded systems by proposing MTSS, a multi-task stack sharing technique, that grows the stack of a particular task into other tasks in the system after it has overflown its bounds. This technique can avoid the out-of-memory error if the extra space recovered is enough to complete execution. Experiments show that MTSS, on an average, is able to recover 47% of the stack space allocated to the overflowing task in the free space of other tasks. Therefore, even if we underestimate the stack size of a particular task by 47% on an average, it will still run to completion by reusing stack in other task's stack. Alternatively, MTSS can also be used for decreasing the physical memory for an embedded system by reducing the initial memory allocated to each of the tasks and recovering the deficit by sharing stack with other tasks. Results show that MTSS used in this way can be used to reduce the memory required in multi-tasking embedded systems by 18% on an average, thus reducing the memory cost of the system. MTSS also offers good real time guarantees, since it uses a paging system that never incurs an episodic increase in run-time. The overheads of MTSS are extremely low: the run-time and code size overheads are 1.8% and 2.6% on an average, making it a feasible method for increasing system reliability and reducing the memory footprint of embedded systems

关键词： embedded systems

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Message from the conference chairs

CASES 2005: International Conference on Compilers, Architect...

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems 2005年 iii页

作者： Conte, Tom Faraboschi, Paolo Mangione-Smith, Bill Najjar, Walid North Carolina State University United States HP Labs. Quantum Intellectual Property Services University of California Riverside United States

No abstract available

ISBN: (纸本)159593149X

No abstract available

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New decompilation techniques for binary-level co-processor generation

New decompilation techniques for binary-level co-processor g...

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IEEE international conference on Computer-Aided Design

作者： G. Stiff F. Vahid Dept. of Comput. Sci. & Eng. California Univ. Riverside CA USA Department of Computer Science and Engineering University of California Riverside USA Center for Embedded Computer Systems UC Irvine

Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded applications while consuming less power than high-performance gigahertz microprocessors. However, existing approaches place restrictions on software languages and compilers. Binary-level co-processor generation has previously been proposed as a complementary approach to reduce impact on tool restrictions, supporting all languages and compilers, at the cost of some decrease in performance. In a binary-level approach, decompilation recovers much of the high-level information, like loops and arrays, needed for effective synthesis, and in many cases yields hardware similar to that of a compiler-based approach. However, previous binary-level approaches have not considered the effects of software compiler optimizations on the resulting hardware. In this paper, we introduce two new decompilation techniques, strength promotion and loop rerolling, and show that they are necessary to synthesize an efficient custom hardware coprocessor from a binary in the presence of software compiler optimizations. In addition, unlike previous approaches, we show the robustness of binary-level co-processor generation by achieving order of magnitude speedups for binaries generated for three different instruction sets, MIPS, ARM, and MicroBlaze, using two different levels of compiler optimizations.

关键词： Coprocessors Hardware Application software Application specific processors Microprocessors Optimizing compilers Software performance Field programmable gate arrays Costs Fabrics

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cases 2003: international conference on compilers, architecture, and synthesis for embedded systems

CASES 2003: International Conference on Compilers, Architect...

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cases 2003: international conference on compilers, architecture, and synthesis for embedded systems

ISBN: (纸本)1581136765

The proceedings contain 33 papers from the cases 2003: international conference on compilers, architecture, and synthesis for embedded systems. The topics discussed include: Moving from embedded systems to embedded computing;vectorizing for a SIMdD DSP architecture;simple offset assignment in presence of subword data;efficient spill code for SDRAM;cluster assignment of global values for clustered VLIW processors;extending STI for demanding hard-real-time systems;clustered calculation of worst-case execution times;task-level timing models for guaranteed performance in multiprocessor networks-on-chip;and system-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures.

关键词： Program processors

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Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems

Memory and architecture exploration with thread shifting for...

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Kiemb, Mary Choi, Kiyoung School of Electrical Engineering and Computer Science Seoul National University San 56-1 Shillim-dong Gwanak-gu Seoul Korea Republic of

ISBN: (纸本)1581138903

In embedded multithreaded architectures, the performance enhancement relative to the base single-threaded architecture is highly dependent on the characteristics of the application and memory configuration, When the application is well parallelized, the multithreading performance may be good even with a small cache since the memory access latency can be hidden. However, if there are complicated dependencies between threads, they cause frequent cache conflicts, so the performance may not be improved. For that reason, not only processor architecture but also memory configuration should be customized to get an optimal solution of an embedded multithreaded system. We suggest a design space exploration algorithm, which considers both memory configuration and multithreaded architecture and a thread shifting technique, which shifts threads in compile time to minimize cache conflict. Copyright 2004 ACM.

关键词： embedded systems

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Cluster miss prediction with prefetch on miss for embedded CPU instruction caches

Cluster miss prediction with prefetch on miss for embedded C...

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Batcher, Ken Walker, Robert Kent State University Cisco Systems 4125 Highlander Parkway Richfield OH 44286 United States Kent State University Computer Science Department Kent OH 44242 United States

ISBN: (纸本)1581138903

Soft CPU cores are often used in embedded systems, yet they limit opportunities to improve cache performance to hardware assistance outside the CPU core. Instruction prefetching is commonly used, but the popular Prefetch On Miss (POM) technique is less helpful when the instruction flow does not follow a sequential execution order, which is often the case in real-time networking applications. Cluster Miss Prediction (CMP) can help in those worst case situations when cache misses do not follow a sequential order, and can be combined with POM to provide an effective technique for real-time networking applications on embedded systems. The benefits of the CMP+POM technique are illustrated in the context of an industrial embedded networking application using different cache configurations. © Copyright 2004 ACM.

关键词： Computer hardware

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