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26th IFIP WG 6.1 international conference on Formal Methods for Networked and Distributed systems, FORTE 2006

26th IFIP WG 6.1 international conference on Formal Methods for Networked and Distributed systems, FORTE 2006

ISBN: (纸本)3540462198

The proceedings contain 35 papers. The special focus in this conference is on Invited talks, Services, Middleware, Composition and synthesis, Logics, Symbolic verification - slicing, Unified modeling languages, Petri nets, Parameterized verification, Real time and Testing . The topics include: Modelling of Complex Software systems: A Reasoned Overview, Semantic-Based Development of Service-Oriented systems, JSCL: A Middleware for Service Coordination, Analysis of Realizability Conditions for Web Service Choreographies, Web Cube, Presence Interaction Management in SIP SOHO architecture, Formal Analysis of Dynamic, Distributed File-System Access Controls, Analysing the MUTE Anonymous File-Sharing System Using the Pi-Calculus, Towards Fine-Grained Automated Verification of Publish-Subscribe architectures, A LOTOS Framework for Middleware Specification, Automatic synthesis of Assumptions for Compositional Model Checking, Refined Interfaces for Compositional Verification, On Distributed Program Specification and synthesis in architectures with Cycles, Generalizing the Submodule Construction Techniques for Extended State Machine Models, Decidable Extensions of Hennessy-Milner Logic, Symbolic Verification of Communicating systems with Probabilistic Message Losses: Liveness and Fairnes, A New Approach for Concurrent Program Slicing, Reducing Software architecture Models Complexity: A Slicing and Abstraction Approach, Branching Time Semantics for UML 2.0 Sequence Diagrams, Formalizing Collaboration Goal Sequences for Service Choreography, Composition of Use cases Using Synchronization and Model Checking, PN Standardisation: A Survey, Optimized Colored Nets Unfolding, Liveness by Invisible Invariants and Extending EFSMs to Specify and Test Timed systems with Action Durations and Timeouts.

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synthesis of adaptive and controllable compliant systems with embedded actuators and sensors

Synthesis of adaptive and controllable compliant systems wit...

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2006 ASME international Design Engineering Technical conferences and Computers and Information In Engineering conference, DETC2006

作者： Trease, Brian P. Kota, Sridhar University of Michigan Department of Mechanical Engineering Ann Arbor MI 48109 United States

ISBN: (纸本)079183784X

This paper presents a framework for the design of a compliant system;that is, the concurrent design of a compliant mechanism with embedded actuators and embedded sensors. We focus on methods that simultaneously synthesize optimal structural topology and placement of actuators and sensors for maximum energy efficiency and adaptive performance, while satisfying various weight and performance constraints. The goal of this research is to lay a scientific foundation and a mathematical framework for distributed actuation and sensing within a compliant active structure. Key features of the methodology include (1) the simultaneous optimization of the location, orientation, and size of actuators concurrent with the compliant transmission topology and (2) the concepts of controllability and observability that arise from the consideration of control, and their implementation in compliant systems design. The methods used include genetic algorithms, graph searches for connectivity, and multiple load cases implemented with linear finite element analysis. Actuators, modeled as both force generators and structural compliant elements, are included as topology variables in the optimization. Results are provided for several studies, including: (1) concurrent actuator placement and topology design for a compliant amplifier and (2) a shape-morphing aircraft wing demonstration with three controlled output nodes. Central to this method is the concept of structural orthogonality, which refers to the unique system response for each actuator it contains. Finally, the results from the controllability problem are used to motivate and describe the analogous extension to observability for sensing Copyright © 2006 by ASME.

关键词： Adaptive systems

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Towards Quality-Driven Approximate Software Generation for Accurate Hardware: Work-in-Progress

Towards Quality-Driven Approximate Software Generation for A...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Jorge Castro-Godínez Muhammad Shafique Jörg Henkel Karlsruhe Institute of Technology (KIT) Germany Instituto Tecnológico de Costa Rica (TEC) Costa Rica Vienna University of Technology (TU Wien) Austria New York University Abu Dhabi UAE

ISBN: (数字)9781728191928

ISBN: (纸本)9781728191935

Many existing processor-based systems, especially using off-the-shelf components, cannot afford hardware modifications to embrace different approximate computing techniques proposed by the research community. In that case, it is mainly at the software level where error resiliency can be exploited efficiently. Although a multitude of approximate techniques can be applied at software level, they have been presented in isolation and little has been done to report their combined usage on different types of applications amenable to approximations. We present here AxSWGen, an automated quality-driven methodology to jointly explore and apply multiple approximate techniques to error-tolerant sections of applications. AxSWGen is implemented using LLVM compiler infrastructure. We present results of automated approximate software generated with AxSWGen and executed on a RISC-V processor (SiFive HiFive1 board), achieving up to 50% energy reduction for a 5% image degradation for an approximate Gaussian filter.

关键词： Degradation embedded systems Diversity reception Software Hardware Energy efficiency Resilience

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Improved use of the carry-save representation for the synthesis of complex arithmetic circuits

Improved use of the carry-save representation for the synthe...

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ICCAD-2004 - IEEE/ACM international conference on Computer-Aided Design, Digest of Technical Papers

作者： Verma, Ajay K. Ienne, Paolo Processor Architecture Laboratory Swiss Fed. Inst. Technol. Lausanne Lausanne Switzerland

The increasing importance of datapath circuits in complex systems-on-chip calls for special arithmetic optimisations. The goal is to achieve automatically the handcrafted results which escape classic logic optimisations. Some work has been done in the recent years to infer the use of the carry-save representation in the synthesis of arithmetic circuits. Yet, many cases of practical interest cannot be handled due to the scattering of logic operations among the arithmetic ones - especially in arithmetic computations which are originally described at the bit level in high-level languages such as C. We therefore introduce an algorithm to restructure dataflow graphs so that they can be synthesized in high-quality arithmetic circuits, close to those that an expert designer would conceive. On typical embedded software benchmarks which could be advantageously implemented with hardware accelerators, our technique always reduces tangibly the critical path by up to 46% and generally achieves the quality of manual implementations. In many cases, our algorithm also manages to reduce the cell area by up to 10-20%. ©2004 IEEE.

关键词： Logic circuits

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Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip

Handling large data sets for high-performance embedded appli...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Paolo Mantovani Emilio G. Cota Christian Pilato Giuseppe Di Guglielmo Luca P. Carloni Department of Computer Science Columbia University New York NY USA

ISBN: (纸本)9781509035892

Local memory is a key factor for the performance of accelerators in SoCs. Despite technology scaling, the gap between on-chip storage and memory footprint of embedded applications keeps widening. We present a solution to preserve the speedup of accelerators when scaling from small to large data sets. Combining specialized DMA and address translation with a software layer in Linux, our design is transparent to user applications and broadly applicable to any class of SoCs hosting high-throughput accelerators. We demonstrate the robustness of our design across many heterogeneous workload scenarios and memory allocation policies with FPGA-based SoC prototypes featuring twelve concurrent accelerators accessing up to 768MB out of 1GB-addressable DRAM.

关键词： Program processors Random access memory System-on-chip Hardware Linux Computer architecture

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Hybrid custom instruction and co-processor synthesis methodology for extensible processors

Hybrid custom instruction and co-processor synthesis methodo...

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19th international conference on VLSI Design held jointly with 5th international conference on embedded systems Design

作者： Sun, Fei Ravi, Srivaths Raghunathan, Anand Jha, Niraj K. Tensilica Inc. Santa Clara CA 95054 NEC Laboratories America Princeton NJ 08540 Department of Electrical Engineering Princeton University Princeton NJ 08544

ISBN: (纸本)0769525024

Classical hardware/software partitioning techniques, recent advances in application-specific instruction set architecture (ISA) design tools, etc., provide avenues to address the individual problems of co-processor generation and custom instruction addition for extensible processors. However, we argue that there is a need for hybrid synthesis techniques by demonstrating that a combination of custom instructions and co-processors is often the better solution in many applications. We propose a systematic methodology that builds on basic observations and trade-offs associated with co-processors and custom instructions: co-processors are good for performing coarse-grained tasks that require minimal intervention or support from the processor, while custom instructions are efficient solutions for fine-grained tasks that are best integrated into a processor's pipeline. We have developed a hierarchical synthesis How that incorporates a muti-objective evolutionary algorithm in order to handle diverse design dimensions such as area, performance. We have implemented the proposed methodology in the context of a commercial extensible processor based platform (Xtensa™ from Tensilica). Our design flow incorporates a commercial behavioral synthesis tool and an automatic custom instruction generation engine. Our experiments with several applications show that simultaneous custom instruction and co-processor synthesis can achieve significantly better area/performance trade-offs than using only one of them. © 2006 IEEE.

关键词： Program processors

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Design and synthesis of a Multiprocessor System-on-Chip architecture for Real-Time Biomedical Signal Processing in Gamma Cameras

Design and Synthesis of a Multiprocessor System-on-Chip Arch...

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IFIP international conference embedded and Ubiquitous Computing

作者： Sun, Kai Wang, Meng Shao, Zili Liu, Hui Wei, Hongxing Wang, Tianmiao Hong Kong Polytech Univ Dept Comp Kowloon Hong Kong Peoples R China Beihang Univ Robot Res Inst Beijing 100083 Peoples R China Xidan Univ Inst Software Engn Xian Peoples R China

MPSoC (Multi-Processor System-on-Chip) architecture is becoming increasingly used because it can provide designers much more opportunities to meet specific performance and power goals. In this paper, we propose an MPSoC architecture for implementing real-time signal processing in gamma camera. Based on a fully analysis of the characteristics of the application, we design several algorithms to optimize the systems in terms of processing speed, power consumption, and area costs etc. Two types of DSP core have been designed for the integral algorithm and the coordinate algorithm, the key parts of signal processing in a gamma camera. An interconnection synthesis algorithm is proposed to reduce the area cost of the Network-on-Chip. We implement our MPSoC architecture on FPGA, and synthesize DSP cores and Network-on-Chip using Synopsys Design Compiler with a UMC 0.18 mu m standard cell library. The results show that our technique can effectively accelerate the processing and satisfy the requirements of real-time signal processing for 256 x 256 image construction.

关键词： Real time Multiprocessor system-on-chip

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CMSM: An efficient and effective code management for software managed multicores

CMSM: An efficient and effective code management for softwar...

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11th ACM/IEEE international conference on Hardware/Software Codesign and System synthesis, CODES+ISSS 2013

作者： Bai, Ke Lu, Jing Shrivastava, Aviral Holton, Bryce Compiler Microarchitecture Laboratory Arizona State University Tempe AZ 85287 United States

ISBN: (纸本)9781479914173

As we scale the number of cores in a multicore processor, scaling the memory hierarchy is a major challenge. Software Managed Multicore (SMM) architectures are one of the promising solutions. In an SMM architecture, there are no caches, and each core has only a local scratchpad memory. If all the code and data of the task mapped to a core do not fit on its local scratchpad memory, then explicit code and data management is required. In this paper, we solve the problem of efficiently managing code on an SMM architecture. We extend the state of the art by: i) correctly calculating the code management overhead, ii) even in the presence of branches in the task, and iii) developing a heuristic CMSM (Code Mapping for Software Managed multicores) that results in efficient code management execution on the local scratchpad memory. Our experimental results collected after executing applications from MiBench suite [1] on the Cell SPEs (Cell is an SMM architecture) [2], demonstrate that correct management cost calculation and branch consideration can improve performance by 12%. Our heuristic CMSM can reduce runtime in more than 80% of the cases, and by up to 20% on our set of benchmarks. © 2013 IEEE.

关键词： embedded systems

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ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2006年第7期14卷 754-762页

作者： Biswas, Partha Banerjee, Sudarshan Dutt, Nikil D. Pozzi, Laura Ienne, Paolo MathWorks Inc Natick MA 01760 USA Univ Calif Irvine Donald Bren Sch Informat & Comp Sci Ctr Embedded Syst Irvine CA 92697 USA Univ Lugano Dept Informat CH-6900 Lugano Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Processor Architecture Lab CH-1015 Lausanne Switzerland

Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Experimental results on a number of MediaBench, EEMBC, and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20 x faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application by effectively exploiting its regular structure.

关键词： application-specific processors hardware-software partitioning instruction set extensions

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Formal Techniques for Networked and Distributed systems - FORTE 2006 - 26th IFIP WG 6.1 international conference, Proceedings

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26th IFIP WG 6.1 international conference

ISBN: (纸本)3540462198

The proceedings contain 33 papers. The topics discussed include: analysis of realizability conditions for web service chreographics;web cube;presence interaction management in SIP SOHO architecture;formal analysis of dynamic, distributed file-system access controls;analyzing the MUTE anonymous file-sharing system using the pi-calculus;towards fine-grained automated verification of publish-subscribe architectures;a LOTOS framework for middleware specification;automatic synthesis of assumptions for compositional model checking;refined interfaces for compositional verification;on distributed program specification and synthesis in architectures with cycles;generalizing the submodule construction techniques for extended state machine models;decidable extensions of Hennessy-Milner logic;a new approach for concurrent program slicing;formalizing collaboration goal sequences for service choreography;and composition of use cases using synchronization and model checking.

关键词： Distributed computer systems

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