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A low power architecture for embedded perception

A low power architecture for embedded perception

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Mathew, Binu Davis, Al Parker, Mike School of Computing University of Utah Salt Late City UT 84112 United States

ISBN: (纸本)1581138903

Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of complex perception applications cannot be met by current embedded processors and often even exceed the performance of high performance microprocessors whose energy consumption far exceeds embedded energy budgets. Though custom ASICs provide a solution to this problem, they incur expensive and lengthy design cycles and are inflexible. This paper introduces a VLIW perception processor which uses a combination of clustered function units, compiler controlled dataflow and compiler controlled clock-gating in conjunction with a scratch-pad memory system to achieve high performance for perceptual algorithms at low energy consumption. The architecture is evaluated using ten benchmark applications taken from complex speech and visual feature recognition, security, and signal processing domains. The energy-delay product of a 0.13μ implementation of this architecture is compared against ASICs and general purpose processors. Using a combination of Spice simulations and real processor power measurements, we show that the cluster running at 1 GHz clock frequency outperforms a 2.4 GHz Pentium 4 by a factor of 1.75 while simultaneously achieving 159 times better energy delay product than a low power Intel XScale embedded processor. © Copyright 2004 ACM.

关键词： embedded systems

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General loop fusion technique for nested loops considering timing and code size

General loop fusion technique for nested loops considering t...

引用

cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Liu, Meilin Zhuge, Qingfeng Shao, Zili Sha, Edwin H.-M. Department of Computer Science University of Texas at Dallas Richardson TX 75083 United States

ISBN: (纸本)1581138903

Loop fusion is commonly used to improve the instruction-level parallelism of loops for high-performance embedded computing systems. Loop fusion, however, is not always directly applicable because the fusion prevention dependencies may exist among loops. Most of the existing techniques still have limitations in fully exploiting the advantages of loop fusion, In this paper, we present a general loop fusion technique for loops or nested loops based on the loop dependency graph model, retiming, and multi-dimensional retiming concepts. We show that any "J+K" model loop can be legally fused using our legalizing fusion technique. Polynomial-time algorithms are developed to solve the loop fusion problem for "J+K" model loops considering both timing and code size of the final code. Our technique produces the final code and calculates the resultant code size directly from the retiming values. The experimental results show that our loop fusion technique always significantly reduces the schedule length. Copyright 2004 ACM.

关键词： embedded systems

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Static program analysis of embedded executable assembly code

Static program analysis of embedded executable assembly code

引用

cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Venkitaraman, Ramakrishnan Gupta, Gopal Laboratory Department of Computer Science University of Texas Dallas United States

ISBN: (纸本)1581138903

We consider the problem of automatically checking if coding standards have been followed in the development of embedded applications. The problem arises from practical considerations because DSP chip manufacturers (in our case Texas Instruments) want various third party software developers to adhere to a certain coding standard to facilitate system integration during application development. Checking for compliance with coding standards, in general, is undecidable. Moreover, only machine code of the system components is available since for proprietary reasons vendors of various components do not want to share their source code. In this paper, we describe an approach based on static analysis of embedded assembly code to check for compliance with such coding standards. This static analysis rests on an abstract interpretation framework. We illustrate our approach by showing how we statically analyze the presence of hard-coded pointer variables in embedded assembly code. Hard coded pointer variables are those that are assigned a fixed memory address by the programmer instead of being assigned a value via proper operations in the source language (e.g., malloc/calloc/realloc and & operator in C). Our analyzer takes object code as input, disassembles it, builds the flow-graph, and statically analyzes the flow-graph for the presence of dereferenced pointers that are hard coded. The analyzer is currently being extended to check for compliance with other rules adopted by TI as part of its coding standards. Copyright 2004 ACM.

关键词： embedded systems

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Providing time- and space- efficient procedure calls for asynchronous Software Thread Integration

Providing time- and space- efficient procedure calls for asy...

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Asokan, Vasanth Dean, Alexander G. Center for Embedded Systems Research Department of Electrical and Computer Engineering North Carolina State University Raleigh NC 27695-7256 United States

ISBN: (纸本)1581138903

Asynchronous Software Thread Integration (ASTI) provides fine-grain concurrency in real-time threads by statically scheduling (integrating) code from primary threads into secondary threads, reducing the context switching needed and allowing recovery of fine-grain idle time. Unlike STI, ASTI allows asynchronous thread progress. Current ASTI techniques do not support procedure calls in the secondary thread because they lead to timing conflicts during static scheduling. ASTI requires knowing the secondary thread's instruction execution schedule to guide placement of real-time instructions from the primary thread. A secondary thread procedure called from multiple sites will have ambiguous timing at compile time. In this paper we remove this constraint using both procedure inlining and cloning. We present a formal approach to choosing a subset of calls to inline and to remove the timing conflicts in the remaining call sites in an efficient fashion. Excessive inlining and cloning both lead to code size explosion, while poor choices in timing conflict elimination slow program execution. The cloned threads show a significant speedup when compared to non-cloned versions yet have low code expansion. The techniques presented here have been implemented in our post-pass compiler Thrint and demonstrated on a benchmark suite of secondary threads representative of low-end embedded systems. Copyright 2004 ACM.

关键词： Computer software

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Hardware assisted control flow obfuscation for embedded processors

Hardware assisted control flow obfuscation for embedded proc...

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Zhuang, Xiaotong Zhang, Tao Lee, Hsien-Hsin S. Pande, Santosh College of Computing School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA 30332-0280 United States

ISBN: (纸本)1581138903

With more applications being deployed on embedded platforms, software protection becomes increasingly important. This problem is crucial on embedded systems like financial transaction terminals, pay-TV access-control decoders, where adversaries may easily gain full physical accesses to the systems and critical algorithms must be protected from being cracked. However, as this paper points out that protecting software with either encryption or obfuscation cannot completely preclude the control flow information from being leaked. Encryption has been widely studied and employed as a traditional approach for software protection, however, the control flow information is not 100% hidden with solely encrypting the code. On the other hand, pure software-based obfuscation has been proved inefficient to protect software due to its lack of theoretical foundation and considerable performance overhead introduced by complicated transformations. Moreover, even though obfuscation can prevent static reverse engineering, attacker can still successfully bypass the obfuscation by monitoring the dynamic program execution. To address all of these shortcomings, this paper presents a hardware assisted obfuscation technique that is capable of obfuscating the control flow information dynamically. Dynamic obfuscation changes memory access sequence on-the-fly and conceals recurrent instruction access sequences from being identified. Our scheme makes it provably difficult for the attacker to extract any useful information. Our results show that a high-level security protection is possible with only minor performance penalty. Finally, we show that our scheme can be implemented on embedded systems with very little hardware overhead. Copyright 2004 ACM.

关键词： Program processors

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Safely exploiting multithreaded processors to tolerate memory latency in real-time systems

Safely exploiting multithreaded processors to tolerate memor...

引用

cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： El-Haj-Mahmoud, Ali Rotenberg, Eric Center for Embedded Systems Research North Carolina State University Raleigh NC 27695-7256 United States

ISBN: (纸本)1581138903

A coarse-grain multithreaded processor can effectively hide long memory latencies by quickly switching to an alternate task when the active task issues a memory request, improving overall throughput. However, dynamic switching cannot be safely exploited to improve throughput in hard-real-time embedded systems. The schedulability of a task-set (guaranteeing all tasks meet deadlines) must be determined a priori using offline schedulability tests. Any computation/memory overlap must be statically accounted for. We develop a novel analytical framework that bounds the overlap between computation of a pipeline-resident-task and on-going memory transfers of other tasks. A simple closed-form schedulability test is derived, that only depends on the aggregate computation (C) and memory (M) components of tasks. Namely, the technique does not require specificity regarding the location of memory transfers within and among tasks and avoids searching all task permutations for a specific feasible schedule. To the best of our knowledge, this is the first work to provide the necessary formalism for safely and tractably exploiting coarse-grain multithreaded processors to tolerate memory latency in hard-real-time systems, exceeding the schedulability limits of classic real-time theory for uniprocessors. Our techniques make it possible to capitalize on higher frequency embedded processors, despite the widening processor-memory speed gap. Experiments with task-sets from C-lab benchmarks reveal improvement in the schedulability of task-sets, measured as the ability to schedule previously infeasible task-sets or reduce utilization for already feasible task-sets. We also demonstrate proof-of-concept by deploying our method in a cycle-level simulator of an ARM11-like embedded microprocessor augmented with multiple register contexts, the same hardware multithreading support available in Ubicom's IP3023 embedded microprocessor. Copyright 2004 ACM.

关键词： Program processors

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Memory overflow protection for embedded systems using run-time checks, reuse and compression

Memory overflow protection for embedded systems using run-ti...

引用

cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Biswas, Surupa Simpson, Matthew Barua, Rajeev ECE Department Univ. of MD College Park United States Computer Engg. Department Clemson University United States

ISBN: (纸本)1581138903

Out-of-memory errors are a serious source of unreliability in most embedded systems. Applications run out of main memory because of the frequent difficulty of estimating the memory requirement before deployment, either because it depends on input data, or because certain language features prevent estimation. The typical lack of disks and virtual memory in embedded systems has two serious consequences when an out-of-memory error occurs. First, there is no swap space for the application to grow into, and the system crashes. Second, since protection from virtual memory is usually absent, the fact that a segment has exceeded its bounds is not even detected and hence no pre-crash remedial action is possible. This work improves system reliability in two ways. First it proposes a low-overhead system of run-time checks by which the out-of-memory errors are detected just before they will happen, by using carefully optimized compiler-inserted run-time check code. Such error detection enables the designer to incorporate system-specific remedial action, such as transfer to manual control, shutting down of non-critical tasks, or other actions. Second, this work proposes five related techniques that can grow the stack or heap segment after it is out of memory, into previously un-utilized space such as dead variables and space freed by compressed live variables. These techniques can avoid the out-of-memory error if the extra space recovered is enough to complete execution. Results from our benchmarks show that the overheads from the system of run-time checks for detecting memory overflow are extremely low: the run-time and code-size overheads are 1.1% and 0.09% on average. When the reuse functionality is included, the run-time and code-size overheads increase to only 3.2% and 2.33%, but the method is able to grow the stack or heap beyond its over-flow by an amount that ranges from 0.7% to 93.5% of the combined stack and heap size. Copyright 2004 ACM.

关键词： embedded systems

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Improved use of the carry-save representation for the synthesis of complex arithmetic circuits

Improved use of the carry-save representation for the synthe...

引用

ICCAD-2004 - IEEE/ACM international conference on Computer-Aided Design, Digest of Technical Papers

作者： Verma, Ajay K. Ienne, Paolo Processor Architecture Laboratory Swiss Fed. Inst. Technol. Lausanne Lausanne Switzerland

The increasing importance of datapath circuits in complex systems-on-chip calls for special arithmetic optimisations. The goal is to achieve automatically the handcrafted results which escape classic logic optimisations. Some work has been done in the recent years to infer the use of the carry-save representation in the synthesis of arithmetic circuits. Yet, many cases of practical interest cannot be handled due to the scattering of logic operations among the arithmetic ones - especially in arithmetic computations which are originally described at the bit level in high-level languages such as C. We therefore introduce an algorithm to restructure dataflow graphs so that they can be synthesized in high-quality arithmetic circuits, close to those that an expert designer would conceive. On typical embedded software benchmarks which could be advantageously implemented with hardware accelerators, our technique always reduces tangibly the critical path by up to 46% and generally achieves the quality of manual implementations. In many cases, our algorithm also manages to reduce the cell area by up to 10-20%. ©2004 IEEE.

关键词： Logic circuits

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Design and programming of embedded multiprocessors: an interface-centric approach 04

Design and programming of embedded multiprocessors: an inter...

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international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： P. van der Wolf E. de Kock T. Henriksson W. Kruijtzer G. Essink Philips Research Laboratories Eindhoven Netherlands

ISBN: (纸本)9781581139372

We present design technology for the structured design and programming of embedded multi-processor systems. It comprises a task-level interface that can be used both for developing parallel application models and as a platform interface for implementing applications on multi-processor architectures. Associated mapping technology supports refinement of application models towards implementation. By linking application development and implementation aspects, the technology integrates the specification and design phases in the MPSoC design process. Two design cases demonstrate the efficient implementation of the platform interface on different architectures. Industry-wide standardization of a task-level interface can facilitate reuse of function-specific hardware/software modules across companies.

关键词： Hardware Application software Computer architecture Refining Process design Standardization Permission Joining processes Computer industry Parallel architectures

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Proceedings of the 2002 international conference on compilers, architecture, and synthesis for embedded systems, cases '02

Proceedings of the 2002 International Conference on Compiler...

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2002 international conference on compilers, architecture, and synthesis for embedded systems, cases '02

ISBN: (纸本)1581135750

The proceedings contain 38 papers. The topics discussed include: a near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor;components for embedded software: the PECOS approach;efficient architecture/compiler co-exploration for ASIPs;cycle-time aware architecture synthesis of custom hardware accelerators;an adaptive chip-multiprocessor architecture for future mobile terminals;towards automatic synthesis of a class of application-specific sensor networks;bit section instruction set extension of ARM for embedded applications;code coverage and input variability: effects on architecture and compiler research;an integrated approach to reducing power dissipation in memory hierarchies;embedded cache architecture with programmable write buffer support for power and performance flexibility;increasing power efficiency of multi-core network processors through data filtering;cost effective memory disambiguation for multimedia codes;and leakage-proof program partitioning.

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