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international conference on VLSI Design

作者： D.C. Zaretsky G. Mittal R.P. Dick P. Banerjee Department of Electrical Electrical & Computer Science Northwestern University Evanston IL USA College of Engineering University of Illinois Chicago Chicago IL USA

High-level synthesis compilers often produce reoccurring patterns in intermediate CDFGs during translation. By identifying large reoccurring patterns, one may reduce area and communication overhead by efficiently reusing hardware for multiple operations. This paper presents an algorithm for dynamically generating templates of reoccurring patterns for resource sharing in CDFGs. Results show 40-80% resource reduction using small, incremental template growth, and variations within a 5% margin among varying look-ahead depths.

关键词： Resource management Flow graphs Hardware Field programmable gate arrays Libraries Cost function High level synthesis Routing Data flow computing Computer science

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Efficient Tracing Methodology Using Automata Processor

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 80-80页

作者： Seo, Minjun Kurdahi, Fadi Univ Calif Irvine Ctr Embedded Cyber Phys Syst Irvine CA 92617 USA

Tracing or trace interface has been used in various ways to find system defects or bugs. As embedded systems are increasingly used in safety-critical applications, tracing can provide useful information during system execution at runtime. Non-intrusive tracing that does not affect system performance has become especially important, but unfortunately, the biggest obstacle to this approach was the vast amount of real-time trace data, making it challenging to address complex requirements with relatively limited hardware implementations. Automata processors can be programmed with a memory-like structure of automata and have a structure specific to streaming data, large capacity, and parallel processing functions. This paper promotes the idea of high-level system-on-chip monitoring using automata processors. We used a safety-critical pacemaker application in the experiments, described timed automata (TA)-based requirements, and tested intentionally injected 4,000 random failures. The TA model converted for Automata Processor to monitor system, correctness, and safety properties achieved 100% failure detection rate in the experiment, and the detected failure is reported as fast enough to allow enough extent for failure recovery.

关键词： Tracing tracing methodology runtime verification

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An Area-Efficient Reed-Solomon Decoder for HDTV Channel Demodulation

An Area-Efficient Reed-Solomon Decoder for HDTV Channel Demo...

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IEEE/ASME international conference on Mechtronic and embedded systems and Applications, MESA

作者： Yan Fei Guo Zhan Cai Li Qin Wang Information Engineering School University of Science and Technology Beijing China

In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for Reed-Solomon (RS) decoding. The proposed architecture is exploited based on the features of vector operations of the decoding algorithm. By pipelining and folding, the proposed architecture can improve the reuse rate of the main computation unit, reduce the hardware complexity and delete the redundant circuits. Synthesized by the Cadence Ambittrade tool using the TSMC 0.25 mum standard cell library, the implemented RS decoder consists of about 27,000 gates, which is about 39% smaller than the same kind of conventional ones. It has been integrated in a channel demodulation chip for high-definition television (HDTV) and has been tested successfully in practice

关键词： Reed-Solomon codes Decoding HDTV Demodulation Computer architecture Very large scale integration Pipeline processing Hardware Integrated circuit synthesis Libraries

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TLM/network design space exploration for networked embedded systems

TLM/network design space exploration for networked embedded ...

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international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： D. Quaglia F. Fummi N. Bombieri Dipartimento di Informatica Universitá di Verona Verona Italy

This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design dimension is added to the traditional TLM refinement process to represent network configuration alternatives. Each network configuration can be used both to drive architecture refinement and exploration and to validate the system after each refinement step. A general criterion to map functionalities to System and Network models is presented. As a case study, the proposed methodology is applied to the design of a Voice-over-IP client.

关键词： Space exploration embedded system Internet telephony Computational modeling Computer simulation Permission Computer networks Computer architecture Mobile handsets Wireless sensor networks

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Proceedings of the 2006 international conference on Computer-Aided Design

Proceedings of the 2006 International Conference on Computer...

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IEEE international conference on Computer-Aided Design

The following topics are dealt with: parasitic simulation; parasitic modeling; post-placement optimization; variation modeling; multicore systems; embedded systems; UML; systemC; industrial ESL design; delay test generation; power grid analysis and design; floorplanning; digital testing; RF testing; reliability; statistical timing analysis; system level design; analog simulation; analog verification; high level synthesis; CAD; analog design automation; system level interconnection; placement optimization; power analysis; mixed signal design; global routing; signal integrity; fault tolerant energy minimization; real-time systems; clock synthesis; buffer synthesis; thermal analysis; nanoelectronics; technology driven layout; nanoscale architecture; dynamic power management; model checking; biotechnology; MEMS; NEMS; accelerating verification; model order reduction; parametric analysis; and molecular scale systems

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Deriving Equations from Sensor Data Using Dimensional Function synthesis

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 84-84页

作者： Wang, Youchao Willis, Sam Tsoutsouras, Vasileios Stanley-Marbell, Phillip Univ Cambridge 9 JJ Thomson Ave Cambridge CB3 0FA England

We present a new method for deriving functions that model the relationship between multiple signals in a physical system. The method, which we call dimensional function synthesis, applies to data streams where the dimensions of the signals are known. The method comprises two phases: a compile-time synthesis phase and a subsequent calibration using sensor data. We implement dimensional function synthesis and use the implementation to demonstrate efficiently summarizing multi-modal sensor data for two physical systems using 90 laboratory experiments and 10 000 synthetic idealized measurements. We evaluate the performance of the compile-time phase of dimensional function synthesis as well as the calibration phase overhead, inference latency, and accuracy of the models our method generates. The results show that our technique can generate models in less than 300 ms on average across all the physical systems we evaluated. When calibrated with sensor data, our models outperform traditional regression and neural network models in inference accuracy in all the cases we evaluated. In addition, our models perform better in training latency (over 8660x improvement) and required arithmetic operations in inference (over 34x improvement). These significant gains are largely the result of exploiting information on the physics of signals that has hitherto been ignored.

关键词： Machine learning dimensional analysis sensor data fusion

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CaffePresso: An optimized library for Deep Learning on embedded accelerator-based platforms

CaffePresso: An optimized library for Deep Learning on embed...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Gopalakrishna Hegde Siddhartha Nachiappan Ramasamy Nachiket Kapre School of Computer Science and Engineering Nanyang Technological University Singapore

ISBN: (纸本)9781509035892

Off-the-shelf accelerator-based embedded platforms offer a competitive energy-efficient solution for lightweight deep learning computations over CPU-based systems. Low-complexity classifiers used in power-constrained and performance-limited scenarios are characterized by operations on small image maps with 2- 3 deep layers and few class labels. For these use cases, we consider a range of embedded systems with 5-20W power budgets such as the Xilinx ZC706 board (with MXP soft vector processor), NVIDIA Jetson TX1 (GPU), TI Keystone II (DSP) as well as the Adapteva Parallella board (custom multi-core with NoC). Deep Learning computations push the capabilities of these platforms to the limit through compute-intensive evaluations of multiple 2D convolution filters per layer, and high communication requirements arising from the movement of intermediate maps across layers. We present CaffePresso, a Caffe-compatible framework for generating optimized mappings of user-supplied ConvNet specifications to target various accelerators such as FPGAs, DSPs, GPUs, RISC-multicores. We use an automated code generation and auto-tuning approach based on knowledge of the ConvNet requirements, as well as platform-specific constraints such as on-chip memory capacity, bandwidth and ALU potential. While one may expect the Jetson TX1 + cuDNN to deliver high performance for ConvNet configurations, (1) we observe a flipped result with slower GPU processing compared to most other systems for smaller embedded-friendly datasets such as MNIST and CIFAR10, and (2) faster and more energy efficient implementation on the older 28nm TI Keystone II DSP over the newer 20nm NVIDIA TX1 SoC in all cases.

关键词： Digital signal processing Machine learning Graphics processing units Field programmable gate arrays Neon Two dimensional displays System-on-chip

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End-to-End Timing Analysis of Sporadic Cause-Effect Chains in Distributed systems

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 58-58页

作者： Duerr, Marco Von Der Brueggen, Georg Chen, Kuan-Hsun Chen, Jian-Jia TU Dortmund Univ Dortmund Germany

A cause-effect chain is used to define the logical order of data dependent tasks, which is independent from the execution order of the jobs of the (periodic/sporadic) tasks. Analyzing the worst-case End-to-End timing behavior, associated to a cause-effect chain, is an important problem in embedded control systems. For example, the detailed timing properties of modern automotive systems are specified in the AUTOSAR Timing Extensions. In this paper, we present a formal End-to-End timing analysis for distributed systems. We consider the two most important End-to-End timing semantics, i.e., the button-to-action delay (termed as the maximum reaction time) and the worst-case data freshness (termed as the maximum data age). Our contribution is significant due to the consideration of the sporadic behavior of job activations, whilst the results in the literature have been mostly limited to periodic activations. The proof strategy shows the (previously unexplored) connection between the reaction time (data age, respectively) and immediate forward ( backward, respectively) job chains. Our analytical results dominate the state of the art for sporadic task activations in distributed systems and the evaluations show a clear improvement for synthesized task systems as well as for a real world automotive benchmark setting.

关键词： End-to-End timing analysis distributed systems sporadic cause-effect chains embedded control systems

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ILP-based modulo scheduling for high-level synthesis

ILP-based modulo scheduling for high-level synthesis

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Julian Oppermann Andreas Koch Melanie Reuter-Oppermann Oliver Sinnen Embedded Systems and Applications Group Technische Universität Darmstadt Germany Discrete Optimization and Logistics Group Karlsruhe Institute of Technology Germany Parallel and Reconfigurable Computing Group University of Auckland New Zealand

ISBN: (纸本)9781509035892

In high-level synthesis, loop pipelining is a technique to improve the throughput and utilisation of hardware datapaths by starting new loop iterations after a fixed amount of time, called the initiation interval (II), allowing to overlap subsequent iterations. The problem is to find the smallest II and corresponding operation schedule that fulfils all data dependencies and resource constraints, both of which are usually found by modulo scheduling. We propose Moovac1, a novel integer linear program (ILP) formulation of the modulo scheduling problem based on overlap variables to model exact resource constraints. Given enough time, Moovac will find a mimimum-II solution. This is in contrast to Canis' state-of-the-art Modulo SDC approach, which requires heuristic simplifications of the resource constraints. Moovac can thus be used as a reference to evaluate heuristics, or in a time-limited mode as a heuristic itself to provide a best-so-far solution. We schedule kernels from the CHStone and MachSuite benchmarks for loop pipelining with Moovac, Modulo SDC and a prior exact formulation by Eichenberger. Moovac has competitive performance in its time-limited mode, and delivers better results faster than the Modulo SDC scheduler for some loops. Often its structure leads to quicker solution times than Eichenberger's formulation. Using the Moovac-computed optimal solutions as a reference, we can confirm that the Modulo SDC heuristic is indeed capable of finding optimal or near-optimal solutions for the majority of smallto medium-sized loops. However, for larger loops the two algorithms begin to diverge, with Moovac often being significantly faster to prove the infeasibility of a candidate II. This can be exploited by running both schedulers synergistically, leading to a quicker convergence to the final II.

关键词： Schedules Pipeline processing Hardware Clocks Digital signal processing VLIW

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D-PUF: An intrinsically reconfigurable DRAM PUF for device authentication in embedded systems

D-PUF: An intrinsically reconfigurable DRAM PUF for device a...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Soubhagya Sutar Arnab Raha Vijay Raghunathan School of Electrical and Computer Engineering Purdue University

ISBN: (纸本)9781509035892

Physically Unclonable Functions (PUFs) have proved to be an effective and low-cost measure against counterfeiting by providing device authentication and secure key storage services. Memory based PUF implementations are an attractive option due to the ubiquitous nature of memory in electronic devices and the requirement of minimal (or no) additional circuitry. DRAM based PUFs are particularly advantageous due to their large address space and multiple controllable parameters during response generation. However, prior works on DRAM PUFs use a static response generation mechanism making them vulnerable to security attacks. Further, they result in very slow device authentication, are not applicable to off-the-shelf DRAM modules, or require DRAM power cycling prior to authentication. In this paper, we propose D-PUF, an intrinsically reconfigurable DRAM PUF based on refresh pausing. A key feature of the proposed DRAM PUF is that it can be reconfigured by varying the refresh-pause interval, which changes it's challenge-response behavior, making it robust against various attacks. We use the PUF to design a secure, low-overhead methodology for performing device authentication. The design is implemented and validated using an Altera Stratix IV GX FPGA based Terasic TR4-230 development board and several off-the-shelf 1GB DDR3 DRAM modules. Our experimental results demonstrate a 4.3×-6.4× reduction in authentication time, compared to previous work. Using controlled temperature and accelerated aging tests, we also demonstrate the robustness of our authentication mechanism to temperature variations and aging effects.

关键词： Random access memory Authentication embedded systems Robustness Temperature control Capacitors

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