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IEEE international conference on Computer-Aided Design

作者： G. Stiff F. Vahid Dept. of Comput. Sci. & Eng. California Univ. Riverside CA USA Department of Computer Science and Engineering University of California Riverside USA Center for Embedded Computer Systems UC Irvine

Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded applications while consuming less power than high-performance gigahertz microprocessors. However, existing approaches place restrictions on software languages and compilers. Binary-level co-processor generation has previously been proposed as a complementary approach to reduce impact on tool restrictions, supporting all languages and compilers, at the cost of some decrease in performance. In a binary-level approach, decompilation recovers much of the high-level information, like loops and arrays, needed for effective synthesis, and in many cases yields hardware similar to that of a compiler-based approach. However, previous binary-level approaches have not considered the effects of software compiler optimizations on the resulting hardware. In this paper, we introduce two new decompilation techniques, strength promotion and loop rerolling, and show that they are necessary to synthesize an efficient custom hardware coprocessor from a binary in the presence of software compiler optimizations. In addition, unlike previous approaches, we show the robustness of binary-level co-processor generation by achieving order of magnitude speedups for binaries generated for three different instruction sets, MIPS, ARM, and MicroBlaze, using two different levels of compiler optimizations.

关键词： Coprocessors Hardware Application software Application specific processors Microprocessors Optimizing compilers Software performance Field programmable gate arrays Costs Fabrics

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D-PUF: An intrinsically reconfigurable DRAM PUF for device authentication in embedded systems

D-PUF: An intrinsically reconfigurable DRAM PUF for device a...

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Soubhagya Sutar Arnab Raha Vijay Raghunathan School of Electrical and Computer Engineering Purdue University

ISBN: (纸本)9781509035892

Physically Unclonable Functions (PUFs) have proved to be an effective and low-cost measure against counterfeiting by providing device authentication and secure key storage services. Memory based PUF implementations are an attractive option due to the ubiquitous nature of memory in electronic devices and the requirement of minimal (or no) additional circuitry. DRAM based PUFs are particularly advantageous due to their large address space and multiple controllable parameters during response generation. However, prior works on DRAM PUFs use a static response generation mechanism making them vulnerable to security attacks. Further, they result in very slow device authentication, are not applicable to off-the-shelf DRAM modules, or require DRAM power cycling prior to authentication. In this paper, we propose D-PUF, an intrinsically reconfigurable DRAM PUF based on refresh pausing. A key feature of the proposed DRAM PUF is that it can be reconfigured by varying the refresh-pause interval, which changes it's challenge-response behavior, making it robust against various attacks. We use the PUF to design a secure, low-overhead methodology for performing device authentication. The design is implemented and validated using an Altera Stratix IV GX FPGA based Terasic TR4-230 development board and several off-the-shelf 1GB DDR3 DRAM modules. Our experimental results demonstrate a 4.3×-6.4× reduction in authentication time, compared to previous work. Using controlled temperature and accelerated aging tests, we also demonstrate the robustness of our authentication mechanism to temperature variations and aging effects.

关键词： Random access memory Authentication embedded systems Robustness Temperature control Capacitors

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Speculative disassembly of binary code

Speculative disassembly of binary code

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Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： M. Ammar Ben Khadra Dominik Stoffel Wolfgang Kunz University of Kaiserslautern Kaiserslautern Germany University of Kaiserslautern Germany

ISBN: (纸本)9781509035892

embedded software is rapidly increasing in complexity. To cope with this, developers rely on third-party IPs to accelerate product delivery. However, IP source code might not be available which limits verifiability. This creates a particular challenge especially in safety-critical applications, e.g., automotive. Static Binary Analysis (SBA) is a promising technique to address such a challenge by providing engineers with the ability to reason about the actual instructions executed for all possible inputs. Disassembly is the fundamental first step for any SBA where assembly instructions are recovered from binary code. Correct disassembly, however, is challenging since data is mixed with code in binaries. Moreover, variable-size ISA, e.g., Thumb and TriCore, allow a single byte sequence to have multiple valid interpretations. We introduce Spedi, an open source SPEculative DIsassembler for Thumb ISA. Spedi is based on a principled approach to disassembly where all possible basic blocks are speculatively recovered. Then, basic blocks are refined using conflict analyses to identify assembly instructions. Experiments using a wide range of benchmarks demonstrate that Spedi is both fast and effective. It outperforms IDA Pro, the de-facto industry standard disassembler, in terms of disassembly correctness. Spedi can also recover the majority of the call graph and switch table targets. It is resilient to obfuscation and doesn't use any symbol information which makes it a suitable front-end for a wide variety of SBA applications including security analysis.

关键词： Thumb Switches Binary codes embedded software Complexity theory Security

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SWARAM: Portable Energy and Cost Efficient embedded System for Genomic Processing

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 61-61页

作者： Mohanty, Ram Prasad Gamaarachchi, Hasindu Lambert, Andrew Parameswaran, Sri Univ New South Wales Canberra ACT 2612 Australia Univ New South Wales Sydney NSW 2052 Australia

Treatment of patients using high-quality precision medicine requires a thorough understanding of the genetic composition of a patient. Ideally, the identification of unique variations in an individual's genome is needed for specifying the necessary treatment. Variant calling workflow is a pipeline of tools, integrating state of the art software systems aimed at alignment, sorting and variant calling for the whole genome sequencing (WGS) data. This pipeline is utilized for identifying unique variations in an individual's genome (compared to a reference genome). Currently, such a workflow is implemented on high-performance computers (with additional GPUs or FPGAs) or in cloud computers. Such systems are large, have a high cost, and rely on the internet for genome data transfer which makes the system unusable in remote locations unequipped with internet connectivity. It further raises privacy concerns due to processing being carried out in a different facility. To overcome such limitations, in this paper, for the first time, we present a cost-efficient, offline, scalable, portable, and energy-efficient computing system named SWARAM for variant calling workflow processing. The system uses novel architecture and algorithms to match against partial reference genomes to exploit smaller memory sizes which are typically available in tiny processing systems. Extensive tests on a standard benchmark data-set (NA12878 Illumina platinum genome) confirm that the time consumed for the data transfer and completing variant calling workflow on SWARAM was competitive to that of a 32-core Intel Xeon server with similar accuracy, but costs less than a fifth, and consumes less than 40% of the energy of the server system. The original scripts and code we developed for executing the variant calling workflow on SWARAM are available in the associated Github repository https://***/Rammohanty/swaram.

关键词： Genome alignment variant calling genetic analysis embedded system ARM DNA analysis energy efficient system portable genome analysis

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Hardware-Software Codesign of Multimedia embedded systems: the PeaCE

Hardware-Software Codesign of Multimedia Embedded Systems: t...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Soonhoi Ha Choonseung Lee Youngmin Yi Seongnam Kwon Young-Pyo Joo The CAP Laboratory Seoul National University South Korea

Hardware/software codesign involves various design problems including system specification, design space exploration, hardware/software co-verification, and system synthesis. A codesign environment is a software tool that facilitates capabilities to solve these design problems. This paper presents the peace codesign environment mainly targeting for multimedia applications with real-time constraints. Peace specifies the system behavior with a heterogeneous composition of three models of computation. The Peace environment provides seamless co-design flow from functional simulation to system synthesis, utilizing the features of the formal models maximally during the whole design process. Preliminary experiments with real examples prove the viability of the proposed technique

关键词： Multimedia systems embedded system Hardware Computer architecture Space exploration Algorithm design and analysis Software tools Computational modeling Software design Software performance

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High-Level synthesis of Approximate Designs under Real-Time Constraints

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 59-59页

作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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Numerical Representation of Directed Acyclic Graphs for Efficient Dataflow embedded Resource Allocation

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 101-101页

作者： Arrestier, Florian Desnos, Karol Juarez, Eduardo Menard, Daniel Univ Rennes INSA Rennes CNRS IETRUMR 6164 Rennes France Univ Politecn Madrid CITSEM Madrid Spain

Stream processing applications running on Heterogeneous Multi-Processor systems on Chips (HMPSoCs) require efficient resource allocation and management, both at compile-time and at runtime. To cope with modern adaptive applications whose behavior can not be exhaustively predicted at compile-time, runtime managers must be able to take resource allocation decisions on-the-fly, with a minimum overhead on application performance. Resource allocation algorithms often rely on an internal modeling of an application. Directed Acyclic Graph (DAGs) are the most commonly used models for capturing control and data dependencies between tasks. DAGs are notably often used as an intermediate representation for deploying applications modeled with a dataflow Model of Computation (MoC) on HMPSoCs. Building such intermediate representation at runtime for massively parallel applications is costly both in terms of computation and memory overhead. In this paper, an intermediate representation of DAGs for resource allocation is presented. This new representation shows improved performance for run-time analysis of dataflow graphs with less overhead in both computation time and memory footprint. The performances of the proposed representation are evaluated on a set of computer vision and machine learning applications.

关键词： Dataflow numerical modeling resource allocation

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Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 51-51页

作者： Restuccia, Francesco Pagani, Marco Biondi, Alessandro Marinoni, Mauro Buttazzo, Giorgio Scuola Super Sant Anna Via Moruzzi 1 I-56127 Pisa Italy Scuola Super Sant Anna Area CNR Pisa Italy Univ Lille CRIStAL CNRS Cent LilleUMR 9189 Lille France

AMBA AXI is a popular bus protocol that is widely adopted as the medium to exchange data in field-programmable gate array system-on-chips (FPGA SoCs). The AXI protocol does not specify how conflicting transactions are arbitrated and hence the design of bus arbiters is left to the vendors that adopt AXI. Typically, a round-robin arbitration is implemented to ensure a fair access to the bus by the master nodes, as for the popular SoCs by Xilinx. This paper addresses a critical issue that can arise when adopting the AXI protocol under round-robin arbitration;specifically, in the presence of bus transactions with heterogeneous burst sizes. First, it is shown that a completely unfair bandwidth distribution can be achieved under some configurations, making possible to arbitrarily decrease the bus bandwidth of a target master node. This issue poses serious performance, safety, and security concerns. Second, a low-latency (one clock cycle) module named AXI burst equalizer (ABE) is proposed to restore fairness. Our investigations and proposals are supported by implementations and tests upon three modern SoCs. Experimental results are reported to confirm the existence of the issue and assess the effectiveness of the ABE with bus traffic generators and hardware accelerators from the Xilinx's IP library.

关键词： FPGA AXI BUS arbitration embedded systems

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Generic architecture Description for Retargetable Compilation and synthesis of Application-Specific Pipelined IPs

Generic Architecture Description for Retargetable Compilatio...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Bita Gorjiara Mehrdad Reshadi Daniel Gajski Center for Embedded Computer Systems University of California Irvine USA

Constraints of embedded systems and the shrinking time-to-market have elevated the importance of designer productivity and design predictability more than ever. To improve productivity, in ASIP approaches the system is designed with software and executed on a customized processor. In ASIP design flow, the processor is described in an architecture Description Language (ADL) and the toolset is generated from that ADL automatically. However, in these approaches design predictability is low because the designer has little or no control over the quality of the final implementation. In this paper, we present a new design approach where the target processor or Intellectual Property (IP) does not have any predefined instruction-set and its datapath component netlist is described in a Generic Netlist Representation (GNR). The GNR is used by the toolset to generate the controller of the IP and the RTL of the design. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. We have also developed a web-based interface for our toolset, so that users can upload and evaluate new IPs described in GNR.

关键词： Productivity Application specific processors Computer architecture embedded system Time to market Software design Process design architecture description languages Automatic control Intellectual property

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An approach to architectural enhancement for embedded speech applications

An approach to architectural enhancement for embedded speech...

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international conference on VLSI Design

作者： S. Dey S. Biswas A. Mukhopadhyay A. Basu Department of Computer Science and Engineering Indian Institute of Technology Kharagpur Kharagpur West Bengal India

Advances in human computer interaction (HCI) technology has resulted in widespread development of natural language and speech applications. These applications are known to be computationally different from other end-user applications. In this paper, the architectural features of text to speech (TTS) and automatic speech recognition (ASR) applications have been evaluated and cost effective optimal architectural solutions have been suggested. The results have shown that low cost solutions such as ISA extension and feature addition to an existing embedded architecture can lead to appreciable improvement in performance for these applications. This work also presents a design space exploration to suggest an optimized VLIW architecture for TTS and ASR applications.

关键词： Speech enhancement Application software Speech synthesis Automatic speech recognition Human computer interaction Natural languages Cost function Instruction sets Space exploration Design optimization

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