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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Bita Gorjiara Mehrdad Reshadi Daniel Gajski Center for Embedded Computer Systems University of California Irvine USA

Constraints of embedded systems and the shrinking time-to-market have elevated the importance of designer productivity and design predictability more than ever. To improve productivity, in ASIP approaches the system is designed with software and executed on a customized processor. In ASIP design flow, the processor is described in an architecture Description Language (ADL) and the toolset is generated from that ADL automatically. However, in these approaches design predictability is low because the designer has little or no control over the quality of the final implementation. In this paper, we present a new design approach where the target processor or Intellectual Property (IP) does not have any predefined instruction-set and its datapath component netlist is described in a Generic Netlist Representation (GNR). The GNR is used by the toolset to generate the controller of the IP and the RTL of the design. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. We have also developed a web-based interface for our toolset, so that users can upload and evaluate new IPs described in GNR.

关键词： Productivity Application specific processors Computer architecture embedded system Time to market Software design Process design architecture description languages Automatic control Intellectual property

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Numerical Representation of Directed Acyclic Graphs for Efficient Dataflow embedded Resource Allocation

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 101-101页

作者： Arrestier, Florian Desnos, Karol Juarez, Eduardo Menard, Daniel Univ Rennes INSA Rennes CNRS IETRUMR 6164 Rennes France Univ Politecn Madrid CITSEM Madrid Spain

Stream processing applications running on Heterogeneous Multi-Processor systems on Chips (HMPSoCs) require efficient resource allocation and management, both at compile-time and at runtime. To cope with modern adaptive applications whose behavior can not be exhaustively predicted at compile-time, runtime managers must be able to take resource allocation decisions on-the-fly, with a minimum overhead on application performance. Resource allocation algorithms often rely on an internal modeling of an application. Directed Acyclic Graph (DAGs) are the most commonly used models for capturing control and data dependencies between tasks. DAGs are notably often used as an intermediate representation for deploying applications modeled with a dataflow Model of Computation (MoC) on HMPSoCs. Building such intermediate representation at runtime for massively parallel applications is costly both in terms of computation and memory overhead. In this paper, an intermediate representation of DAGs for resource allocation is presented. This new representation shows improved performance for run-time analysis of dataflow graphs with less overhead in both computation time and memory footprint. The performances of the proposed representation are evaluated on a set of computer vision and machine learning applications.

关键词： Dataflow numerical modeling resource allocation

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A New High Resolution Frequency and Phase synthesis Method based on `Flying-Adder' architecture

A New High Resolution Frequency and Phase Synthesis Method b...

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IEEE international conference on Semiconductor Electronics (ICSE)

作者： Hossein Gharaee Elham Tathesari Tarbiat Modares University Shariati University Iran

High speed electronic systems demand frequency synthesizer of high resolution, wide bandwidth and fast switching speed. The "Flying-Adder" architecture is a frequency and phase synthesis technique that is based on a VCO of multiple delay stages. This Flying-Adder is implemented in Quartus software which its result shows that the highest frequency is about 83 MHz, when VCO oscillates at 5.2 MHz. In some cases, this architecture has a barrier of inherent jitter on the output frequency. In this brief, a new method is proposed for eliminating such jitter problem. This method is caused to achieve exact phase and frequency. This design is implemented in Quartus software with EP1K30QC208-1 device from ACEX IK series. When VCO is running at 0.651-10 MHz high resolution output frequency is achieved.

关键词： Frequency synthesizers Voltage-controlled oscillators Jitter Computer architecture Delay Clocks Signal resolution Signal synthesis Phase locked loops High-speed electronics

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architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays

Architecture Exploration and Tools for Pipelined Coarse-Grai...

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international conference on Field Programmable Logic and Applications

作者： Florian Stock Andreas Koch Department for Integrated Technical University of Braunschweig Brunswick Germany Embedded Systems and Applications Group (ESA) Technical University of Darmstadt Darmstadt Germany

The paper presents a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools perform a simultaneous mapping and pipelining-aware placement, which is then followed by a congestion-avoiding router. Initial experiments show that this flow can succeed in implementing applications with smaller track count and reduced connectivity than existing commercial tools, suggesting changes to the original array architecture. The placer can reduce pipeline latency mismatches on converging paths, simplifying the problem for a pipelining-aware routing step

关键词： Delay Tiles Computer architecture Throughput Switches Fabrics Target tracking Integrated circuit synthesis Integrated circuit modeling Reconfigurable architectures

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Resource virtualization in real-time CORBA middleware

Resource virtualization in real-time CORBA middleware

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international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： Christopher D. Gill Department of Computer Science and Engineering Washington University Saint Louis MO USA

Middleware for parallel and distributed systems is designed to virtualize computation and communication resources so that a more abstract and consistent view of those resources is presented to the applications that use them. Providing such a consistent virtualization in distributed real-time and embedded systems becomes increasingly challenging due to application constraints such as timeliness and resource constraints such as CPU speed, power, memory, and bandwidth limitations, which also must be considered. This paper describes several examples of real-time CORBA middleware and examines how different constraints impact the way in which resources are virtualized in each case. Particular attention is paid to which details are hidden from users of the middleware, which details are exposed in the middleware's programming model, and how the hidden and exposed details interact to shape middleware design and implementation choices.

关键词： Resource virtualization Middleware Real time systems Application virtualization Distributed computing Concurrent computing embedded system Programming profession Application software Computer architecture

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Equivalence checking: a rule-based approach

Equivalence checking: a rule-based approach

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： M. Fujita S. Shankar S. Shunsuke University of Tokyo Japan CUNY City University of New York USA

A well-known problem in the design of embedded systems is checking for equivalence of two systems, and the traditional approach constructs and proves equivalence of finite state models of the two systems. Although widely and successfully used, the main problem is state space explosion, and other forms of higher-level analysis are also needed typically. Many typical system level design/synthesis tools and methodologies basically transform the control structures among function calls and/or sets of statements, with little modification to statements themselves. For example, the systems might differ only in statement order, dataflows (for differing amounts of parallelism), or abstraction levels. For such cases, we have developed an approach based on higher level static code analysis, and we have implemented a tool targeted at the SpecC language

关键词： Control systems Discrete transforms embedded system State-space methods Explosions System-level design Control system synthesis Data mining Prototypes Very large scale integration

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An on-chip diagnosis methodology for embedded cores with replaceable modules

An on-chip diagnosis methodology for embedded cores with rep...

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international conference on VLSI Design

作者： R.C. Tekumalla ATI Research Inc. Marlborough MA USA

We propose a design for test and diagnosis architecture that simplifies the process of identifying failures within a failing sub-module, without explicitly identifying the faults responsible for that failure. The extra hardware eliminates the post-processing step needed to process the failure logs from the tester and automatically determines the sub-modules inside a core that must be replaced. The proposed methodology reduces the turnaround time for locating a failing module or sub-module and also facilitates testing and diagnosis at the same time. Experimental results are presented using industrial test-cases to validate the effectiveness of the proposed method.

关键词： Fault diagnosis Circuit testing Pins Circuit faults Compaction Bandwidth Hardware Automatic testing Design methodology Combinational circuits

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Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus synthesis

Energy Conscious Simultaneous Voltage Scaling and On-chip Co...

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IFIP international conference on Very Large Scale Integration (VLSI-SoC)

作者： Sujan Pandey Tudor Murgan Manfred Glesner Institute of Microelectronics Systems Darmstadt University of Technology Darmstadt Germany

Due to the ever increasing trend of system complexity and technology scaling, synthesizing on-chip communication architecture appears to be a challenging task for the system designers. The traditional approaches are mostly based on the simulation of an entire system. However, the resulting architecture may not fulfil the requirements such as the performance, energy, size etc. and the computational cost of simulation based techniques is infeasible when exploring a large design space. This paper presents a simultaneous on-chip communication bus synthesis and voltage scaling approach, which is modeled in NLP (nonlinear programming) and finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The voltages (supply and body bias) are scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 57.1% by scaling its supply and body bias voltages

关键词： Voltage Computer architecture Topology System-on-a-chip Computational modeling Energy consumption Energy efficiency Computational efficiency Libraries embedded system

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Statistical Verification of Hyperproperties for Cyber-Physical systems

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 92-92页

作者： Wang, Yu Zarei, Mojtaba Bonakdarpour, Borzoo Pajic, Miroslav Duke Univ 100 Sci DrHudson Hall Rm 220 Durham NC 27708 USA Iowa State Univ 207 Atanasoff Hall Ames IA 50011 USA

Many important properties of cyber-physical systems (CPS) are defined upon the relationship between multiple executions simultaneously in continuous time. Examples include probabilistic fairness and sensitivity to modeling errors (i.e., parameters changes) for real-valued signals. These requirements can only be specified by hyperproperties. In this article, we focus on verifying probabilistic hyperproperties for CPS. To cover a wide range of modeling formalisms, we first propose a general model of probabilistic uncertain systems (PUSs) that unify commonly studied CPS models such as continuous-time Markov chains (CTMCs) and probabilistically parametrized Hybrid I/O Automata (P(2)HIOA). To formally specify hyperproperties, we propose a new temporal logic, hyper probabilistic signal temporal logic (HyperPSTL) that serves as a hyper and probabilistic version of the conventional signal temporal logic (STL). Considering the complexity of real-world systems that can be captured as PUSs, we adopt a statistical model checking (SMC) approach for their verification. We develop a new SMC technique based on the direct computation of significance levels of statistical assertions for HyperPSTL specifications, which requires no a priori knowledge on the indifference margin. Then, we introduce SMC algorithms for HyperPSTL specifications on the joint probabilistic distribution of multiple paths, as well as specifications with nested probabilistic operators quantifying different paths, which cannot be handled by existing SMC algorithms. Finally, we show the effectiveness of our SMC algorithms on CPS benchmarks with varying levels of complexity, including the Toyota Powertrain Control System.

关键词： Cyber-physical systems hyperproperties statistical model checking embedded control software

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Predictable dynamic embedded data processing

Predictable dynamic embedded data processing

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international conference on embedded Computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Marc Geilen Sander Stuijk Twan Basten Eindhoven University of Technology Department of Electrical Engineering Eindhoven The Netherlands Embedded Systems Institute Eindhoven The Netherlands

Cyber-physical systems interact with their physical environment. In this interaction, non-functional aspects, most notably timing, are essential to correct operation. In modern systems, dynamism is introduced in many different ways. The additional complexity threatens timely development and reliable operation. Applications often have different modes of operation with different resource requirements and different levels of required quality-of-service. Moreover, multiple applications in dynamically changing combinations share a platform and its resources. To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done. This requires a model-driven design approach in which timing of interaction with the physical environment is taken into consideration; formal models capture applications and their platforms in the physical environment. Moreover, platforms with resources and resource arbitration are needed that allow for predictable and reliable behavior to be realized. Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time. In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time management approach to deal with dynamic use-cases at run-time. A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use. The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient knapsack heuristic.

关键词： Tiles Payloads Computational modeling Schedules Hardware Synchronization

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