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international conference on Field Programmable Logic and Applications

作者： Andreas Fidjeland Wayne Luk Imperial College London London UK

This paper presents Archlog, a language and framework for designing multiprocessor architectures in the logic programming domain. Our goal is to enable application developers in areas such as machine learning and cognitive robotics to produce high-performance designs for reconflgurable devices, without detailed knowledge of hardware development. The Archlog framework provides a high level of abstraction, enabling rapid system generation while supporting high performance. In this paper we present the Archlog language and its library-based compilation framework, which makes use of a customisable logic programming processor. The system generates multiple designs, with different trade-offs in the use of reconfigurable logic and embedded memories. An implementation of a multiprocessor for the machine learning system Progol on a 40MHz XC2V6000 FPGA is 10 times faster than a 2GHz Pentium 4 processor

关键词： High level synthesis Logic programming Hardware Cognitive robotics Computer architecture Machine learning Reconfigurable logic System-on-a-chip Educational institutions Learning systems

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Streamroller:: automatic synthesis of prescribed throughput accelerator pipelines

Streamroller:: automatic synthesis of prescribed throughput ...

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international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： Scott Mahlke Kevin Fan Manjunath Kudlur Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements.

关键词： Throughput Pipelines Hardware Kernel Design methodology Cost function Linear accelerators High level synthesis Algorithm design and analysis embedded computing

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Hybrid custom instruction and co-processor synthesis methodology for extensible processors

Hybrid custom instruction and co-processor synthesis methodo...

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international conference on VLSI Design

作者： Fei Sun S. Ravi A. Raghunathan N.K. Jha Tensilica Inc. Santa Clara CA USA NEC Laboratories of America Inc. Princeton NJ USA Department of Electrical Engineering Princeton University Princeton NJ USA

Classical hardware/software partitioning techniques, recent advances in application-specific instruction set architecture (ISA) design tools, etc., provide avenues to address the individual problems of coprocessor generation and custom instruction addition for extensible processors. However, we argue that there is a need for hybrid synthesis techniques by demonstrating that a combination of custom instructions and co-processors is often the better solution in many applications. We propose a systematic methodology that builds on basic observations and trade-offs associated with co-processors and custom instructions: coprocessors are good for performing coarse-grained tasks that require minimal intervention or support from the processor, while custom instructions are efficient solutions for fine-grained tasks that are best integrated into a processor's pipeline. We have developed a hierarchical synthesis flow that incorporates a muti-objective evolutionary algorithm in order to handle diverse design dimensions such as area, performance. We have implemented the proposed methodology in the context of a commercial extensible processor based platform (Xtensa/spl trade/ from Tensilica). Our design flow incorporates a commercial behavioral synthesis tool and an automatic custom instruction generation engine. Our experiments with several applications show that simultaneous custom instruction and co-processor synthesis can achieve significantly better area/performance trade-offs than using only one of them.

关键词： Coprocessors Hardware Space exploration Software tools Pipelines Evolutionary computation Algorithm design and analysis Engines Sun National electric code

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Automatic generation of transaction level models for rapid design space exploration

Automatic generation of transaction level models for rapid d...

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international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： Junyu Peng Andreas Gerstlauer Daniel D. Gajski Rainer Domer Dongwan Shin Center for Embedded Computer Systems University of California Irvine CA USA

Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate such transaction-level models from abstract input descriptions. Designers have to write such models manually, which is a tedious and error-prone task, and one of bottlenecks in improving designer's productivity. In this paper, we propose a method to generate transaction-level models from virtual architecture models where components communicate via abstract message-passing channels. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness and benefits of our approach for rapid, early exploration of communication design space.

关键词： Space exploration Computational modeling Productivity System-on-a-chip Permission Concrete embedded computing Computer simulation Design automation System-level design

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Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations

Yield prediction for architecture exploration in nanometer t...

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international conference on Hardware/Software Codesign and System synthesis (CODES)

作者： T. Grabner F. Catthoor M. Miranda P. Roussel A. Papanikolaou IMEC vzw Leuven Belgium

Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing violations. Conventional yield models do not allow to accurately analyze this, at least not at the system level. In this paper we propose a technique to estimate this system level yield loss for a number of alternative memory organization implementations. This can aid the designer into making educated trade-offs at the architecture level between energy consumption and parametric timing yield by using memories from different available libraries with different energy/performance characteristics considering the impact of manufacturing variations. The accuracy of this technique is very high, an average error of less than 1% is reported, which enables an early exploration of the available options.

关键词： Predictive models Timing Energy consumption embedded system Performance loss Yield estimation Manufacturing Power system reliability Real time systems System-level design

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HotpathVM: an effective JIT compiler for resource-constrained devices 06

HotpathVM: an effective JIT compiler for resource-constraine...

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Proceedings of the 2nd international conference on Virtual execution environments

作者： Andreas Gal Christian W. Probst Michael Franz University of California Irvine Irvine CA Technical University of Denmark Lyngby Denmark

ISBN: (纸本)9781595933324

We present a just-in-time compiler for a Java VM that is small enough to fit on resource-constrained devices, yet is surprisingly effective. Our system dynamically identifies traces of frequently executed bytecode instructions (which may span several basic blocks across several methods) and compiles them via Static Single Assignment (SSA) construction. Our novel use of SSA form in this context allows to hoist instructions across trace side-exits without necessitating expensive compensation code in off-trace paths. The overall memory consumption (code and data) of our system is only 150 kBytes, yet benchmarks show a speedup that in some cases rivals heavy-weight just-in-time compilers.

关键词： dynamic compilation embedded and resource-constrained systems mixed-mode interpretive compiled systems software trace scheduling static single assignment form virtual machines

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Evolving System Services to Meet Application Requirements

Evolving System Services to Meet Application Requirements

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Annual Hawaii international conference on System Sciences (HICSS)

作者： H. Detmold K. Falkner D.S. Munro T. Olds A. Zakarevicius School of Computer Science University of Adelaide Australia

An increasingly common server deployment scenario involves dedicated servers supporting single applications. In such cases, system software need not be concerned with fairness between applications, but should instead focus on serving the precise needs of one particular application. To meet this goal, system software must permit applications to express their needs and must evolve to meet those needs. The fixed abstractions in conventional systems software militate against both expression of applications’ needs and against restructuring of system components to meet those needs. The compliant systems architecture (CSA) is a novel language-based software architecture that promises to enhance the extent to which system software is compliant to the applications it supports. Using our CSA instantiation, we identify several tactics for evolving system software to enhance compliance. The principal contribution of this paper is practical validation of CSA, via case studies of these tactics, demonstrating improved system services for an application.

关键词： Application software System software Computer architecture Yarn Software architecture Sockets Computer science Web server embedded system Computer languages

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IEC 61499 Model for Avionics Distributed Fuel systems with Networked embedded Holonic Controllers

IEC 61499 Model for Avionics Distributed Fuel Systems with N...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： Carlos C. Insaurralde Miguel A. Seminario Juan F. Jimenez Jose M. Giron-Sierra Department Arquitectura de Computadores y Automática Universidad Complutense de Madrid Madrid Spain

A current methodology for modeling distributed control systems (DCSs) is the standard IEC 61499. This technology is mainly applied in modern manufacturing industrial automation but it has begun to extend to other application areas. This paper proposes, in the framework of a European Research Project, a widespread use of IEC 61499, modeling an avionic distributed fuel control system (ADFCS) with smart components. The main Project target is to change the actual centralized system architecture to a full distributed one. This new system architecture includes fieldbuses and intelligence on the system components which are automata with holonic behavior. According to these new fuel system characteristics, IEC 61499 is perfectly suitable to develop it and at a time, it is interesting to spread the development of this kind of system. The paper objective is to propose a graphic modeling representation methodology to create an ADFCS with smart components. Thus, the generalization and systematization of ADFCS developments is achieved. This paper presents the main ideas of the new distributed avionic system and the control modeling of this system with IEC 61499 function blocks (FBs). Also, a particular example of ADFCS is presented; a helicopter fuel system.

关键词： IEC standards Aerospace electronics Fuels Automatic control Distributed control Control system synthesis Manufacturing industries Manufacturing automation Intelligent systems Automata

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Requirements elicitation through model-driven evaluation of software components

Requirements elicitation through model-driven evaluation of ...

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international IEEE conference on Commercial-off-the-Shelf (COTS)-Based Software systems

作者： L. Chung Weimin Ma K. Cooper Department of Computer Science University of Texas Dallas Richardson TX USA

The use of software components is perceived to significantly shorten development time and cost, while improving quality, in developing a large, complex software system. A key premise to this perception seems to be the ability to effectively search, match, rank, and select software components, during the requirements engineering process. In this paper, we present a technique for eliciting requirements by using model-driven evaluation of software components, where the evaluation revolves around "models" of software components and "models" of the component-based application (CBA). As part of our ongoing project, component-aware requirements engineering (CARE), this model-driven evaluation technique is intended to match the models of the stakeholders' needs for the component-based application against the models of the capabilities of the set of components that are currently available. More specifically, this technique allows for an integrated use of several searching/matching techniques, such as keyword-based search, case-based reasoning (CBR) and analytic hierarchy process (AHP), in evaluating models of components' requirements against models of the requirements of the stakeholders of the CBA being elicited incrementally. The model-driven evaluation technique is illustrated using a home appliance control system (HACS) example.

关键词： Application software Software quality Software systems Costs Computer science Home appliances Control system synthesis embedded software Computer architecture Testing

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Synergistically Exploiting CNN Pruning and HLS Versioning for Adaptive Inference on Multi-FPGAs at the Edge

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ACM TRANSACTIONS ON embedded COMPUTING systems 2021年第5期20卷 59-59页

作者： Korol, Guilherme Jordan, Michael Guilherme Rutzig, Mateus Beck Schneider Beck, Antonio Carlos Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil Univ Fed Santa Maria Elect & Comp Dept Santa Maria RS Brazil

FPGAs, because of their energy efficiency, reconfigurability, and easily tunable HLS designs, have been used to accelerate an increasing number of machine learning, especially CNN-based, applications. As a representative example, IoT Edge applications, which require low latency processing of resource-hungry CNNs, offload the inferences from resource-limited IoT end nodes to Edge servers featuring FPGAs. However, the everincreasing number of end nodes pressures these FPGA-based servers with new performance and adaptability challenges. While some works have exploited CNN optimizations to alleviate inferences' computation and memory burdens, others have exploited HLS to tune accelerators for statically defined optimization goals. However, these works have not tackled both CNN and HLS optimizations altogether;neither have they provided any adaptability at runtime, where the workload's characteristics are unpredictable. In this context, we propose a hybrid two-step approach that, first, creates new optimization opportunities at design-time through the automatic training of CNN model variants (obtained via pruning) and the automatic generation of versions of convolutional accelerators (obtained during HLS synthesis);and, second, synergistically exploits these created CNN and HLS optimization opportunities to deliver a fully dynamic Multi-FPGA system that adapts its resources in a fully automatic or user-configurable manner. We implement this two-step approach as the AdaServ Framework and show, through a smart video surveillance Edge application as a case study, that it adapts to the always-changing Edge conditions: AdaServ processes at least 3.37x more inferences (using the automatic approach) and is at least 6.68x more energy-efficient (user-configurable approach) than original convolutional accelerators and CNN Models (VGG-16 and AlexNet). We also show that AdaServ achieves better results than solutions dynamically changing only the CNN model or HLS version, highlightin

关键词： FPGA CNN inference pruning High-Level synthesis Edge computing

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