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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是31-40 订阅

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Work-in-Progress: RISC-V Based Low-cost embedded Trace Processing System

Work-in-Progress: RISC-V Based Low-cost Embedded Trace Proce...

引用

international conference on compilers, architecture, and synthesis for embedded systems (cases)

作者： Hu, Xiao Wang, Yaohua Gao, Xuan Natl Univ Def Technol Sch Comp Changsha 410073 Peoples R China

ISBN: (数字)9781665472968

ISBN: (纸本)9781665472968

Although on-chip Trace debugging plays a key role in post-silicon debug and software optimizations, it suffers from massive trace information handling with limited on-chip hardware resources in embedded SoC processors. To this end, this paper proposes a Low-cost embedded Trace Processing System (LE-TPS). LE-TPS employs a low-cost RISC-V core with customized trace handling instructions to exploit the underutilized resources of existing SoCs. This helps LE-TPS to collect, store and transmit the trace information in a way with low hardware cost, software independent feature, and minimal performance overhead. We believe that LE-TPS could be effective in post-silicon debug and software optimizations.

关键词： processor trace debug profile RISC-V

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Automated ISA Branch Coverage Analysis and Test Case Generation for Retargetable Instruction Set Simulators

Automated ISA Branch Coverage Analysis and Test Case Generat...

引用

international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Wagstaff, Harry Spink, Tom Franke, Bjoern Univ Edinburgh Edinburgh EH8 9YL Midlothian Scotland

ISBN: (纸本)9781450330503

Processor design tools integrate in their workflows generators for instruction set simulators (ISS) from architecture descriptions. However, it is difficult to validate the correctness of these simulators. ISA coverage analysis is insufficient to isolate modelling faults, which might only be exposed in corner cases. We present a novel ISA branch coverage analysis, which considers every possible execution path within an instruction and, on demand, generates new test cases to cover the missing paths. We have applied this analysis to industry standard EEMBC and SPEC CPU2006 benchmarks and show that for an ARM V5T model neither of these benchmark suites provides a sufficient ISA coverage to exercise every path through each instruction of the whole instruction set.

关键词： fault tolerant computing instruction sets program diagnostics program testing ARM V5T model EEMBC benchmark ISA branch coverage analysis ISS SPEC CPU2006 benchmark instruction execution path modelling fault isolation processor design tools retargetable instruction set simulators test case generation Benchmark testing Context Generators Registers Semantics Vectors instruction sets CASING INSPECTION analysis programme Benchmark testing Fault tolerant computing program testing Registers dynamos international space stations European Union Institute for Security Studies Semantics Coverage execution path

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Cognitive Cameras: Assistive Vision systems

Cognitive Cameras: Assistive Vision Systems

引用

international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Irick, Kevin M. Zientara, Peter A. Sampson, Jack Narayanan, Vijaykrishnan SiliconScapes LLC State Coll PA 16803 USA Penn State Univ University Pk PA USA

ISBN: (纸本)9781467383202

As a benefactor of the proliferation of large scale integration, traditionally simple and unintelligent devices such as cameras have been transformed into key components of rich and engaging smart environments. By integrating machine perception algorithms, these cognitive cameras have the ability to perceive and understand their environments. A principal barrier to realizing the potential of cognitive cameras has been the absence of sufficient computing power within the device. This is especially true in wearable devices which are limited by both compute capability and energy. Hardware customization and specialization present effective solutions to the power and performance bottlenecks that have limited ubiquitous adoption. This work details the architecture, design, and evaluation of a cognitive camera system that employs custom hardware to meet both power and performance constraints. Furthermore we illustrate its use as an assistance system for the visually impaired.

关键词： cognitive computing vision hardware acceleration embedded system architecture system-on-chip wearable

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Work-in-Progress: Code-Size-Aware Mapping for Synchronous Dataflow Graphs on Multicore systems

Work-in-Progress: Code-Size-Aware Mapping for Synchronous Da...

引用

international conference on compilers architectures and synthesis For embedded systems (cases)

作者： Ma, Mingze Sakellariou, Rizos Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (纸本)9781450351843

Synchronous Dataflow Graphs (SDFGs) are widely used to model streaming applications (e.g. digital signal processing applications), which are commonly executed by embedded systems. The usage of on-chip resources is always strictly constrained in embedded systems. As the cost of instruction memory is a significant part of on-chip resource costs, code size reduction is an effective way to control the overall costs of on-chip resources. In this work, a code-size-aware mapping heuristic is proposed to decrease the code size for SDFGs on multicore systems. The mapping heuristic is jointly used with a self-timed scheduling heuristic to decrease the code size of the original schedule. In preliminary experiments, the proposed heuristic achieves significant code size reduction for all the tested SDFGs without affecting throughput.

关键词： Multicore processing Throughput Processor scheduling Schedules Satellites Digital signal processing embedded systems

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Proceedings of the international conference on compilers, architecture and synthesis for embedded systems: Preface

Proceedings of the International Conference on Compilers, Ar...

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Palem, Krishna V.

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embedded System and Application Aware Design of Deregulated Energy Delivery systems

Embedded System and Application Aware Design of Deregulated ...

引用

international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： He, Xuejing Dick, Robert P. Joseph, Russ Univ Michigan Ann Arbor MI 48109 USA Northwestern Univ Evanston IL 60208 USA

ISBN: (纸本)9781467383202

Voltage regulation circuity can be removed from embedded systems, commonly saving 30% of the printed circuit board area. Most unregulated systems suffer from performance degradation or premature failure as battery voltage decreases. Researchers have described a technique called power deregulation, in which performance is preserved by activating processor cores as battery voltage decreases. Unfortunately, the operating lifespans of such systems may be limited due to mismatches between the battery discharge profiles and the voltage-performance characteristics of processors. This paper provides a technique for codesign of power deregulated systems in which battery, processor, and workload characteristics are jointly considered. This technique extends lifespans of deregulated embedded systems. We also describe new battery and system performance and power models, some of which are based on a recently commercialized silver-zinc battery technology that is well suited to power deregulated systems. These models support lifetime simulation of regulated and deregulated embedded systems. If it is possible to find an appropriate match between embedded system and battery characteristics, the proposed design technique results in lifetimes similar to those of regulated systems and eliminates the need for bulky power regulation components.

关键词： Battery embedded systems Energy Voltage regulator

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Work-in-Progress: A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM

Work-in-Progress: A Processing-in-Pixel Accelerator based on...

引用

international conference on compilers, architecture, and synthesis for embedded systems (cases)

作者： Abedin, Minhaz Roohi, Arman Cady, Nathaniel Angizi, Shaahin SUNY Polytech Inst Coll Nanoscale Sci & Engn Albany NY 12203 USA Univ Nebraska Sch Comp Lincoln NE USA New Jersey Inst Technol Dept Elect & Comp Engn Newark NJ 07102 USA

ISBN: (数字)9781665472968

ISBN: (纸本)9781665472968

This work paves the way to realize a processingin-pixel accelerator based on a multi-level HfOx ReRAM as a flexible, energy-efficient, and high-performance solution for real-time and smart image processing at edge devices. The proposed design intrinsically implements and supports a coarsegrained convolution operation in low-bit-width neural networks leveraging a novel compute-pixel with non-volatile weight storage at the sensor side. Our evaluations show that such a design can remarkably reduce the power consumption of data conversion and transmission to an off-chip processor maintaining accuracy compared with the recent in-sensor computing designs.

关键词： Power demand embedded systems Data conversion Convolution Image processing Image edge detection Neural networks

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Exploiting Cache Conflicts to Reduce Radiation Sensitivity of Operating systems on embedded systems

Exploiting Cache Conflicts to Reduce Radiation Sensitivity o...

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Santini, Thiago Rech, Paolo Carro, Luigi Wagner, Flavio Rech Univ Fed Rio Grande do Sul Inst Informat PPGC BR-90046900 Porto Alegre RS Brazil

ISBN: (纸本)9781467383202

In this paper, we investigate how the presence of a general purpose operating system influences the reliability of modern embedded systems-on-Chips (SoCs). We analytically study the difference in the reliability of SoCs when executing the application bare to the metal and on top of the Linux kernel. Our analysis demonstrates that Linux presence barely affects the Silent Data Corruption rate while it greatly increases the system Functional Interruption (FI) rate (up to 7.48 times) if no preventive measures are taken. Furthermore, we analytically show that cache conflicts between the operating system and application can significantly reduce the Linux-induced FI rate increase. To support our analysis, a total of four representative embedded applications were individually executed bare to the metal and on top of Linux on a 28nm ARM-based SoC exposed to an accelerated neutron beam. Our experimental results demonstrate that, by carefully tuning cache conflicts, it is possible to successfully limit the Linux-induced FI rate increase to 3.85 times. The proposed solution is general and readily applied to a broad set of applications and embedded systems.

关键词： Applications Reliability System-on-Chip Experimentation Reliability

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Optimization of Multi-Channel BCH Error Decoding for Common cases

Optimization of Multi-Channel BCH Error Decoding for Common ...

引用

international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Dill, Russ Shrivastava, Aviral Oh, Hyunok Arizona State Univ Tempe AZ 85287 USA Hanyang Univ Seoul South Korea

ISBN: (纸本)9781467383202

This paper proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. We break the BCH decoding process into its three basic blocks: syndrome calculation, the error locator polynomial generation, and the roots of the error locator polynomial computation. While an existing multi-channel BCH decoder consists of several single-channel BCH decoders operating in parallel, this paper utilizes a pooled group of shared decoding blocks. By considering the frequency of errors, the proposed pooled group approach requires fewer hardware blocks than in a traditional multi-channel configuration with a negligible impact on performance. Combined with a specialized root finding unit for blocks with only 1 error, our scheme reduces hardware area by 47%-71 % and dynamic power by 44%-59% with 2% performance degradation in typical NAND flash systems. With a constant hardware area, the proposed scheme can improve throughput by 3x-5x or NAND flash lifetime by 1.4x-4.5x.

关键词： Clocks Error correction codes Force Polynomials Throughput

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Work-in-Progress: Smart data reduction in SLAM methods for embedded systems

Work-in-Progress: Smart data reduction in SLAM methods for e...

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international conference on compilers, architecture, and synthesis for embedded systems (cases)

作者： Picard, Quentin Chevobbe, Stephane Darouich, Mehdi Mandelli, Zoe Carrier, Mathieu Didier, Jean-Yves CEA LIST F-91191 Gif Sur Yvette France Univ Paris Saclay Univ Evry IBISC F-91025 Evry France

ISBN: (数字)9781665472968

ISBN: (纸本)9781665472968

Visual-inertial simultaneous localization and mapping methods (SLAM) process and store large amounts of data based on image sequences to estimate accurate and robust realtime trajectories. Real-time performances, memory management and low power consumption are critical for embedded SLAM with restrictive hardware resources. We aim at reducing the amount of injected input data in SLAM algorithms and, thereby, the memory footprint while providing improved real-time performances. Two decimation approaches are used, constant filtering and adaptive filtering. The first one decimates input images to reduce frame rate (from 20 to 10, 7, 5 and 2 fps). The latter one uses inertial measurements to reduce the frame rate when no significant motion is detected. Applied to SLAM methods, it produces more accurate trajectories than the constant filtering approach, while further reducing the amount of injected data up to 85%. It also impacts the resource utilization by reducing up to an average of 91% the peak of memory consumption.

关键词： SLAM localization embedded systems realtime data reduction memory management

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