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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Ottlik, Sebastian Stattelmann, Stefan Viehl, Alexander Rosenstiel, Wolfgang Bringmann, Oliver FZI Res Ctr Informat Technol D-76131 Karlsruhe Germany ABB Corp Res Res Area Software D-68526 Ladenburg Germany Univ Tubingen D-72076 Tubingen Germany

ISBN: (纸本)9781450330503

We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the microarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional simulation.

关键词： Software Timing Simulation Binary Level Simulation Instruction Set Simulation System Level Design Virtual Prototyping

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems

Proceedings of the international conference on compilers, ar...

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

ISBN: (纸本)1581133383

The proceedings contain 27 paper from the conference on Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems. Topic discussed include: efficient compilation of ESTEREL for real-time embedded systems;eliminating external fragmentation in a non-moving garbage collector for Java;a code generation framework for Java component-based designs and a preprocessing step for global loop transformations for data transfer optimization.

关键词： embedded systems

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Report on the 2022 embedded systems Week (ESWEEK)

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2023年第1期40卷 108-111页

作者： Shrivastava, Aviral Hu, Xiaobo Sharon Arizona State Univ Tempe AZ 85281 USA Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

embedded systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences [the international conference on compilers, architecture, and synthesis for embedded systems (cases); the international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS); and the international conference on embedded Software (EMSOFT)] and a variety of symposia, hot-topic workshops, tutorials, and education classes, ESWEEK presents to the attendees a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.

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On Evaluation of On-chip Thermal Covert Channel Attacks

On Evaluation of On-chip Thermal Covert Channel Attacks

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international conference on compilers, architecture, and synthesis for embedded systems (cases)

作者： Wang, Jiachen Wang, Xiaohang Jiang, Yingtao Singh, Amit Kumar Huang, Letian Yang, Mei South China Univ Technol Sch Software Engn Guangzhou 510006 Guangdong Peoples R China Chinese Acad Sci Inst Comp Technol Zhejiang Lab Beijing Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Univ Nevada Dept Elect & Comp Engn Las Vegas NV 89557 USA Univ Essex Colchester Essex England Univ Elect Sci & Technol China Chengdu Peoples R China

ISBN: (数字)9781665472968

ISBN: (纸本)9781665472968

Thermal covert channel (TCC) attacks have been a serious security concern to the use of many-core chips. Severity of these attacks is directly linked to the TCC's transmission rate and its BER (bit error rate) performance, both of which are impacted by the transmission characteristics of thermal signals and adopted encoding, modulation, and multiplexing schemes. This paper examines, compares, and analyzes various TCCs built upon different combinations of encoding, modulation, and multiplexing. In particular, our study shows that TCC using non-return-to-zero (NRZ) line coding and frequency shift keying (FSK) modulation achieves the highest throughput of 120 bps

关键词： Multiplexing embedded systems Bit error rate Modulation Frequency shift keying Throughput Encoding

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NUVA: Architectural Support for Runtime Verification of Parametric Specifications over Multicores

NUVA: Architectural Support for Runtime Verification of Para...

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Nassar, Ahmed Kurdahi, Fadi J. Elsharkasy, Wael Univ Calif Irvine Dept EECS Ctr Embedded & Cyber Phys Syst Irvine CA 92697 USA

ISBN: (纸本)9781467383202

Runtime Verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification methods. To address the substantial performance and power overhead of pure software RV frameworks, this paper introduces NUVA, which stands for nonuniform verification architecture, a distributed automata-based RV architecture for parametric specifications in the form of parameterized finite-state automata, with a case study over a cache-coherent nonuniform-memory-access (ccNUMA) multiprocessor. The core of NUVA is a coherent distributed automata transactional memory (ATM) that efficiently maintains states of a dynamic population of automata checkers organized into a rooted dynamic directed acyclic graph (DAG) concurrently shared among all processor nodes. A cycle-accurate model of a ccNUMA multiprocessor confirms that performance slowdown is 1 similar to 3% and NoC message traffic increases by 10 similar to 15% at parametric event density(1) of 0.025 EPI for two compute-intensive scientific benchmarks having irregular concurrent data structures. The detailed architecture and implementation metrics in TSMC 40nm CMOS technology are presented. NUVA can be dimensioned to incur average total power overhead of less than 140mW and area overhead of 4mm(2) for a quad-core multiprocessor chip, at operating frequency of 250MHz. It is also estimated to incur 1.9 similar to 2.6% area overhead and 0.5 similar to 1% power overhead when integrated with Intel's family of high-end desktop and mobile quad-core processors operating at 1.6 similar to 3.2GHz. Our silicon implementation achieves average performance(2) of 1.5 MEPS/mW. For a processor core with 5 MIPS/mW, this corresponds to a 3.2% drop in energy efficiency at parametric event density of 0.01 EPI.

关键词： Runtime verification automata concurrency

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Team Up: Cooperative Memory Management in embedded systems

Team Up: Cooperative Memory Management in Embedded Systems

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Stilkerich, Isabella Taffner, Philip Erhardt, Christoph Dietrich, Christian Wawersich, Christian Stilkerich, Michael Univ Erlangen Nurnberg D-91054 Erlangen Germany

ISBN: (纸本)9781450330503

The use of a managed, type-safe languages such as Java in real-time and embedded systems can offer productivity and, in particular, safety and dependability benefits over the dominating unsafe languages at reasonable costs. A JVM that has dynamic memory-management needs to provide an implicit memory-management strategy, that is, for example, a garbage collector (GC) or stack allocation provided by the escape analysis of the JVM's compiler: Explicit management of dynamically allocated memory (i.e., by use of functions such as C's malloc () and free ()) is vulnerable to programming errors such as neglected or false memory release operations causing memory leaks or dangling pointers. Such operations have the potential to break the soundness of the type system and are therefore usually not available for strongly typed languages. Type-safe languages in combination with static analyses - which respect hardware as well as system-specific information - can efficiently be employed to provide a runtime system including memory management (MM) that is specifically suited to an embedded application on a particular hardware device. In the context of this paper, we present novel memory-management strategy we implemented in our KESO JVM. It is a latency-aware garbage-collection algorithm called LAGC. Also, we introduce the static analyses that can assist LAGC. The application developers have to ensure that there is enough time for the GCs to run. Hardware characteristics such as soft-error proneness of the hardware or the memory layout can also be taken into consideration as demanded by the system configuration. This is achieved by integrating the GCs in the design process of the whole system just as any other user application, which is the reason why this approach is called cooperative memory management. The suggested strategies require reasonably low overhead.

关键词： Memory Management Garbage Collection Design Languages

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Rigorous development of embedded systems

Rigorous development of embedded systems

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Pnueli, Amir

ISBN: (纸本)1581133383

The rigorous development of embedded systems was discussed. The components of European Esprit project Sacres environment which included executable system specification language of Statecharts or the dataflow-based specification language Sildex were elaborated. Several approaches that helps designers of an embedded system to formulate their requirement in either a visual style were also presented.

关键词： embedded systems

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Energy-interference-free System and Toolchain Support for Energy-harvesting Devices

Energy-interference-free System and Toolchain Support for En...

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Colin, Alexei Sample, Alanson P. Lucia, Brandon Carnegie Mellon Univ Pittsburgh PA 15213 USA Disney Res Pittsburgh PA USA

ISBN: (纸本)9781467383202

Energy-harvesting computers eschew tethered power and batteries by harvesting energy from their environment. The devices gather energy into a storage element until they have enough energy to power a computing device. Once powered, the device functions until its energy is depleted, when it browns out and gathers more energy. Software on such computing devices executes intermittently, as power is available. An intermittent program execution may be interrupted by a power failure at any point and with each interruption, the volatile state of the device (e.g., register file, RAM) is erased, and its non-volatile state (e.g., FRAM) is retained. Recent work [3] defined and characterized the intermittent execution model, in which a program's execution spans periods of execution perforated by power failures. Our position is that designers of system and toolchain support for energy-harvesting devices should treat energy-interference-freedom and intermittence as first-class design concerns in future systems, methodologies, and techniques. From this position, we discuss the design of an energy-interference-free platform for monitoring and manipulating the energy and device state of an energy-harvesting device. We see our platform as an essential step toward a toolchain for energy-harvesting devices that supports debugging, testing, and analysis of realistic, intermittent executions.

关键词： energy harvesting power aware computing program debugging system monitoring batteries computing device debugging energy-harvesting computers energy-harvesting devices energy-interference-free platform design energy-interference-free system energy-interference-freedom intermittence intermittent execution model intermittent executions intermittent program execution monitoring nonvolatile state power failure storage element testing tethered power toolchain support Computer bugs Debugging embedded systems Energy states Energy storage Monitoring Nonvolatile memory Debugging energy harvesting power generation faults memory element power aware computing system monitoring Energy level tool chain Batteries Nonvolatile memory embedded systems Energy sources energy storage

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Run-Time Accuracy Reconfigurable Stochastic Computing for Dynamic Reliability and Power Management: Work-in-Progress

Run-Time Accuracy Reconfigurable Stochastic Computing for Dy...

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international conference on compilers, architecture, and synthesis for embedded systems (cases) / embedded systems Week (ESWEEK)

作者： Yu, Shuyuan Zhou, Han Peng, Shaoyi Amrouch, Hussam Henkel, Joerg Tan, Sheldon X-D Univ Calif Riverside Dept Elect & Comp Engn Riverside CA 92521 USA Karlsruhe Inst Technol Chair Embedded Syst CES Karlsruhe Germany

ISBN: (数字)9781728191928

ISBN: (纸本)9781728191928

In this paper, we propose a novel accuracy-reconfigurable stochastic computing (ARSC) framework for dynamic reliability and power management. Different than the existing stochastic computing works, where the accuracy versus power/energy trade-off is carried out in the design time, the new ARSC design can change accuracy or bit-width of the data in the run-time so that it can accommodate the long-term aging effects by slowing the system clock frequency at the cost of accuracy while maintaining the throughput of the computing. We validate the ARSC concept on a discrete cosine transformation (DCT) and inverse DCT designs for image compressing/decompressing applications, which are implemented on Xilinx Spartan-6 family XC6SLX45 platform. Experimental results show that the new design can easily mitigate the long-term aging induced effects by accuracy trade-off while maintaining the throughput of the whole computing process using simple frequency scaling. We further show that one-bit precision loss for the input data, which translated to 3.44dB of the accuracy loss in term of Peak Signal to Noise Ratio (PSNR) for images, we can sufficiently compensate the NBTI induced aging effects in 10 years while maintaining the pre-aging computing throughput of 7.19 frames per second. At the same time, we can save 74% power consumption by 10.67dB of accuracy loss. The proposed ARSC computing framework also allows much aggressive frequency scaling, which can lead to order of magnitude power savings compared to the traditional dynamic voltage and frequency scaling (DVFS) techniques.

关键词： PSNR Image coding Power system management Aging Throughput Reliability engineering Discrete cosine transforms

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Code transformation strategies for extensible embedded processors

Code transformation strategies for extensible embedded proce...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Bonzini, Paolo Pozzi, Laura Switzerland

ISBN: (纸本)1595935436

embedded application requirements, including high performance, low power consumption and fast time to market, are uncommon in the broader domain of general purpose applications. In order to satisfy these demands, chip manufacturers often provide developers with the possibility to define application-specific Instruction Set Extensions (ISEs). Many techniques have been proposed that automatically identify the most beneficial ISEs from source code, so that compilers can identify the 'best' instruction set for the underlying machine. However, can we simply retrofit these techniques into a traditional compiler, or does ISE identification demand different tuning of the heuristics utilized throughout the optimization pipeline? In this paper, we show why compilers should sometimes make different decisions when targeting customized processors, and we show how traditional ISE identification techniques can improve significantly if the code is properly transformed in order to expose more beneficial extensions. The proposed approach was validated using the SimpleScalar simulator for the ARM processor, augmented with the possibility to define additional *** benchmarks taken from the MiBench suite,we show that the proposed transformations improve state of the art ISE identi cation techniques by 55% on average and 4x maximum. Copyright 2006 ACM.

关键词： Program compilers

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