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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Stilkerich, Isabella Taffner, Philip Erhardt, Christoph Dietrich, Christian Wawersich, Christian Stilkerich, Michael Univ Erlangen Nurnberg D-91054 Erlangen Germany

ISBN: (纸本)9781450330503

The use of a managed, type-safe languages such as Java in real-time and embedded systems can offer productivity and, in particular, safety and dependability benefits over the dominating unsafe languages at reasonable costs. A JVM that has dynamic memory-management needs to provide an implicit memory-management strategy, that is, for example, a garbage collector (GC) or stack allocation provided by the escape analysis of the JVM's compiler: Explicit management of dynamically allocated memory (i.e., by use of functions such as C's malloc () and free ()) is vulnerable to programming errors such as neglected or false memory release operations causing memory leaks or dangling pointers. Such operations have the potential to break the soundness of the type system and are therefore usually not available for strongly typed languages. Type-safe languages in combination with static analyses - which respect hardware as well as system-specific information - can efficiently be employed to provide a runtime system including memory management (MM) that is specifically suited to an embedded application on a particular hardware device. In the context of this paper, we present novel memory-management strategy we implemented in our KESO JVM. It is a latency-aware garbage-collection algorithm called LAGC. Also, we introduce the static analyses that can assist LAGC. The application developers have to ensure that there is enough time for the GCs to run. Hardware characteristics such as soft-error proneness of the hardware or the memory layout can also be taken into consideration as demanded by the system configuration. This is achieved by integrating the GCs in the design process of the whole system just as any other user application, which is the reason why this approach is called cooperative memory management. The suggested strategies require reasonably low overhead.

关键词： Memory Management Garbage Collection Design Languages

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Report on the 2022 embedded systems Week (ESWEEK)

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2023年第1期40卷 108-111页

作者： Shrivastava, Aviral Hu, Xiaobo Sharon Arizona State Univ Tempe AZ 85281 USA Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

embedded systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences [the international conference on compilers, architecture, and synthesis for embedded systems (cases); the international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS); and the international conference on embedded Software (EMSOFT)] and a variety of symposia, hot-topic workshops, tutorials, and education classes, ESWEEK presents to the attendees a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems

Proceedings of the international conference on compilers, ar...

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

ISBN: (纸本)1581133383

The proceedings contain 27 paper from the conference on Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems. Topic discussed include: efficient compilation of ESTEREL for real-time embedded systems;eliminating external fragmentation in a non-moving garbage collector for Java;a code generation framework for Java component-based designs and a preprocessing step for global loop transformations for data transfer optimization.

关键词： embedded systems

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A high-level model of embedded flash energy consumption

A high-level model of embedded flash energy consumption

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Pallister, James Eder, Kerstin Hollis, Simon J. Bennett, Jeremy Univ Bristol Bristol BS8 1TH Avon England Embecosm Lymington Hants England

ISBN: (纸本)9781450330503

The alignment of code in the flash memory of deeply embedded SoCs can have a large impact on the total energy consumption of a computation. We investigate the effect of code alignment in six SoCs and find that a large proportion of this energy (up to 15% of total SoC energy consumption) can be saved by changes to the alignment. A flexible model is created to predict the read-access energy consumption of flash memory on deeply embedded SoCs, where code is executed in place. This model uses the instruction level memory accesses performed by the processor to calculate the flash energy consumption of a sequence of instructions. We derive the model parameters for five SoCs and validate them. The error is as low as 5%, with a 11% average normalized RMS deviation overall. The scope for using this model to optimize code alignment is explored across a range of benchmarks and SoCs. Analysis shows that over 30% of loops can be better aligned. This can significantly reduce energy while increasing code size by less than 4%. We conclude that this effect has potential as an effective optimization, saving significant energy in deeply embedded SoCs.

关键词： embedded systems energy consumption flash memories system-on-chip RMS deviation code alignment deeply embedded SoC embedded flash energy consumption energy proportion flash memory instruction level memory access root mean square deviation Ash Energy consumption Memory management Nonvolatile memory Optimization Random access memory System-on-chip system-on-chip flash memories energy consumption Root mean square deviation random access machine Store management Nonvolatile memory SYNTHETIC ORGANIC CHEMICALS embedded systems Ashes Codes

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Context-Sensitive Timing Simulation of Binary embedded Software

Context-Sensitive Timing Simulation of Binary Embedded Softw...

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Ottlik, Sebastian Stattelmann, Stefan Viehl, Alexander Rosenstiel, Wolfgang Bringmann, Oliver FZI Res Ctr Informat Technol D-76131 Karlsruhe Germany ABB Corp Res Res Area Software D-68526 Ladenburg Germany Univ Tubingen D-72076 Tubingen Germany

ISBN: (纸本)9781450330503

We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the microarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional simulation.

关键词： Software Timing Simulation Binary Level Simulation Instruction Set Simulation System Level Design Virtual Prototyping

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Timing Characterization of OpenMP4 Tasking Model

Timing Characterization of OpenMP4 Tasking Model

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Serrano, Maria A. Melani, Alessandra Vargas, Roberto Marongiu, Andrea Bertogna, Marko Quinones, Eduardo Tech Univ Catalonia Barcelona Spain Barcelona Supercomp Barcelona Spain Scuola Super Sant Anna Pisa Italy Swiss Fed Inst Technol Zurich Switzerland Univ Modena & Reggio Emilia Modena Italy

ISBN: (纸本)9781467383202

OpenMP is increasingly being supported by the newest high-end embedded many-core processors. Despite the lack of any notion of real-time execution, the latest specification of OpenMP (v4.0) introduces a tasking model that resembles the way real-time embedded applications are modeled and designed, i.e., as a set of periodic task graphs. This makes OpenMP4 a convenient candidate to be adopted in future real-time systems. However, OpenMP4 incorporates as well features to guarantee backward compatibility with previous versions that limit its practical usability in real-time systems. The most notable example is the distinction between tied and untied tasks. Tied tasks force all parts of a task to be executed on the same thread that started the execution, whereas a suspended untied task is allowed to resume execution on a different thread. Moreover, tied tasks are forbidden to be scheduled in threads in which other non-descendant tied tasks are suspended. As a result, the execution model of tied tasks, which is the default model in OpenMP to simplify the coexistence with legacy constructs, clearly restricts the performance and has serious implications on the response time analysis of OpenMP4 applications, making difficult to adopt it in real-time environments. In this paper, we revisit OpenMP design choices, introducing timing predictability as a new and key metric of interest. Our first results confirm that even if tied tasks can be timing analyzed, the quality of the analysis is much worse than with untied tasks. We thus reason about the benefits of using untied tasks, deriving a response time analysis for this model, and so allowing OpenMP4 untied model to be applied to real-time systems.

关键词： embedded systems message passing open systems OpenMP4 tasking model backward compatibility high-end embedded many-core processors real-time systems response time analysis timing characterization Analytical models Force Programming Real-time systems Scheduling algorithms Synchronization real-time systems backward compatibility time series analysis Scheduling algorithms Religious Missions message passing ANALYSIS MODELS open systems embedded systems Programming Force Legal Executions THREADS

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Rigorous development of embedded systems

Rigorous development of embedded systems

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Pnueli, Amir

ISBN: (纸本)1581133383

The rigorous development of embedded systems was discussed. The components of European Esprit project Sacres environment which included executable system specification language of Statecharts or the dataflow-based specification language Sildex were elaborated. Several approaches that helps designers of an embedded system to formulate their requirement in either a visual style were also presented.

关键词： embedded systems

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On Evaluation of On-chip Thermal Covert Channel Attacks

On Evaluation of On-chip Thermal Covert Channel Attacks

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international conference on compilers, architecture, and synthesis for embedded systems (cases)

作者： Wang, Jiachen Wang, Xiaohang Jiang, Yingtao Singh, Amit Kumar Huang, Letian Yang, Mei South China Univ Technol Sch Software Engn Guangzhou 510006 Guangdong Peoples R China Chinese Acad Sci Inst Comp Technol Zhejiang Lab Beijing Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Univ Nevada Dept Elect & Comp Engn Las Vegas NV 89557 USA Univ Essex Colchester Essex England Univ Elect Sci & Technol China Chengdu Peoples R China

ISBN: (数字)9781665472968

ISBN: (纸本)9781665472968

Thermal covert channel (TCC) attacks have been a serious security concern to the use of many-core chips. Severity of these attacks is directly linked to the TCC's transmission rate and its BER (bit error rate) performance, both of which are impacted by the transmission characteristics of thermal signals and adopted encoding, modulation, and multiplexing schemes. This paper examines, compares, and analyzes various TCCs built upon different combinations of encoding, modulation, and multiplexing. In particular, our study shows that TCC using non-return-to-zero (NRZ) line coding and frequency shift keying (FSK) modulation achieves the highest throughput of 120 bps

关键词： Multiplexing embedded systems Bit error rate Modulation Frequency shift keying Throughput Encoding

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Energy-interference-free System and Toolchain Support for Energy-harvesting Devices

Energy-interference-free System and Toolchain Support for En...

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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Colin, Alexei Sample, Alanson P. Lucia, Brandon Carnegie Mellon Univ Pittsburgh PA 15213 USA Disney Res Pittsburgh PA USA

ISBN: (纸本)9781467383202

Energy-harvesting computers eschew tethered power and batteries by harvesting energy from their environment. The devices gather energy into a storage element until they have enough energy to power a computing device. Once powered, the device functions until its energy is depleted, when it browns out and gathers more energy. Software on such computing devices executes intermittently, as power is available. An intermittent program execution may be interrupted by a power failure at any point and with each interruption, the volatile state of the device (e.g., register file, RAM) is erased, and its non-volatile state (e.g., FRAM) is retained. Recent work [3] defined and characterized the intermittent execution model, in which a program's execution spans periods of execution perforated by power failures. Our position is that designers of system and toolchain support for energy-harvesting devices should treat energy-interference-freedom and intermittence as first-class design concerns in future systems, methodologies, and techniques. From this position, we discuss the design of an energy-interference-free platform for monitoring and manipulating the energy and device state of an energy-harvesting device. We see our platform as an essential step toward a toolchain for energy-harvesting devices that supports debugging, testing, and analysis of realistic, intermittent executions.

关键词： energy harvesting power aware computing program debugging system monitoring batteries computing device debugging energy-harvesting computers energy-harvesting devices energy-interference-free platform design energy-interference-free system energy-interference-freedom intermittence intermittent execution model intermittent executions intermittent program execution monitoring nonvolatile state power failure storage element testing tethered power toolchain support Computer bugs Debugging embedded systems Energy states Energy storage Monitoring Nonvolatile memory Debugging energy harvesting power generation faults memory element power aware computing system monitoring Energy level tool chain Batteries Nonvolatile memory embedded systems Energy sources energy storage

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Report on the 2023 embedded systems Week (ESWEEK)

IEEE Design and Test

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IEEE Design and Test 2024年第2期41卷 84-87页

作者： Hu, Xiaobo Sharon Girault, Alain Falk, Heiko University of Notre Dame Notre DameIN46556 United States Université Grenoble Alpes Inria Cnrs Grenoble Inp Grenoble38000 France Tu Hamburg Hamburg21073 Germany

embedded systems Week (ESWEEK) is the premier worldwide event covering all aspects of embedded systems, encompassing software, hardware, and codesign aspects. Since its creation in 2005, it has gathered three leading conferences (international conference on compilers, architecture, and synthesis for embedded systems, cases;international conference on Hardware/Software Codesign and System synthesis, CODES+ISSS;and international conference on embedded Software, EMSOFT) along with several colocated events, to offer, to the attendees, a wide range of choices unveiling state-of-the-art embedded systems design and hardware/software architectures. © 2013 IEEE.

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