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embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Gutierrez-Galan, Daniel Pedro Jimenez-Fernandez, Juan Jimenez-Fernandez, Angel Tapiador-Morales, Ricardo Rios-Navarro, Antonio Linares-Barranco, Alejandro Univ Seville Seville Spain

ISBN: (纸本)9781450369244

Autonomous robots have become a very popular topic within the artificial intelligence field. These systems are able to perform difficult or risky tasks that could be dangerous when done by humans or trained animals. Vision is commonly considered the most relevant input sensor for autonomous robots and tracking systems. However, auditory information is also important in some specific situations where vision cannot provide any useful information when navigating. In this work, a spike-based model of the medial superior olive of the inner ear has been implemented in reconfigurable hardware for performing sound source localization in real time. Future works will focus on integrating this information with vision in order to achieve a fully bio-inspired autonomous tracking system.

关键词： Neuromorphic auditory sensor FPGA binaural sound localization real-time audio processing spike-based system

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Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization

Synterface: Efficient Chip-to-World Interfacing for Flow-Bas...

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作者： Sridhar, Aditya Ibrahim, Mohamed Chakrabarty, Krishnendu Duke Univ Dept Elect & Comp Engn 130 Hudson Hall Durham NC 27708 USA

Flow-based microfluidic biochips can be used to perform bioassays by manipulating a large number of on-chip valves. These biochips are increasingly used today for biomolecular recognition, single-cell screening, and point-of-care disease diagnostics, and design-automation solutions for flow-based microfluidics enable the mapping and optimization of bimolecular protocols and software-based valve control. However, a key problem that has not received adequate attention is chip-to-world interfacing, which requires the use of off-chip control equipment to provide control signals for the on-chip valves. This problem is exacerbated by the increase in the number of valves as chips get more complex. To address the interfacing problem, we present an efficient pin-count minimization (synthesis) problem, referred to as Synterface, which uses on-chip microfluidic logic gates and optimization based on concepts from linear algebra. We present results to show that Synterface significantly reduces pin-count and simplifies the external interface for flow-based microfluidics.

关键词： Microfluidic biochips chip-to-world interfacing synthesis logic gates

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Efficient Tracing Methodology Using Automata Processor

Efficient Tracing Methodology Using Automata Processor

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作者： Seo, Minjun Kurdahi, Fadi Univ Calif Irvine Ctr Embedded Cyber Phys Syst Irvine CA 92617 USA

Tracing or trace interface has been used in various ways to find system defects or bugs. As embedded systems are increasingly used in safety-critical applications, tracing can provide useful information during system execution at runtime. Non-intrusive tracing that does not affect system performance has become especially important, but unfortunately, the biggest obstacle to this approach was the vast amount of real-time trace data, making it challenging to address complex requirements with relatively limited hardware implementations. Automata processors can be programmed with a memory-like structure of automata and have a structure specific to streaming data, large capacity, and parallel processing functions. This paper promotes the idea of high-level system-on-chip monitoring using automata processors. We used a safety-critical pacemaker application in the experiments, described timed automata (TA)-based requirements, and tested intentionally injected 4,000 random failures. The TA model converted for Automata Processor to monitor system, correctness, and safety properties achieved 100% failure detection rate in the experiment, and the detected failure is reported as fast enough to allow enough extent for failure recovery.

关键词： Tracing tracing methodology runtime verification

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IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of embedded systems

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 1-22页

作者： Smirnov, Fedor Pourmohseni, Behnaz Glass, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Cauerstr 11 D-91058 Erlangen Germany Univ Ulm Albert Einstein Allee 11 D-89081 Ulm Germany

Design Space Exploration (DSE) techniques for complex embedded systems must cope with a huge variety of applications and target architectures as well as a wide spectrum of objectives and constraints. In particular, existing design automation approaches are either problem-independent, in that they do not exploit any knowledge about the optimization problem at hand, or are tailored to specific a priori assumptions about the problem and/or a specific set of design objectives. While the latter are only applicable within a very limited scope of design problems, the former may struggle to deliver high-quality solutions for problems with large design spaces and/or complex design objectives. As a remedy, we propose Importance-Guided Order Rearrangement (IGOR) as a novel approach for DSE of embedded systems. Instead of relying on an a priori problem knowledge, IGOR uses a machine-learning-inspired technique to dynamically analyze the importance of design decisions, i.e., the impact that these decisions-within the specific problem that is being optimized-have on the quality of explored problem solutions w.r.t. the given design objectives. Throughout the DSE, IGOR uses this information to guide the optimization towards the most promising regions of the design space. Experimental results for a variety of applications from different domains of embedded computing and for different optimization scenarios give evidence that the proposed approach is both scalable and adaptable, as it can be used for the optimization of systems described by several thousands constraints, where it outperforms both problem-specific and problem-independent optimization approaches and achieves e-dominance improvements of up to 95%.

关键词： Design space exploration constrained combinatorial problems multi-objective optimization embedded systems

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End-to-End Timing Analysis of Sporadic Cause-Effect Chains in Distributed systems

End-to-End Timing Analysis of Sporadic Cause-Effect Chains i...

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作者： Duerr, Marco Von Der Brueggen, Georg Chen, Kuan-Hsun Chen, Jian-Jia TU Dortmund Univ Dortmund Germany

A cause-effect chain is used to define the logical order of data dependent tasks, which is independent from the execution order of the jobs of the (periodic/sporadic) tasks. Analyzing the worst-case End-to-End timing behavior, associated to a cause-effect chain, is an important problem in embedded control systems. For example, the detailed timing properties of modern automotive systems are specified in the AUTOSAR Timing Extensions. In this paper, we present a formal End-to-End timing analysis for distributed systems. We consider the two most important End-to-End timing semantics, i.e., the button-to-action delay (termed as the maximum reaction time) and the worst-case data freshness (termed as the maximum data age). Our contribution is significant due to the consideration of the sporadic behavior of job activations, whilst the results in the literature have been mostly limited to periodic activations. The proof strategy shows the (previously unexplored) connection between the reaction time (data age, respectively) and immediate forward ( backward, respectively) job chains. Our analytical results dominate the state of the art for sporadic task activations in distributed systems and the evaluations show a clear improvement for synthesized task systems as well as for a real world automotive benchmark setting.

关键词： End-to-End timing analysis distributed systems sporadic cause-effect chains embedded control systems

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Deriving Equations from Sensor Data Using Dimensional Function synthesis

Deriving Equations from Sensor Data Using Dimensional Functi...

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作者： Wang, Youchao Willis, Sam Tsoutsouras, Vasileios Stanley-Marbell, Phillip Univ Cambridge 9 JJ Thomson Ave Cambridge CB3 0FA England

We present a new method for deriving functions that model the relationship between multiple signals in a physical system. The method, which we call dimensional function synthesis, applies to data streams where the dimensions of the signals are known. The method comprises two phases: a compile-time synthesis phase and a subsequent calibration using sensor data. We implement dimensional function synthesis and use the implementation to demonstrate efficiently summarizing multi-modal sensor data for two physical systems using 90 laboratory experiments and 10 000 synthetic idealized measurements. We evaluate the performance of the compile-time phase of dimensional function synthesis as well as the calibration phase overhead, inference latency, and accuracy of the models our method generates. The results show that our technique can generate models in less than 300 ms on average across all the physical systems we evaluated. When calibrated with sensor data, our models outperform traditional regression and neural network models in inference accuracy in all the cases we evaluated. In addition, our models perform better in training latency (over 8660x improvement) and required arithmetic operations in inference (over 34x improvement). These significant gains are largely the result of exploiting information on the physics of signals that has hitherto been ignored.

关键词： Machine learning dimensional analysis sensor data fusion

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Will My Program Break on This Faulty Processor?: Formal Analysis of Hardware Fault Activations in Concurrent embedded Software

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 1-21页

作者： Bajczi, Levente Voros, Andras Molnar, Vince Budapest Univ Technol & Econ Fault Tolerant Syst Res Grp Dept Measurement & Informat Syst POB 91 H-1521 Budapest Hungary MTA BME Lendulet Cyber Phys Syst Res Grp Budapest Hungary

Formal verification is approaching a point where it will be reliably applicable to embedded software. Even though formal verification can efficiently analyze multi-threaded applications, multi-core processors are often considered too dangerous to use in critical systems, despite the many benefits they can offer. One reason is the advanced memory consistency model of such CPUs. Nowadays, most software verifiers assume strict sequential consistency, which is also the naive view of programmers. Modernmulti-core processors, however, rarely guarantee this assumption by default. In addition, complex processor architectures may easily contain design faults. Thanks to the recent advances in hardware verification, these faults are increasingly visible and can be detected even in existing processors, giving an opportunity to compensate for the problem in software. In this paper, we propose a generic approach to consider inconsistent behavior of the hardware in the analysis of software. Our approach is based on formal methods and can be used to detect the activation of existing hardware faults on the application level and facilitate their mitigation in software. The approach relies heavily on recent results of model checking and hardware verification and offers new, integrative research directions. We propose a partial solution based on existing model checking tools to demonstrate feasibility and evaluate their performance in this context.

关键词： Fault analysis memory consistency model concurrent litmus test

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IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of embedded systems

IGOR, Get Me the Optimum! Prioritizing Important Design Deci...

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关键词： Design space exploration constrained combinatorial problems multi-objective optimization embedded systems

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Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs

Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI I...

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作者： Restuccia, Francesco Pagani, Marco Biondi, Alessandro Marinoni, Mauro Buttazzo, Giorgio Scuola Super Sant Anna Via Moruzzi 1 I-56127 Pisa Italy Scuola Super Sant Anna Area CNR Pisa Italy Univ Lille CRIStAL CNRS Cent LilleUMR 9189 Lille France

AMBA AXI is a popular bus protocol that is widely adopted as the medium to exchange data in field-programmable gate array system-on-chips (FPGA SoCs). The AXI protocol does not specify how conflicting transactions are arbitrated and hence the design of bus arbiters is left to the vendors that adopt AXI. Typically, a round-robin arbitration is implemented to ensure a fair access to the bus by the master nodes, as for the popular SoCs by Xilinx. This paper addresses a critical issue that can arise when adopting the AXI protocol under round-robin arbitration;specifically, in the presence of bus transactions with heterogeneous burst sizes. First, it is shown that a completely unfair bandwidth distribution can be achieved under some configurations, making possible to arbitrarily decrease the bus bandwidth of a target master node. This issue poses serious performance, safety, and security concerns. Second, a low-latency (one clock cycle) module named AXI burst equalizer (ABE) is proposed to restore fairness. Our investigations and proposals are supported by implementations and tests upon three modern SoCs. Experimental results are reported to confirm the existence of the issue and assess the effectiveness of the ABE with bus traffic generators and hardware accelerators from the Xilinx's IP library.

关键词： FPGA AXI BUS arbitration embedded systems

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High-Level synthesis of Approximate Designs under Real-Time Constraints

High-Level Synthesis of Approximate Designs under Real-Time ...

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作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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