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international conference on compilers, architecture and synthesis for embedded systems (cases)

作者： Serrano, Maria A. Melani, Alessandra Vargas, Roberto Marongiu, Andrea Bertogna, Marko Quinones, Eduardo Tech Univ Catalonia Barcelona Spain Barcelona Supercomp Barcelona Spain Scuola Super Sant Anna Pisa Italy Swiss Fed Inst Technol Zurich Switzerland Univ Modena & Reggio Emilia Modena Italy

ISBN: (纸本)9781467383202

OpenMP is increasingly being supported by the newest high-end embedded many-core processors. Despite the lack of any notion of real-time execution, the latest specification of OpenMP (v4.0) introduces a tasking model that resembles the way real-time embedded applications are modeled and designed, i.e., as a set of periodic task graphs. This makes OpenMP4 a convenient candidate to be adopted in future real-time systems. However, OpenMP4 incorporates as well features to guarantee backward compatibility with previous versions that limit its practical usability in real-time systems. The most notable example is the distinction between tied and untied tasks. Tied tasks force all parts of a task to be executed on the same thread that started the execution, whereas a suspended untied task is allowed to resume execution on a different thread. Moreover, tied tasks are forbidden to be scheduled in threads in which other non-descendant tied tasks are suspended. As a result, the execution model of tied tasks, which is the default model in OpenMP to simplify the coexistence with legacy constructs, clearly restricts the performance and has serious implications on the response time analysis of OpenMP4 applications, making difficult to adopt it in real-time environments. In this paper, we revisit OpenMP design choices, introducing timing predictability as a new and key metric of interest. Our first results confirm that even if tied tasks can be timing analyzed, the quality of the analysis is much worse than with untied tasks. We thus reason about the benefits of using untied tasks, deriving a response time analysis for this model, and so allowing OpenMP4 untied model to be applied to real-time systems.

关键词： embedded systems message passing open systems OpenMP4 tasking model backward compatibility high-end embedded many-core processors real-time systems response time analysis timing characterization Analytical models Force Programming Real-time systems Scheduling algorithms Synchronization real-time systems backward compatibility time series analysis Scheduling algorithms Religious Missions message passing ANALYSIS MODELS open systems embedded systems Programming Force Legal Executions THREADS

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Report on the 2023 embedded systems Week (ESWEEK)

IEEE Design and Test

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IEEE Design and Test 2024年第2期41卷 84-87页

作者： Hu, Xiaobo Sharon Girault, Alain Falk, Heiko University of Notre Dame Notre DameIN46556 United States Université Grenoble Alpes Inria Cnrs Grenoble Inp Grenoble38000 France Tu Hamburg Hamburg21073 Germany

embedded systems Week (ESWEEK) is the premier worldwide event covering all aspects of embedded systems, encompassing software, hardware, and codesign aspects. Since its creation in 2005, it has gathered three leading conferences (international conference on compilers, architecture, and synthesis for embedded systems, cases;international conference on Hardware/Software Codesign and System synthesis, CODES+ISSS;and international conference on embedded Software, EMSOFT) along with several colocated events, to offer, to the attendees, a wide range of choices unveiling state-of-the-art embedded systems design and hardware/software architectures. © 2013 IEEE.

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The 2019 embedded systems Week (ESWEEK)

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2020年第1期37卷 100-101页

作者： Eles, Petru Mitra, Tulika Linkoping Univ Linkoping Sweden Natl Univ Singapore Dept Comp Sci Singapore 117417 Singapore

embedded systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems. By bringing together three leading conferences [the international conference on compilers, architecture, and synthesis for embedded systems (cases), the international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS), and the international conference on embedded Software (EMSOFT)], a special Internet of Medical Things (IoMT) day, a symposium [the international Symposium on Networks-on-Chip (NOCS)], and hottopic workshops and tutorials, ESWEEK presents the attendees with a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.

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A new method for compiling schizophrenic synchronous programs 2

A new method for compiling schizophrenic synchronous program...

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Schneider, K. Wenz, M. University of Karlsruhe Institute for Computer Design and Fault Tolerance Germany

ISBN: (纸本)1581133995

Synchronous programming languages have proved to be advantageous for designing software and hardware for embedded systems. Despite their clear semantics, their compilation is remarkably difficult: In particular, one has to take care of potential schizophrenia problems. Although these problems are correctly translated with existing compilers, there is still a need for clean algorithms. In this paper, we present the first solution to eliminate schizophrenia problems by program transformations. These transformations are used for compilation, but also for increasing the readability of programs. Copyright 2001 ACM.

关键词： embedded systems

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Dances with multimedia: embedded video codec design

Dances with multimedia: Embedded video codec design

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Chen, Liang-Gee Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)1595935436

The rapid progress of semiconductor technology enables the rising and flourishing of digital multimedia. Fancy terms such as ubiquitous multimedia, mobile multimedia, embedded video, etc., and hot products such as iPod, Camera phone, Portable Multimedia Player, etc., mark our colorful life, now and future. In this talk, I attempt to review the past and present developments of video coding, and to explore some future trends. Then, this talk will discuss the challenging optimization tasks that video codec architects have to face under the stringent time-to-market pressure for applications ranged from low-power mobile multimedia to high definition video. Design issues, optimization techniques, and case studies are presented. What we have learned is that multimedia SOC design is a beautiful but challenging dance among video codec HW/SW designers, transistors and video bits.

关键词： Multimedia systems

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Methods for power optimization in distributed embedded systems with real-time requirements

Methods for power optimization in distributed embedded syste...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Racu, Razvan Hamann, Arne Ernst, Rolf Mochocki, Bren Hu, Xiaobo Sharon IDA Technical University of Braunschweig D-38106 Braunschweig Germany Department of CSE University of Notre Dame Notre Dame IN 46556 United States

ISBN: (纸本)1595935436

Dynamic voltagescaling and sleep state control have been shown to be extremely effective in reducing energy consumption in CMOS circuits. Though plenty of research papers have studied the application of these techniques in real-time embedded system design through intelligent task and/or voltage scheduling, most of these results are limited to relatively simple real-time application models. In this paper, a comprehensive real-time application model including periodic, sporadic and bursty tasks as well as distributed real-time constraints such as end-to-end delays is considered. Two methods are presented for reducing energy consumption while satisfying complex real-time constraints for this model. Experimental results show that the methods achieve significant energy savings without violating any deadlines. Copyright 2006 ACM.

关键词： embedded systems

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Cycle-time aware architecture synthesis of custom hardware accelerators

Cycle-time aware architecture synthesis of custom hardware a...

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2002 international conference on compilers, architecture, and synthesis for embedded systems, cases '02

作者： Sivaraman, Mukund Aditya, Shail Hewlett-Packard Labs. MS 1166 1501 Page Mill Road Palo Alto CA 94304 United States

ISBN: (纸本)1581135750

We present the cycle-time aware architecture synthesis methodology used in PICO-NPA that automatically synthesizes minimal cost RT-level designs from high-level specifications to meet a given cycle-time. This allows subsequent physical synthesis to succeed on first pass with predictable performance. The core of the methodology is a static timing analysis engine that is used at multiple levels - program-level, architecture-level and RT-level - in order to identify, schedule and validate useful operator chains that are incorporated into the design automatically. We present architecture synthesis results for several embedded applications and evaluate the benefits of this technique. Copyright 2002 ACM.

关键词： High level synthesis

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Compiler optimization of embedded applications for an adaptive SoC architecture

Compiler optimization of embedded applications for an adapti...

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Hardnett, Charles R. Palem, Krishna V. Chobe, Yogesh Spelman College Computer Science Department Atlanta GA 30314 United States Center for Research on Embedded Systems and Technology Georgia Institute of Technology Atlanta GA 30308 United States

ISBN: (纸本)1595935436

Adaptive Explicitly Parallel Instruction Computing (AEPIC) is a stylized form of a reconfigurable system-on-a-chip that is designed to enable compiler control of reconfigurable resources. In this paper, and for the first time, we validate the viability of automating two key optimizations proposed in the AEPIC compilation framework: configuration allocation and configuration scheduling. The AEPIC architecture is comprised of an Explicitly Parallel Instruction Computing (EPIC) core coupled with an adaptive fabric and architectural features to support dynamic management of the fabric. We show that this approach to compiler-centric hardware customization, originally proposed by Palem, Talla, Devaney and Wong ([26],[27]), yields speedups with factors from 150% to over 600% for embedded applications, when compared with general purpose and digital signal processor solutions. We also provide a normalized cost analysis for our performance gains, where the normalization is based on the area of silicon required. In addition, we provide an analysis of the AEPIC architectural space, where we identify the "sweet-spot" of performance on the AEPIC architecture by examining the performance across benchmarks and computational resource configurations. Finally, we have a preliminary result for how our compiler-based approach impacts productivity metrics in the development of ardware/software partitioned custom solutions. Our implementation and validation platform is based on the well-known TRIMARAN optimizing compiler infrastructure [13]. Copyright 2006 ACM.

关键词： Program compilers

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Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems

Memory and architecture exploration with thread shifting for...

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Kiemb, Mary Choi, Kiyoung School of Electrical Engineering and Computer Science Seoul National University San 56-1 Shillim-dong Gwanak-gu Seoul Korea Republic of

ISBN: (纸本)1581138903

In embedded multithreaded architectures, the performance enhancement relative to the base single-threaded architecture is highly dependent on the characteristics of the application and memory configuration, When the application is well parallelized, the multithreading performance may be good even with a small cache since the memory access latency can be hidden. However, if there are complicated dependencies between threads, they cause frequent cache conflicts, so the performance may not be improved. For that reason, not only processor architecture but also memory configuration should be customized to get an optimal solution of an embedded multithreaded system. We suggest a design space exploration algorithm, which considers both memory configuration and multithreaded architecture and a thread shifting technique, which shifts threads in compile time to minimize cache conflict. Copyright 2004 ACM.

关键词： embedded systems

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A case study of multi-threading in the embedded space

A case study of multi-threading in the embedded space

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cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Hoover, Greg Brewer, Forrest Sherwood, Timothy University of California Santa Barbara Engineering I Santa Barbara CA 93106

ISBN: (纸本)1595935436

The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net processors are tasked with the job of handling a disparate set of interrupt driven activity, from networks to timers to the sensors *** this paper,we demonstrate the advantages of a tiny multi-threaded microcontroller design which targets embedded applications that need to respond to events at high speed. While multi-threading is typically used to improve resource utilization, in the embedded space it can provide zero-cycle context switching and interrupt service threads (IST), enabling complex programmable control in latency constrained environments. To explore the advantages of multi-threading on these embedded problems, we have implemented in hardware a family of controllers supporting eight dynamically interleaved threads and executing the AVR instruction set. This allows us to carefully quantify the effects of threading on interrupt latency, code size, overall processor throughput, cycle time, and design area for complete designs with different numbers of threads. Copyright 2006 ACM.

关键词： embedded systems

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