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2016 international conference on compilers, architectures and synthesis for embedded systems, cases 2016

ISBN: (纸本)9781450344821

The proceedings contain 21 papers. The topics discussed include: ILP-based modulo scheduling for high-level synthesis;handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip;theoretical foundations for workload modeling with implications on power optimization;thermal-driven resource allocation and application mapping for complex many core systems;runtime management of adaptive MPSoCs for graceful degradation;towards the design of fault-tolerant mixed-criticality systems on multicores;COMET: communication-optimised multi-threaded error-detection technique;neural network transformation and co-design under neuromorphic hardware constraints;cambricon: an instruction set architecture for neural networks;RRAM based learning acceleration;a real-time digital-microfluidic platform for epigenetics;LOCUS: low-power customizable many-core architecture for wearables;D-PUF: an intrinsically reconfigurable DRAM PUF for device authentication in embedded systems;hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous Manycore platforms;matrix multiplication beyond auto-tuning: rewrite-based GPU code generation;and a jump-target identification method for multi-architecture static binary translation.

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Optimized FPGA Implementation of a Compute-Intensive Oil Reservoir Simulation Algorithm 19th

Optimized FPGA Implementation of a Compute-Intensive Oil Res...

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19th international conference on embedded Computer systems: architectures, Modeling, and Simulation (SAMOS)

作者： Ioannou, Aggelos D. Malakonakis, Pavlos Georgopoulos, Konstantinos Papaefstathiou, Ioannis Dollas, Apostolos Mavroidis, Iakovos Tech Univ Crete Sch Elect & Comp Engn Khania Greece Telecommun Syst Inst Campus Kounoupidiana Khania Greece Aristotle Univ Thessaloniki Sch Elect & Comp Engn Thesssaloniki Greece Synelixis Solut Ltd 10 Farmakidou St Chalkida 34100 Greece

ISBN: (纸本)9783030275624;9783030275617

Modern-day High Performance Computing (HPC) trends are shifting towards exascale performance figures in order to satisfy the needs of many compute-intensive and power-hungry applications. Hence, the European-funded ECOSCALE project introduces a highly innovative architecture, which spreads the workload among a number of independent and concurrently-operating conventional (CPU) as well as reconfigurable (FPGA) processing elements that execute OpenCL cores whilst significantly minimizing the need for data transfers. The accelerator cores implemented on the ECOSCALE platform correspond to the project use cases and have been the source of a meticulous exploration process for optimal performance results such as execution time. This paper focuses on performance and power optimizations of the Michelsen algorithm. This algorithm is an efficient calculator of the Rachford-Rice equation, which is extensively used in the field of oil Reservoir Simulation (RS). The algorithm was first optimized manually through Vivado HLS and, subsequently, using a Design Space Exploration (DSE) tool we developed in [1]. Here we present up-to-date optimization results based on the latest FPGA ECOSCALE platform in order to reveal bottlenecks, saturation points and design alternatives. The measurements are performed on real data and the evaluation results register significant gains in calculation times over conventional CPU platforms;an achievement that carries added value considering the significantly reduced power consumption costs commonly associated with reconfigurable hardware.

关键词： High-Level synthesis Accelerator architectures OpenCL Exascale

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Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 54-54页

作者： Sridhar, Aditya Ibrahim, Mohamed Chakrabarty, Krishnendu Duke Univ Dept Elect & Comp Engn 130 Hudson Hall Durham NC 27708 USA

Flow-based microfluidic biochips can be used to perform bioassays by manipulating a large number of on-chip valves. These biochips are increasingly used today for biomolecular recognition, single-cell screening, and point-of-care disease diagnostics, and design-automation solutions for flow-based microfluidics enable the mapping and optimization of bimolecular protocols and software-based valve control. However, a key problem that has not received adequate attention is chip-to-world interfacing, which requires the use of off-chip control equipment to provide control signals for the on-chip valves. This problem is exacerbated by the increase in the number of valves as chips get more complex. To address the interfacing problem, we present an efficient pin-count minimization (synthesis) problem, referred to as Synterface, which uses on-chip microfluidic logic gates and optimization based on concepts from linear algebra. We present results to show that Synterface significantly reduces pin-count and simplifies the external interface for flow-based microfluidics.

关键词： Microfluidic biochips chip-to-world interfacing synthesis logic gates

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Efficient Tracing Methodology Using Automata Processor

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 80-80页

作者： Seo, Minjun Kurdahi, Fadi Univ Calif Irvine Ctr Embedded Cyber Phys Syst Irvine CA 92617 USA

Tracing or trace interface has been used in various ways to find system defects or bugs. As embedded systems are increasingly used in safety-critical applications, tracing can provide useful information during system execution at runtime. Non-intrusive tracing that does not affect system performance has become especially important, but unfortunately, the biggest obstacle to this approach was the vast amount of real-time trace data, making it challenging to address complex requirements with relatively limited hardware implementations. Automata processors can be programmed with a memory-like structure of automata and have a structure specific to streaming data, large capacity, and parallel processing functions. This paper promotes the idea of high-level system-on-chip monitoring using automata processors. We used a safety-critical pacemaker application in the experiments, described timed automata (TA)-based requirements, and tested intentionally injected 4,000 random failures. The TA model converted for Automata Processor to monitor system, correctness, and safety properties achieved 100% failure detection rate in the experiment, and the detected failure is reported as fast enough to allow enough extent for failure recovery.

关键词： Tracing tracing methodology runtime verification

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Deriving Equations from Sensor Data Using Dimensional Function synthesis

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 84-84页

作者： Wang, Youchao Willis, Sam Tsoutsouras, Vasileios Stanley-Marbell, Phillip Univ Cambridge 9 JJ Thomson Ave Cambridge CB3 0FA England

We present a new method for deriving functions that model the relationship between multiple signals in a physical system. The method, which we call dimensional function synthesis, applies to data streams where the dimensions of the signals are known. The method comprises two phases: a compile-time synthesis phase and a subsequent calibration using sensor data. We implement dimensional function synthesis and use the implementation to demonstrate efficiently summarizing multi-modal sensor data for two physical systems using 90 laboratory experiments and 10 000 synthetic idealized measurements. We evaluate the performance of the compile-time phase of dimensional function synthesis as well as the calibration phase overhead, inference latency, and accuracy of the models our method generates. The results show that our technique can generate models in less than 300 ms on average across all the physical systems we evaluated. When calibrated with sensor data, our models outperform traditional regression and neural network models in inference accuracy in all the cases we evaluated. In addition, our models perform better in training latency (over 8660x improvement) and required arithmetic operations in inference (over 34x improvement). These significant gains are largely the result of exploiting information on the physics of signals that has hitherto been ignored.

关键词： Machine learning dimensional analysis sensor data fusion

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End-to-End Timing Analysis of Sporadic Cause-Effect Chains in Distributed systems

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 58-58页

作者： Duerr, Marco Von Der Brueggen, Georg Chen, Kuan-Hsun Chen, Jian-Jia TU Dortmund Univ Dortmund Germany

A cause-effect chain is used to define the logical order of data dependent tasks, which is independent from the execution order of the jobs of the (periodic/sporadic) tasks. Analyzing the worst-case End-to-End timing behavior, associated to a cause-effect chain, is an important problem in embedded control systems. For example, the detailed timing properties of modern automotive systems are specified in the AUTOSAR Timing Extensions. In this paper, we present a formal End-to-End timing analysis for distributed systems. We consider the two most important End-to-End timing semantics, i.e., the button-to-action delay (termed as the maximum reaction time) and the worst-case data freshness (termed as the maximum data age). Our contribution is significant due to the consideration of the sporadic behavior of job activations, whilst the results in the literature have been mostly limited to periodic activations. The proof strategy shows the (previously unexplored) connection between the reaction time (data age, respectively) and immediate forward ( backward, respectively) job chains. Our analytical results dominate the state of the art for sporadic task activations in distributed systems and the evaluations show a clear improvement for synthesized task systems as well as for a real world automotive benchmark setting.

关键词： End-to-End timing analysis distributed systems sporadic cause-effect chains embedded control systems

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High-Level synthesis of Approximate Designs under Real-Time Constraints

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 59-59页

作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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SWARAM: Portable Energy and Cost Efficient embedded System for Genomic Processing

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 61-61页

作者： Mohanty, Ram Prasad Gamaarachchi, Hasindu Lambert, Andrew Parameswaran, Sri Univ New South Wales Canberra ACT 2612 Australia Univ New South Wales Sydney NSW 2052 Australia

Treatment of patients using high-quality precision medicine requires a thorough understanding of the genetic composition of a patient. Ideally, the identification of unique variations in an individual's genome is needed for specifying the necessary treatment. Variant calling workflow is a pipeline of tools, integrating state of the art software systems aimed at alignment, sorting and variant calling for the whole genome sequencing (WGS) data. This pipeline is utilized for identifying unique variations in an individual's genome (compared to a reference genome). Currently, such a workflow is implemented on high-performance computers (with additional GPUs or FPGAs) or in cloud computers. Such systems are large, have a high cost, and rely on the internet for genome data transfer which makes the system unusable in remote locations unequipped with internet connectivity. It further raises privacy concerns due to processing being carried out in a different facility. To overcome such limitations, in this paper, for the first time, we present a cost-efficient, offline, scalable, portable, and energy-efficient computing system named SWARAM for variant calling workflow processing. The system uses novel architecture and algorithms to match against partial reference genomes to exploit smaller memory sizes which are typically available in tiny processing systems. Extensive tests on a standard benchmark data-set (NA12878 Illumina platinum genome) confirm that the time consumed for the data transfer and completing variant calling workflow on SWARAM was competitive to that of a 32-core Intel Xeon server with similar accuracy, but costs less than a fifth, and consumes less than 40% of the energy of the server system. The original scripts and code we developed for executing the variant calling workflow on SWARAM are available in the associated Github repository https://***/Rammohanty/swaram.

关键词： Genome alignment variant calling genetic analysis embedded system ARM DNA analysis energy efficient system portable genome analysis

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cases 2018 Message from Program Chairs

2018 International Conference on Compilers, Architecture and...

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2018 international conference on compilers, architecture and synthesis for embedded systems, cases 2018 2018年

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Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs

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ACM TRANSACTIONS ON embedded COMPUTING systems 2019年第5期18卷 51-51页

作者： Restuccia, Francesco Pagani, Marco Biondi, Alessandro Marinoni, Mauro Buttazzo, Giorgio Scuola Super Sant Anna Via Moruzzi 1 I-56127 Pisa Italy Scuola Super Sant Anna Area CNR Pisa Italy Univ Lille CRIStAL CNRS Cent LilleUMR 9189 Lille France

AMBA AXI is a popular bus protocol that is widely adopted as the medium to exchange data in field-programmable gate array system-on-chips (FPGA SoCs). The AXI protocol does not specify how conflicting transactions are arbitrated and hence the design of bus arbiters is left to the vendors that adopt AXI. Typically, a round-robin arbitration is implemented to ensure a fair access to the bus by the master nodes, as for the popular SoCs by Xilinx. This paper addresses a critical issue that can arise when adopting the AXI protocol under round-robin arbitration;specifically, in the presence of bus transactions with heterogeneous burst sizes. First, it is shown that a completely unfair bandwidth distribution can be achieved under some configurations, making possible to arbitrarily decrease the bus bandwidth of a target master node. This issue poses serious performance, safety, and security concerns. Second, a low-latency (one clock cycle) module named AXI burst equalizer (ABE) is proposed to restore fairness. Our investigations and proposals are supported by implementations and tests upon three modern SoCs. Experimental results are reported to confirm the existence of the issue and assess the effectiveness of the ABE with bus traffic generators and hardware accelerators from the Xilinx's IP library.

关键词： FPGA AXI BUS arbitration embedded systems

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