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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是71-80 订阅

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Work-in-Progress: PowerMonitor: Design Pattern for Modelling Energy-Aware embedded systems

Work-in-Progress: PowerMonitor: Design Pattern for Modelling...

引用

embedded systems Week / Int Conf on compilers, architecture, and synthesis for embedded systems (cases) / international conference on Hardware/Software Codesign and System synthesis (CODES+ISSS) / Int Conf on embedded Software (EMSOFT)

作者： Uelschen, Michael Schaarschmidt, Marco Fuhrmann, Christian Westerkamp, Clemens Univ Appl Sci Osnabruck Fac Engn & Comp Sci Osnabruck Germany

ISBN: (纸本)9781450369244

This paper introduces a new software design pattern that can be applied to embedded systems. The pattern enables the application to access the peripheral devices under defined power conditions and allows to implement a fine-grained and energy-efficient strategy on using functional units of the microcontroller. The approach considers power consumption properties of the CPU itself as well as properties of external peripheral devices like connected sensors and actuators.

关键词： Software architecture Design Patterns embedded systems Energy efficiency Template Meta Programming

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Adaptive and flexible dictionary code compression for embedded applications

Adaptive and flexible dictionary code compression for embedd...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Brorsson, Mats Collin, Mikael KTH ICT Dept. of Electronic Computer and Software Systems Electrum 229 SE-164 40 Kista Sweden

ISBN: (纸本)1595935436

Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions. We present a new view of dictionary code compression for moderately high-performance processors for embedded applications. Previous work with dictionary code compression has shown decent performance and energy savings results which we verify with our own measurement that are more thorough than previously published. We also augment previous work with a more thorough analysis on the effects of cache and line size changes. In addition, we introduce the concept of aggregated profiling to allow for two or more programs to share the same dictionary contents. Finally, we also introduce dynamic dictionaries where the dictionary contents is considered to be part of the context of a process and show that the performance overhead of reloading the dictionary contents on a context switch is negligible while on the same time we can save considerable energy with a more specialized dictionary contents. Copyright 2006 ACM.

关键词： Codes (symbols)

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Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems

Memory and architecture exploration with thread shifting for...

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cases 2004: international conference on compilers, architecture, and synthesis for embedded systems

作者： Kiemb, Mary Choi, Kiyoung School of Electrical Engineering and Computer Science Seoul National University San 56-1 Shillim-dong Gwanak-gu Seoul Korea Republic of

ISBN: (纸本)1581138903

In embedded multithreaded architectures, the performance enhancement relative to the base single-threaded architecture is highly dependent on the characteristics of the application and memory configuration, When the application is well parallelized, the multithreading performance may be good even with a small cache since the memory access latency can be hidden. However, if there are complicated dependencies between threads, they cause frequent cache conflicts, so the performance may not be improved. For that reason, not only processor architecture but also memory configuration should be customized to get an optimal solution of an embedded multithreaded system. We suggest a design space exploration algorithm, which considers both memory configuration and multithreaded architecture and a thread shifting technique, which shifts threads in compile time to minimize cache conflict. Copyright 2004 ACM.

关键词： embedded systems

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Compiler optimization of embedded applications for an adaptive SoC architecture

Compiler optimization of embedded applications for an adapti...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Hardnett, Charles R. Palem, Krishna V. Chobe, Yogesh Spelman College Computer Science Department Atlanta GA 30314 United States Center for Research on Embedded Systems and Technology Georgia Institute of Technology Atlanta GA 30308 United States

ISBN: (纸本)1595935436

Adaptive Explicitly Parallel Instruction Computing (AEPIC) is a stylized form of a reconfigurable system-on-a-chip that is designed to enable compiler control of reconfigurable resources. In this paper, and for the first time, we validate the viability of automating two key optimizations proposed in the AEPIC compilation framework: configuration allocation and configuration scheduling. The AEPIC architecture is comprised of an Explicitly Parallel Instruction Computing (EPIC) core coupled with an adaptive fabric and architectural features to support dynamic management of the fabric. We show that this approach to compiler-centric hardware customization, originally proposed by Palem, Talla, Devaney and Wong ([26],[27]), yields speedups with factors from 150% to over 600% for embedded applications, when compared with general purpose and digital signal processor solutions. We also provide a normalized cost analysis for our performance gains, where the normalization is based on the area of silicon required. In addition, we provide an analysis of the AEPIC architectural space, where we identify the "sweet-spot" of performance on the AEPIC architecture by examining the performance across benchmarks and computational resource configurations. Finally, we have a preliminary result for how our compiler-based approach impacts productivity metrics in the development of ardware/software partitioned custom solutions. Our implementation and validation platform is based on the well-known TRIMARAN optimizing compiler infrastructure [13]. Copyright 2006 ACM.

关键词： Program compilers

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Moving from embedded systems to embedded computing

Moving from embedded systems to embedded computing

引用

cases 2003: international conference on compilers, architecture, and synthesis for embedded systems

作者： Fisher, Joseph A. Hewlett Packard Labs United States

ISBN: (纸本)1581136765

In the middle of the last decade, there was a large gulf between embedded systems and general-purpose computing. Most researchers and advanced developers in general-purpose computing thought naively that real-time considerations added a little twist, but after that it was mostly a matter of size. Their impression was that embedded systems were just like general-purpose systems, but smaller. At the same time, those working in embedded systems were usually insufficiently aware of progress in computing that could be applied to what they were doing, and felt that theirs was a discipline apart. This talk address lessons my colleagues and I learned while working in embedded systems over the past decade. Many of these lessons are reflections of the coming fundamental shifts in embedded systems. The changes caused by higher silicon densities and greater performance are pulling embedded systems towards general-purpose computing, and the embedded field can no longer afford to ignore progress in architecture, compilers and general-purpose operating systems and tools. At the same time, there is a unique flavor to embedded, and some aspects of this different flavor will survive the changes. I'll discuss this shift in relation to questions of customization, special-purpose functionality in hardware vs. software, and similar topics.

关键词： embedded systems

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Automated compile-time and run-time techniques to increase usable memory in MMU-less embedded systems

Automated compile-time and run-time techniques to increase u...

引用

cases 2006: international conference on compilers, architecture and synthesis for embedded systems

作者： Bai, Lan S. Yang, Lei Dick, Robert P. Electrical Engineering and Computer Science Department Northwestern University 2145 Sheridan Road Evanston IL 60208

ISBN: (纸本)1595935436

Random access memory (RAM) is tightly-constrained in many embedded systems. This is especially true for the least expensive, lowest-power embedded systems, such as sensor network nodes and portable consumer electronics. The most widely-used sensor network nodes have only 4-10 KB of RAM and do not contain memory management units (MMUs). It is very difficult to implement increasingly complex applications under such tight memory constraints. Nonetheless, price and power consumption constraints make it unlikely that increases in RAM in these systems will keep pace with the requirements of *** propose the use of automated compile-time and run-time techniques to increase the amount of usable memory in MMU-less embedded systems. The proposed techniques do not increase hardware cost, and are designed to require few or no changes to existing applications. We have developed a fast compression algorithm well suited to this application, as well as run-time library routines and compiler transformations to control and optimize the automatic migration of application data between compressed and uncompressed memory regions. These techniques were experimentally evaluated on Crossbow TelosB sensor network nodes running a number of data collection and signal processing applications. The results indicate that available memory can be increased by up to 50% with less than 10% performance degradation for most benchmarks. Copyright 2006 ACM.

关键词： Program compilers

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Dynamic scheduling of concurrent tasks with cost performance trade-off

Dynamic scheduling of concurrent tasks with cost performance...

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Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Yang, Peng Desmet, Dirk Catthoor, Francky Verkest, Diederik IMEC Kapeldreef 75 Leuven Belgium

ISBN: (纸本)1581133383

This paper addresses the run time task scheduling problem on a multiprocessor platform for embedded systems, where energy consumption is a major concern, as opposed to the traditional static and dynamic scheduling approaches. Our approach intends to combine the advantages of the low run time complexity of the static scheduler and the flexibility of the dynamic scheduler and to optimize the system energy consumption at run time based on precomputed cost-performance Pareto curves. We have applied our method to an ADSL modem application and the result shows the effectiveness of our method.

关键词： embedded systems

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Iterative procedural abstraction for code size reduction

Iterative procedural abstraction for code size reduction

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2002 international conference on compilers, architecture, and synthesis for embedded systems, cases '02

作者： Kim, Dae-Hwan Lee, Hyuk Jae School of Electrical Engineering and Computer Science Seoul National University San 56-1 Shilim-Dong Kuanak-Gu Seoul Korea Republic of

ISBN: (纸本)1581135750

For code size reduction, an iterative approach for procedural abstraction is proposed. Contrary to the previous approaches, the proposed technique iterates saving estimation and procedural abstraction repeatedly based on estimated global saving. The global saving is dynamically re-calculated in each iteration. Experimental results show that the proposed approach achieves additional code size reduction on an average of 14.9% in 8 benchmarks when compared to the previous conventional approach. Copyright 2002 ACM.

关键词： embedded systems

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A first-step towards an architecture tuning methodology for low power

A first-step towards an architecture tuning methodology for ...

引用

Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (cases 2000)

作者： Stitt, Greg Vahid, Frank Givargis, Tony Lysecky, Roman Dept. of Comp. Sci. and Engineering University of California Riverside CA United States Center for Embedded Computer Systems UC Irvine Irvine CA United States

ISBN: (纸本)1581133383

We describe an automated environment to assist a system-on-a-chip designer to tune a microprocessor core to a particular application program that will run on the microprocessor, and vice-versa, with the goal of reducing embedded system power consumption. We limit such tuning to modifications that do not change the microprocessor instruction set, thus avoiding the large costs that would come with such a change. Our tuning environment for the 8051 microcontroller is freely-available on the web.

关键词： systems analysis

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Exposing non-standard architectures to embedded software using compile-time virtualisation

Exposing non-standard architectures to embedded software usi...

引用

embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Gray, Ian Audsley, Neil C. Department of Computer Science University of York York United Kingdom

ISBN: (纸本)9781605586267

The architectures of embedded systems are often application-specific, containing multiple heterogenous cores, non-uniform memory, on-chip networks and custom hardware elements (e.g. DSP cores). Standard programming languages do not use these many of these features natively because they assume a traditional single processor and a single logical address space abstraction that hides these architectural details. This paper describes Compile-Time Virtualisation, a technique which uses a virtualisation layer to map software onto the target architecture whilst allowing the programmer to control the virtualisation mappings in order to effectively exploit custom architectures. Copyright 2009 ACM.

关键词： Virtualization

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