检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

51 篇 会议

馆藏范围

51 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

39 篇 工学
- 39 篇 材料科学与工程（可...
- 13 篇 电气工程
35 篇 理学
- 35 篇 物理学
4 篇 医学
- 4 篇 临床医学

主题

8 篇 etching
8 篇 plasma etching
6 篇 etch
5 篇 optical lithogra...
4 篇 plasma
4 篇 cfet
3 篇 semiconducting w...
3 篇 ler
3 篇 line width rough...
3 篇 silicon
3 篇 lithography
3 篇 high aspect rati...
3 篇 sadp
3 篇 back end of line
3 篇 euv
3 篇 nanosheet
2 篇 metals
2 篇 gaa
2 篇 photomasks
2 篇 electrical yield...

机构

6 篇 imec kapeldreef ...
5 篇 imec kapeldreef ...
4 篇 america llc tel ...
3 篇 chinese acad sci...
2 篇 sandbox semicond...
2 篇 tokyo electron l...
2 篇 univ chinese aca...
1 篇 cea leti 17 rue ...
1 篇 stmicroelectroni...
1 篇 cea leti 17 rue ...
1 篇 univ grenoble al...
1 篇 ibm corp tj wats...
1 篇 arkema france f-...
1 篇 ibm res semicond...
1 篇 synopsys inc 675...
1 篇 coventor 3 ave q...
1 篇 univ bordeaux en...
1 篇 imec b-3001 leuv...
1 篇 ltm cnrs 17 ave ...
1 篇 changxin memory ...

作者

7 篇 lazzarino f.
4 篇 ko akiteru
4 篇 wei yayi
4 篇 raley angelique
4 篇 chen rui
4 篇 biolsi peter
4 篇 barnola s.
4 篇 shao hua
3 篇 li junjie
3 篇 kumar kaushik
3 篇 demuynck s.
3 篇 chan b. t.
3 篇 mannaert g.
3 篇 mohanty nihar
3 篇 horiguchi n.
3 篇 tiron r.
3 篇 dupuy e.
2 篇 gupta a.
2 篇 barros p. piment...
2 篇 chopra meghali j...

语言

51 篇 英文

检索条件"任意字段=Conference on Advanced Etch Technology and Process Integration for Nanopatterning XIII"

共 51 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

advanced etch technology and process integration for nanopatterning xiii

Advanced Etch Technology and Process Integration for Nanopat...

引用

advanced etch technology and process integration for nanopatterning xiii 2024

ISBN: (纸本)9781510672222

The proceedings contain 25 papers. The topics discussed include: metalens manufacturing complexities and costs;confinement-dependent wet etching kinetics in Si nanochannels;extreme UV self-aligned double patterning process optimization for BEOL interconnections on 3nm nodes and beyond;etching of iridium thin films in chlorine- and fluorine-based inductively coupled plasmas;in-depth discussion on pitch doubling flow CpK improvement through process integration;kinetic simulations of low-temperature plasmas used for plasma processing;new oxidants for thermal atomic layer etching of Cu;development of ALD precursors for low resistivity Zr, Hf, and Nb nitride films;life cycle assessment of etching processes for FDSOI transistors technologies;and active area patterning for CFET – nanosheet etch.

关键词：

来源：评论

学校读者我要写书评

暂无评论

In-depth discussion on pitch doubling flow CpK improvement through process integration 13

In-depth discussion on pitch doubling flow CpK improvement t...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Liu, Zhao Han, Baodong Superstring Acad Memory Technol Beijing Beijing Peoples R China

ISBN: (纸本)9781510672239;9781510672222

Self-aligned double patterning scheme is the dominant technique which is widely adopted in semiconductor industry to achieve finer patterns before extreme ultraviolet (EUV) lithography volume production is available. The critical dimension (CD) for the key structures fabricated from SADP flow, normally referred to as Bitline (BL) or Wordline (WL), is crucial to enable the microcircuitry to operate properly. Therefore, the CDs' precise control receives substantial attention as a key indicator to demonstrate the manufacturing process capability in quality management. This paper presents an in-depth analysis on BL CDs' variation control from SADP scheme, followed by several applicable approaches for process capability improvement across multiple modules through conceptual and experimental illustration, which could serve as a guideline for semiconductor manufacturing industry.

关键词： SADP EUV pitch SPC process capability index

来源：评论

学校读者我要写书评

暂无评论

Green Chemistry for SiN etch 13

Green Chemistry for SiN Etch

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Stafford, Nathan Jennings, Colin Biltek, Scott Phong Nguyen Yao, Yichen Amer Air Liquide Inc 200 GBC Dr Newark DE 19702 USA

ISBN: (纸本)9781510672239;9781510672222

Over the past few years, numerous countries and semiconductor manufacturing entities have unveiled their commitments to achieving net-zero carbon emissions by 2050 or even sooner. When it comes to manufacturing chips, plasma etch processes contribute significantly to emissions, especially in dielectric etching. These processes typically involve the use of high global warming potential (GWP) fluorocarbon gasses like CHF3, CF4, and CH2F2. Air Liquide's research and development (R&D) endeavors have led to the creation of multiple alternative etch chemistries for SiN and SiO2 etching applications that boast remarkably low GWPs. Despite strides in developing these alternative chemistries, accurately forecasting the gases emitted post-plasma remains elusive. The complexities inherent in the breakdown and recombination processes within the plasma make it challenging to predict the specific emissions, regardless of whether the gas introduced into the plasma etch chamber carries a high or low GWP. This research showcases the utilization of Fourier Transform Infrared Spectroscopy (FTIR) to analyze and measure the emission gas stream from the plasma etch chamber. Moreover, the innovative chemistries developed by Air Liquide have exhibited enhanced etch performance while resulting in lower CO2 equivalent emissions compared to the current baseline in dielectric etching

关键词： Emissions GWP etch

来源：评论

学校读者我要写书评

暂无评论

process Optimization of MP18 Semi-Damascene Interconnects with Fully Self-Aligned Vias at Sub-2nm Nodes 13

Process Optimization of MP18 Semi-Damascene Interconnects wi...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Soussou, A. Marti, G. Tokei, Zs. Park, S. Vincent, B. Coventor 3 Ave Quebec F-91140 Villebon Sur Yvette France IMEC Kapeldreef 75 B-3001 Heverlee Belgium

ISBN: (纸本)9781510672239;9781510672222

This work presents a process optimization study of 18nm metal pitch (MP) semi-damascene interconnects with fully self-aligned Vias (FSAV) using SEMulator3D (R) virtual fabrication coupled with silicon data. Simulation was used to early identify process failures and avoid via opens found on silicon, and to ensure process manufacturability. A full predictive virtual model was calibrated against silicon data to predict the complete process flow from the M2 module to the via module. A process sensitivity analysis was performed to simulate process variability impact on via resistance performance. The simulation identified process parameters and corresponding process windows that need to be controlled to avoid via opens and ensure process manufacturability.

关键词： FSAV Metal pitch MP18 semi-damascene via resistance resistance variability manufacturability virtual fabrication

来源：评论

学校读者我要写书评

暂无评论

Multi-step process optimization of high aspect ratio etching for memory devices 13

Multi-step process optimization of high aspect ratio etching...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Zaima, Kazunori Tsuda, Hirotaka Manabe, Yuta Omura, Mitsuhiro Kioxia Corp Adv Memory Dev Ctr 800 Yamanoisshiki Cho Yokaichi Mie 5128550 Japan

ISBN: (纸本)9781510672239;9781510672222

We performed a multi-step process optimization for high-aspect ratio etching using a Monte-Carlo based etching process simulation by solving the inverse problem. In this simulation, physical and empirical models are combined to provide a surface reaction model with response process knobs to achieve high accuracy within a short calculation time. We constructed a physical model for surface reactions which includes physical sputtering, chemical sputtering, radical deposition, surface modification by radicals, and thermal isotropic etching. We also updated the physical model to accommodate equipment parameters on the basis of experimental data. In this paper, we optimized 2-step recipe parameters including step time, low frequency RF power, O-2 flow rate and C4F8 flow rate. This yielded conditions for achieving straighter profiles. Furthermore, we experimentally verified that one of the proposed recipes has a better profile than that of the baseline condition. We achieved a straighter profile by optimizing multiple parameters with different bottom vs. bow sensitivity and by appropriate multi-step control.

关键词： Reactive Ion etching High aspect ratio Multi-step process optimization Feature process simulation

来源：评论

学校读者我要写书评

暂无评论

MEMS-on-CMOS integration of a holographic 8M-Pixel SLM device using KrF-Lithography 13

MEMS-on-CMOS integration of a holographic 8M-Pixel SLM devic...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Doering, S. Recknagel, P. A. Hohle, C. Duerr, P. Fraunhofer Inst Photon Microsyst IPMS Maria Reiche Str 2 D-01109 Dresden Germany

ISBN: (纸本)9781510672239;9781510672222

We discuss the process integration to manufacture a spatial light modulator (SLM) device for application in mixed and augmented reality. The MEMS-part of the device is integrated on an external 180nm CMOS. The SLM consists of an 8MPixel micro mirror array with a pixel size of 4 mu m x 6 mu m. To provide the vertical strokes necessary for RGB color image generation, a comb-drive actuator concept was developed. Besides the yoke and the stator of the comb-drive, the actuator uses a double spring structure to reduce tilting of the mirror and other stress-induced effects. At the beginning of the product development we used iLine-lithography only, while later for the final device we switched to KrF-lithography to provide the necessary feature size down to 200nm as well as better CD-uniformity and overlay specification. We describe the process development, with focus on the lithography and etching processes for the actuator. Especially the different processes for patterning the Titanium-Aluminum structures of ultra-thin springs as well as the yoke and the stator with their high aspect ratios, which are specific for MEMS processing. Finally we achieved post-etch CD- uniformity <10nm per wafer for all metal structures as well on-product-overlay accuracy <15nm.

关键词： Spatial Light Modulator SLM MMA AR/MR/VR integration holography MEMS KrF-Lithography

来源：评论

学校读者我要写书评

暂无评论

Dry etch Challenges for Patterning Middle-of-line (MOL) Contact Trench in Monolithic CFET (complementary FET) 13

Dry Etch Challenges for Patterning Middle-of-line (MOL) Cont...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Sarkar, T. Radisic, D. Gonzalez, V. Vega Stiers, K. Sheng, C. Montero, D. Jenkins, H. Demand, M. Wang, P. Lazzarino, F. Horiguchi, N. IMEC Kapeldreef 75 B-3001 Leuven Belgium TEL Technol Ctr Amer LLC Albany NY 12203 USA Tokyo Elect Europe Ltd Kapeldreef 75 B-3001 Leuven Belgium

ISBN: (纸本)9781510672239;9781510672222

In a complementary FET (CFET), n- and p-type transistors are stacked on top of each other to enable device scaling. This stacking approach requires very high aspect ratio vertical feature pattering, namely, active gate, spacer source/drain cavity and contact patterning. We report contact trench patterning and plasma etch process development for contacting bottom and top transistors relevant to middle-of-line (MOL) integration in monolithic nanosheet based CFET. First, deep trenches (M0) with aspect ratio (AR) similar to 13 - 15 are etched into SiO2 dielectric layer between tall gates for routing bottom device. After the formation of bottom device, MOL contact patterning (M0T, AR similar to 8 - 9) for top device is performed. The main etch challenges are to preserve gate and gate spacer (SiN) and achieve good depth uniformity, especially when the M0 trench CD is reduced at tight pitches. At pitch 50nm, M0 etch development results are shown for four different etch processes (named as etch Recipe 1 - 4) in which M0 etch depth is increased gradually targeting minimal SiN loss. To reduce gate spacer (SiN) loss, fluorocarbon plasma passivation and hydrocarbon polymer deposition step is used during M0 trench patterning.

关键词： CFET plasma dry etch contact patterning passivation selectivity

来源：评论

学校读者我要写书评

暂无评论

Where to apply sustainability optimizations in process flows? 13

Where to apply sustainability optimizations in process flows...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Filippidou, Konstantina Bezard, Philippe Liu, I-Yun Rolin, Cedric Lazzarino, Frederic Ragnarsson, Lars-Ake IMEC VZW Kapeldreef 75 Leuven Belgium

ISBN: (纸本)9781510672239;9781510672222

Future advanced semiconductor manufacturing processes are introducing significant patterning challenges. These challenges are coming together with additional requirements for sustainable, low Global Warming Potential/ low toxicity /low fine particle emissions. As a result, new solutions in terms of process integrations, molecules used for patterning modules, and overall stack of materials will have to meet those requirements while staying compatible with high-volume manufacturing (cost, availability, throughput, and overall patterning performance). Although specific process steps such as capacitor patterning for DRAM or 3D NAND high aspect ratio oxide etch are heavily scrutinized steps in terms of emissions and patterning challenges, many applications, including logic, integrate hundreds of steps where the patterning of 10-30 nm-thick layers requiring fluorine-containing gases. Although independently accounting for a modest amount of emissions, their sheer counts makes them a major contributor to CO2 equivalent emissions. In this work, the cumulative impact of these low aspect-ratio patterning steps will be modelled through the *** program model. Then, the impact of a few sustainability-optimized solutions, such as low temperature etching for ultra-thin layer or stack optimization will be assessed.

关键词： Sustainability dry etching optimization

来源：评论

学校读者我要写书评

暂无评论

Active area patterning for CFET - Nanosheet etch 13

Active area patterning for CFET - Nanosheet etch

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Brissonneau, V. Koo, Il Gyo Hosseini, M. Batuk, D. Veloso, A. Mannaert, G. Lazzarino, F. IMEC Kapeldreef 75 B-3001 Heverlee Belgium

ISBN: (纸本)9781510672239;9781510672222

Nanosheet device architectures such as complementary FET (CFET) are candidates to replace FinFET, improving device performance while allowing a higher density of devices for a similar footprint. Two main challenges can be highlighted in the definition of the active area (AA) patterning for CFET. First the presence of stacked nanosheets generates the need for a higher aspect-ratio compared to FinFET. Secondly, the nanosheets layers, composed of silicon and silicon-germanium with varied thicknesses and concentrations, require new approaches in terms of process definition and control. The first results of an active area patterning for a full CFET device have been demonstrated at imec. Thicker nanosheet stacks are patterned opening the path to the creation of a complete CFET device.

关键词： CFET Nanosheet Active Area

来源：评论

学校读者我要写书评

暂无评论

Investigation of the Influence of Hardmask Morphology on Bowing Effect in Nano-scale Silicon Plasma etching process 13

Investigation of the Influence of Hardmask Morphology on Bow...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Hu, Ziyi Li, Junjie Shao, Hua Chen, Rui Wei, Yayi Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuit Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China

ISBN: (纸本)9781510672239;9781510672222

Bowing is one of plasma etching effects that negatively impact device performance. Although there has been plenty of research work on micro-feature surface etch modeling to investigate bowing effect, limited research has been reported on the influence of hardmask morphology on bowing effect. In this paper, we present a plasma etching model based on Monte Carlo simulation with cellular method in order to simulate the feature profile evolution of etching process in nano-scale. The relationship among hardmask angle, open CD and distribution of reflected ion flux on the sidewall from the opposite hardmask was calculated. The reflected ion flux was heavily concentrated in the upper part of the sidewall in the case of a tapered hardmask, and this was the main mechanism of the bowing formation. This model considers chemical reactions and a novel particle reflection algorithm which is a prominent mechanism. This model is capable of reproducing the feature in periodic dense trenches with dimension of tens of nanometers. The hardmask morphology considered in our study includes hardmask angle (theta) and pattern (CD and pitch). As the hardmask angle decreases, the bowing becomes severe, when CD equals to 90nm and theta equals to 70 degrees, the bowing deviation (D=(W-CD)/2) and relative deviation (Delta D=D/CDx100 %) are 23.86nm (26.51 %). In contrast, as the CD increases, the bowing becomes slight. However, bowing moves toward the bottom of the hole as the CD increases. When CD equals to 150nm and theta equals to 70 degrees, the bowing deviation is 18.95nm (12.63 %). Accordingly, a vertical hardmask is very important for a small CD trench.

关键词： plasma etching etch model bowing hardmask morphology particle reflection

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共6页 << < 1 2 3 4 5 6 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：