检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

51 篇 会议

馆藏范围

51 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

39 篇 工学
- 39 篇 材料科学与工程（可...
- 13 篇 电气工程
35 篇 理学
- 35 篇 物理学
4 篇 医学
- 4 篇 临床医学

主题

8 篇 etching
8 篇 plasma etching
6 篇 etch
5 篇 optical lithogra...
4 篇 plasma
4 篇 cfet
3 篇 semiconducting w...
3 篇 ler
3 篇 line width rough...
3 篇 silicon
3 篇 lithography
3 篇 high aspect rati...
3 篇 sadp
3 篇 back end of line
3 篇 euv
3 篇 nanosheet
2 篇 metals
2 篇 gaa
2 篇 photomasks
2 篇 electrical yield...

机构

6 篇 imec kapeldreef ...
5 篇 imec kapeldreef ...
4 篇 america llc tel ...
3 篇 chinese acad sci...
2 篇 sandbox semicond...
2 篇 tokyo electron l...
2 篇 univ chinese aca...
1 篇 cea leti 17 rue ...
1 篇 stmicroelectroni...
1 篇 cea leti 17 rue ...
1 篇 univ grenoble al...
1 篇 ibm corp tj wats...
1 篇 arkema france f-...
1 篇 ibm res semicond...
1 篇 synopsys inc 675...
1 篇 coventor 3 ave q...
1 篇 univ bordeaux en...
1 篇 imec b-3001 leuv...
1 篇 ltm cnrs 17 ave ...
1 篇 changxin memory ...

作者

7 篇 lazzarino f.
4 篇 ko akiteru
4 篇 wei yayi
4 篇 raley angelique
4 篇 chen rui
4 篇 biolsi peter
4 篇 barnola s.
4 篇 shao hua
3 篇 li junjie
3 篇 kumar kaushik
3 篇 demuynck s.
3 篇 chan b. t.
3 篇 mannaert g.
3 篇 mohanty nihar
3 篇 horiguchi n.
3 篇 tiron r.
3 篇 dupuy e.
2 篇 gupta a.
2 篇 barros p. piment...
2 篇 chopra meghali j...

语言

51 篇 英文

检索条件"任意字段=Conference on Advanced Etch Technology and Process Integration for Nanopatterning XIII"

共 51 条记录，以下是11-20 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Metalens Manufacturing Complexities and Costs 13

Metalens Manufacturing Complexities and Costs

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Melvin, Lawrence S., III Chalony, Maryvonne Dawes, Andrew M. C. Kuechler, Bernd Zimmermann, Rainer Viasnoff, Emilie Zhou, Ying Blais, Al Synopsys EV Pole Act Hyerois 1128 F-83400 Hyeres France Synopsys GmbH Karl Hammerschmidt Str 34 D-85609 Aschheim Dornach Germany Synopsys Inc 675 Almanor Ave Sunnyvale CA 94085 USA Synopsys Inc 2025 Cornelius Pass Rd Hillsboro OR 97124 USA Synopsys Inc 400 Execut BlvdSuite 101 Ossining NY 10562 USA

ISBN: (纸本)9781510672239;9781510672222

Background: Metalenses are flat devices that focus and manipulate optical waves. Unlike reflective and refractive optics, metalenses rely on phase shifts introduced by subwavelength metastructures. Aim: Demonstrate the cost and performance impact of using manufactured metaatoms from two lithography processes to design and manufacture metalenses. Approach: Design two types of metalenses, the first type (ideal) uses an ideal design made up of square metaatoms. This lens design is then simulated using both 193 nm and 248 nm lithography processes. The second type (manufacture-aware) uses a design that is built around metaatom profiles produced by the corresponding lithography process (193 nm and 248 nm respectively). By comparing the performance of these two approaches (ideal and manufacture-aware) we demonstrate the process performance impact can be reduced. Results: Comparing 193 nm and 248 nm processes show a up to a 27% difference in monochromatic metalens performance for a design derived from ideal metaatoms. However, by simulating manufactured metaatoms and using them in the design stage, manufactured metalens performance returns to within 7% of ideal. Conclusions: When designing with manufactured metaatoms rather than ideal metaatoms, metalens performance is similar between both 193 nm and 248 nm processes and manufacture-aware design makes either process viable for visible-light metalens manufacturing.

关键词： Metalens metaatom photolithography reactive ion etch manufacturing process design aware flow

来源：评论

学校读者我要写书评

暂无评论

Study of Selective Dry etching Si0.7Ge0.3 with Different Plasma Source in process of Gate-all-around FET 13

Study of Selective Dry etching Si0.7Ge0.3 with Different Pla...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Liu, Enxu Yang, Chaoran Li, Junjie Zhou, Na Xia, Longrui Chen, Rui Shao, Hua Gao, Jianfeng Kong, Zhenzhen Zhang, Chenchen Lai, Panpan Yang, Tao Wei, Yayi Li, Junfeng Luo, Jun Wang, Wenwu Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuit 3 West Beitucheng Rd Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits 3 West Beitucheng Rd Beijing 100049 Peoples R China

ISBN: (纸本)9781510672239;9781510672222

The lateral gate-all-around (GAA) field effect transistor is considered to be the most promising candidate for the next generation of logic devices at the 3nm technology node and beyond. SiGe plays an important role as a sacrificial layer in the GAA device, which requires isotropic etching, and the quality of the etching has a critical impact on the device performance. However, there is no definite scheme in the industry for the choice of etching method. In this paper, we choose two etching methods-ICP(Inductively coupled Plasma) and RPS (Remote Plasma Source) etching according to the presence or absence of particle incidence. The profile and etching effect of the two etching methods are analyzed by PEGASUS simulation software. The presence or absence of particle incidence has different effects on the damage of the structure, the inconsistency of etching amount and the reflection of the particles on the Si surface. Compared with ICP etching, the optimization of RPS etching on etching damage and etch amount consistency is verified by TEM and roughness characterization. And through the extraction of MOSCAP capacitance, it is found that the density of interface states(Dit) after ICP etching is 3.5 times higher than that of RPS etching.

关键词： GAA selective etching silicon germanium remote plasma process simulation

来源：评论

学校读者我要写书评

暂无评论

Modeling of Silicon Nitride Chemical Vapor Deposition in High Aspect Ratio Nano-scale Substrate Features 13

Modeling of Silicon Nitride Chemical Vapor Deposition in Hig...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Shao, Hua Deng, Sen Yang, Chaoran Li, Junjie Chen, Rui Wei, Yayi Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuit Beijing 100029 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China

ISBN: (纸本)9781510672239;9781510672222

Three-dimensional (3D) architectures have become main stream for the advanced node logic and memory devices, such as the gate-all-around field effect transistors (GAAFET) and 3D dynamic random access memory (3D DRAM). These devices feature with stacked structure offers higher integration, better device performance and lower power consumption. However, the manufacturing of such devices needs high aspect ratio (AR) feature processing which brings challenges to conventional thin film deposition process such as chemical vapor deposition (CVD). SiN is a common barrier and spacer material and usually grown by CVD with a gas mixture of SiH4/NH3/N-2. In this work, we conduct simulations of SiN CVD process in deep trenches to investigate the thin film step coverage dependence on process conditions and AR. We adopt the reaction-diffusion theory to develop the surface growth model of SiN deposition and set a few semi-empirical mechanism parameters to calibrate the model with experimental results. Simulation results show that in the substrate trench with 50nm open CD and AR of 5, the film deposition step coverage becomes better as the fluxes of neutrals increases, corresponding to lager f(neu) value. Simulations also suggest that with trench depth fixed at 250nm, as the AR of the trench increases, the overall deposition rate in the trench decreases. As the AR increases, the density of the reactant species such as radicals and ions decrease and the diffusion-limited phenomenon appear, which further reduces the reaction rate at the bottom of the trench.

关键词： process modeling chemical vapor deposition silicon nitride high aspect ratio

来源：评论

学校读者我要写书评

暂无评论

A Novel Kinetic Framework Based Multiscale Modeling of Spatial Atomic Layer Deposition process 13

A Novel Kinetic Framework Based Multiscale Modeling of Spati...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Deng, Sen Shao, Hua Han, Dandan Chen, Rui Wei, Yayi Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuit Beijing 100029 Peoples R China

ISBN: (纸本)9781510672239;9781510672222

Atomic layer deposition (ALD) technology is a self-limiting film deposition process that grows films on substrates through repeated process cycles of precursor dosing, purge, co-reactant dosing and purge. This technology is widely utilized in advanced technology node processes due to its merits of excellent step coverage and atomic scale film thickness control. However, as the industry moves to three-dimensional (3D) device architectures, ALD faces emerging challenges such as the bottle neck phenomenon in extremely high aspect ratio structure with nanometer scale trench or hole open. ALD modeling provides insights into the underlying mechanisms and help engineers optimize the process. There has been research on different kind of ALD process models on film conformity, growth profile and saturation behavior at multiscale from reactor to micro-feature and molecular level. Angel Yanguas-Gil et al. proposed a reactor scale model which discussed the ideal and non-ideal self-limited processes in a cylindrical and a 300 mm wafer cross-flow reactor. Adomaitis et al. presented a multiscale model to describe the reactant transport in a high aspect ratio nanopore and growth of ALD film based on continuum and Monte Carlo model. In this work, we propose an ALD model in order to simulate the spatial ALD process, coupling with surface reaction kinetics theory and hydrodynamics model. Firstly, we analyze and model the adsorption process of precursor molecules and co-reactant molecules, as well as their transport mechanism in ALD reactor chamber. Secondly, we discuss how the substrate temperature, precursor and co-reactant partial pressure, and reaction probabilities influence coverage distribution and growth per cycle in spatial ALD process. This model enables the possibility of spatial ALD process parameter optimization in an efficient and economy way.

关键词： spatial atomic layer deposition ALD process simulation multiscale modeling computational fluid dynamics

来源：评论

学校读者我要写书评

暂无评论

Patterning spacer source drain cavities in CFET devices 13

Patterning spacer source drain cavities in CFET devices

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Choudhury, S. Mannaert, G. Lima, L. P. B. Demuynck, S. Koo, I. G. Lazzarino, F. IMEC B-3001 Leuven Belgium

ISBN: (纸本)9781510672239;9781510672222

In conventional gate-all-around FET architecture, p-type and n-type devices are stacked on top of each other on separate devices. In Complementary FET (CFET) architecture, n-MOS and p- MOS devices are stacked in the same device on top of each other. This allows for reduction in footprint and power consumption. One of the most high aspect ratio (HAR) patterning in CFET processing comes from patterning of the gate spacer, followed by nanosheet (NSH) patterning. The HAR Spacer Source/Drain cavity area is a Si/SiGe/Dielectric superlattices bringing quite a few patterning challenges. This work discusses the challenges for the spacer opening, optimization of the profile of the source drain (SD) cavity and strategies to improve selectivity with the gate hard mask (HM). The first patterning challenge includes etching of a superlattice consisting of numerous materials, including dielectrics, while maintaining selectivity to HM. This means switching of chemistries to accommodate the patterning of these multilayers. Secondly, this patterning step needs to be highly selective to the gate HM to allow enough margin for downstream processes. The patterning step also needs to deliver vertical cavity profile. All these challenges require us to explore complex etch processes including in-situ isolation, passivation, and other etching sequences. The results and challenges for a fully patterned spacer & SD cavity as demonstrated at Imec are presented in this proceeding.

关键词： CFET HAR Spacer Nanosheet etch

来源：评论

学校读者我要写书评

暂无评论

Extreme UV Self-Aligned Double Patterning process optimization for BEOL interconnections on 3nm nodes and beyond 13

Extreme UV Self-Aligned Double Patterning process optimizati...

引用

conference on advanced etch technology and process integration for nanopatterning xiii

作者： Montero, D. Buccheri, N. Lin, Q. Roy, S. Paolillo, S. Wu, C. Hermans, Y. Decoster, S. Baudemprez, B. Finoulst, J. F. Lazzarino, F. Park, S. Tokei, Z. IMEC Kapeldreef 75 B-3001 Leuven Belgium

ISBN: (纸本)9781510672239;9781510672222

Microchip downscaling has been one of the main drivers on the semiconductor industry to enable faster, more efficient, and compact microchips, greatly broadening their range of applications, like the Internet of Things, smart mobility, artificial intelligence and 5G, among others. Aside from transistor scaling, the Back End of Line (BEOL) interconnection network, which transfers power and signals from and into the transistors, must also be scaled down consequently. The scaling requirements have surpassed the maximum resolution achievable by any lithographic technique by solely relying on direct printing. In the case of low numerical aperture, Extreme UV (low NA EUV), the most advanced, commercially available lithography technology, printing line/space structures below pitch 30 nm (P30) is extremely challenging [1]. However, 3nm and newer nodes require BEOL line space structures with P26 nm or narrower, in particular for the M2 layer. It is here where multipatterning techniques come into play. Self-Aligned multipatterning techniques allow to divide by a factor of two (double patterning, SADP), four (quadruple patterning, SAQP) or even eight (octuple patterning, SAOP) the pitch printed at lithography level, easing the lithography requirements [2]. However, with multipatterning, there comes a risk that not all interconnect lines would be patterned with equal dimensions, which would introduce resistance and capacitance variations across lines that theoretically should be equivalent. Hence, all multipatterning techniques require a precise control of each of the fabrication steps to guarantee that all lines and spaces present the same dimensions, i.e., a balanced patterning with no pitch walking. The target of our work is to find the fabrication parameters that lead to the lowest pitch walking, roughness and defectivity conditions on EUV SADP patterning (eSADP) at P21 nm structures with 10.5 nm metal line Critical Dimension (CD). Thus, we carried out a set of experiments

关键词： EUV multipatterning self-aligned double patterning (SADP) pitch walking 3nm node unbiased roughness

来源：评论

学校读者我要写书评

暂无评论

Control of sidewall roughness formation in through-silicon via etch at non-cryogenic temperatures 11

Control of sidewall roughness formation in through-silicon v...

引用

conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Papalia, John M. Koty, Devi Marchack, Nathan LeFevre, Scott Yang, Qingyun Mosden, Aelan Engelmann, Sebastian U. Bruce, Robert L. IBM TJ Watson Res Ctr 1101 Kitchawan Rd Yorktown Hts NY 10598 USA America LLC TEL Technol Ctr Albany NY USA

ISBN: (纸本)9781510649880;9781510649873

Through-silicon via etch (TSV) is critical to current and future advanced packaging schemes. For heterogeneous integration approaches in particular, where modular components are tightly packed together, these processes play an integral role.1 While etch processes for silicon appear well understood and the frontiers of plasma etch have led us to advanced cyclic processes for device fabrication such as atomic layer etching, TSV applications are fundamentally different due to their relative size and aspect ratio targets. Unlike small-scale etching, TSV feature etching has not shown exponential change over time.(2) To achieve TSV targets such as high etch rate, high aspect ratio, and clean profiles to support filling, known solutions are employed such as cryogenic wafer temperatures(3), alternative hard mask schemes(4), and extremely short gas cycle times(5);these solutions require specialized equipment and/or a more complex integration scheme. We explore the creation of high-aspect ratio, diffusion-limited TSV etches with high PR selectivity (>50:1) and high aspect ratios while simultaneously aiming for a high etch rate all while using non-cryogenic temperatures and a standard photoresist mask. A focus on sidewall profile and sidewall damage is maintained.

关键词： TSV sidewall damage profile aspect ratio selectivity

来源：评论

学校读者我要写书评

暂无评论

Tone reversal patterning for advanced technology nodes 11

Tone reversal patterning for advanced technology nodes

引用

conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Schleicher, F. Bekaert, J. Thiam, A. Decoster, S. Blanc, R. Lazzarino, F. Santaclara, J. Garcia Rispens, G. Maslow, M. IMEC Kapeldreef 75 B-3001 Leuven Belgium ASML De Run 6501 NL-5504 DR Veldhoven Netherlands

ISBN: (纸本)9781510649880;9781510649873

As technology nodes continue to scale down, maintaining roughness and defectivity during the pattern transfer becomes more challenging. For the smallest features, Metal-Organic Resists (MOR) are preferred due to their better selectivity than Chemically Amplified Resists (CAR). However, MORs are usually negative tone resists. Primarily based on defectivity reasons, dark field Extreme Ultraviolet (EUV) masks are strongly preferred over light field EUV masks. Therefore, the MOR resist is more suited for pillar patterning than hole patterning. The purpose of this paper is to show that exposing pillars with MOR and converting them into holes can yield better roughness and defectivity than patterning holes with CAR directly. A similar comparison is done for the tone reversal of lines and spaces. It is shown that the Local Critical Dimension Uniformity (LCDU) of holes and the Line Edge Roughness (LER) of lines/spaces are well conserved throughout the tone inversion process.

关键词： hole patterning pillar patterning lines and spaces tone reversal tone inversion LER dry etch LCDU EUV metal-organic resist

来源：评论

学校读者我要写书评

暂无评论

Patterning of Ru metal lines at 18 nm pitch 11

Patterning of Ru metal lines at 18 nm pitch

引用

conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Decoster, Stefan Kundu, Souvik Lazzarino, Frederic Lariviere, Stephane O'Toole, Martin Murdoch, Gayle Quoc Toan Le van der Veen, Marleen Heylen, Nancy IMEC Kapeldreef 75 B-3001 Heverlee Belgium

ISBN: (纸本)9781510649880;9781510649873

In this work, we present two different approaches to pattern Ru metal lines at a metal pitch of 18 nm, by making use of self- aligned double patterning (SADP) in combination with EUV lithography. The first and more conventional patterning approach is to define the 18 nm pitch gratings into a hard mask by means of SADP, which is consequently transferred into the Ru layer by means of direct metal etch. The second and more innovative approach consists of a combination of direct metal etch and damascene filling of Ru. This so-called mixed flow is a patterning- friendly approach which enables the integration of self-aligned cuts and vias. We will share the schematics as well as the results for 18 nm pitch Ru gratings on 300 mm Si wafers for both approaches. Finally, we will discuss and demonstrate the enablement of selfaligned cuts and vias for the mixed flow, which makes this patterning flow a promising alternative to standard damascene patterning for future interconnects at sub- 20 nm metal pitches.

关键词： back-end-of-line (BEOL) ruthenium interconnects direct metal etch double patterning SADP damascene

来源：评论

学校读者我要写书评

暂无评论

Middle-of-line plasma dry etch challenges for Buried Power Rail integration 11

Middle-of-line plasma dry etch challenges for Buried Power R...

引用

conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Radisic, Dunja Veloso, A. Gupta, A. Hosseini, M. Wang, S. Mertens, H. Chan, B. T. Batuk, D. Martinez, G. T. Lazzarino, F. Litta, E. D. Horiguchi, N. IMEC Kapeldreef 75 B-3001 Heverlee Belgium

ISBN: (纸本)9781510649880;9781510649873

Buried power rail (BPR), a novel integration approach for further device scaling, brings in new patterning needs and requirements, the most importantly, the challenging middle-of-line (MOL) patterning process steps. In this paper, some of the critical plasma dry etch development processing results for the FinFET device flow with BPR integrated are presented. Mainly, the study was focused on plasma dry etch development of high aspect ratio Via contact to BPR metal (VBPR) and Trench contact etch (M0A) to the source/drain (S/D) device region. We demonstrate the short-free M0A (no attack on the neighboring gates) contact etch to the S/D, with the high etch selectivity values obtained in case of the dielectric SiO2 trench etch to the thin Si3N4 liner (deposited over epitaxial S/D), and subsequently the high selectivity values during SiN liner etch to the underlying S/D (SiN liner etch results in 0nm epitaxial film loss). Patterning of high aspect ratio (HAR) Via consisting of the multi-stack, SiO2/SiN/SiO2/SiN dielectric, landing on the bottom BPR metal was achieved, with the target critical dimension (CD) required to avoid shorting to the adjacent gates. Additionally, we report our learnings on how choice of buried power metal (W, Ru and Mo) impacts the etch requirements, i.e., the etch challenges associated by using Ru and Mo as a replacement for standardly used W metal.

关键词： Buried power rail Selective SiO2 plasma etch Selective SiN Si3N4 plasma etch FinFET MOL plasma etch Buried metal plasma recess

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共6页 << < 1 2 3 4 5 6 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：