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检索条件"任意字段=Conference on Advanced Etch Technology and Process Integration for Nanopatterning XIII"

共 51 条记录，以下是21-30 订阅

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Creating new multistep etch and deposition processes with recycled etch data using SandBox Studio AI™ 11

Creating new multistep etch and deposition processes with re...

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conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Kearney, Kara Medina, Leandro Bonnecaze, Roger T. Chopra, Meghali J. SandBox Semicond Inc 9901 Brodie LaneSuite 160568 Austin TX 78748 USA

ISBN: (纸本)9781510649880;9781510649873

Identification of optimal recipes for multi-step and cyclic etch processes where the outcome of each step depends on the progression of the previous steps is a major challenge. Selecting the order and duration of each step is typically performed by a tedious trial and error process where the number of experimental trials scales exponentially with process complexity. Here we present a simulation-based methodology that significantly accelerates the process. We use limited experimental data taken at various process conditions, which may include pressure, gas type, gas flow rate, power, bias, and time to calibrate a step-aware reduced-order physics-based etch and deposition model. This model is used to generate predictions with steps permuted in any desired order and duration. The calibrated model predicts ordering, timing, and possible cycling of each step to achieve desired etch targets. The methodology is demonstrated on a multilayer stack with three possible steps, including etch and deposition. It is shown that the total number of experiments required for the proposed methodology is significantly less than that required by standard methods like full-factorial design of experiment. We also demonstrate how the etch data and the resulting calibrated model can be used to determine the optimal etch recipe for different aperture and/or mask geometries without having to perform further experiments.

关键词： etch etch recipe creation multi-step etch deposition experimental design modeling

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Automated high throughput optimization of multistep and cyclic etch and deposition processes using SandBox Studio™ AI 11

Automated high throughput optimization of multistep and cycl...

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conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Kearney, Kara Medina, Leandro Bonnecaze, Roger T. Chopra, Meghali J. SandBox Semicond Inc 9901 Brodie LaneSuite 160568 Austin TX 78748 USA

ISBN: (纸本)9781510649880;9781510649873

The development of new technologies and advanced nodes is capitally intensive due to process design strategies that involve dependent unit processes with different yields and performances. This has led to the exploration of model-based optimization to cut the cost and time of recipe creation;however, computational optimization of semiconductor processes is quite challenging due to multi-dimensional parameter spaces and limited experimental data. SandBox StudioT AI is a computational tool that automatically builds a hybrid physics-based and machine learning model that can be used to predict optimal process recipes and explore novel process changes such as different incoming mask geometries and step durations. Herein, we show the utilization of SandBox Studio T AI to build a computational representation of a cyclic etch and deposition process of a high aspect ratio channel etch with the following detrimental effects - bowing, resist over-etching, clogging via deposition, and twisting. The model was calibrated to a synthetic data set of thirteen experiments with five varying process parameters. Then, an optimal recipe was predicted that minimized the observed detrimental effects. The model was then used to explore different incoming mask geometries and step durations to improve the recipe even further. This capability is made possible by the software's foundational physics-based model and is not possible using conventional statistics and machine learning based tools.

关键词： etch Deposition Experimental Design process Optimization High Aspect Ratio Recipe Creation Computation Twisting Clogging

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OPC accuracy improvement through deep-learning based etch model 11

OPC accuracy improvement through deep-learning based etch mo...

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conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Shi, Weina Zhu, Liang Chen, Yuqian Huang, Jiao Wang, Jinze Xie, Qian Zhang, Bilun Xi, Yunfei Pan, Wenhao Zheng, Yuanxia Fan, Yongfa Cheng, Jin Zhao, Yu Zheng, Leiwu ChangXin Memory Technol Inc Hefei Anhui Peoples R China ASML China Shenzhen 3023 Chuangye Rd Shenzhen Guangdong Peoples R China ASML US 80 W Tasman San Jose CA 95131 USA

ISBN: (纸本)9781510649880;9781510649873

This paper demonstrates a full-chip OPC correction flow based on deep-learning etch model in a DUV litho-etch case. The flow leverages SEM metrology (eP5 fast E-beam tool, ASML- HMI) to collect massive data, automated metrology software (MXP, ASML-Brion) to extract high quality gauges, and deep-learning etch modeling (Newron etch, ASML-Brion) to capture complicated etch behaviors. The model calibration and verification are performed using a combined data from a test and real chip wafer to ensure sufficient pattern coverage. The model performance of Newron etch is benchmarked against a term-based etch model, wherein Newron etch model shows significant accuracy improvement in the model calibration (>50% for test patterns and >35% for real chip pattern). The Newron etch model is proven stable with a comparable performance in the model verification. Particularly, strong loading effects from underlying sublayer are observed in the full chip wafer, and effectively captured by the Newron etch with a sublayer-aware model form. The calibrated Newron etch model is successfully applied in a model-based etch OPC tape-out with new mask design rules but the same litho-etch process conditions. Compared to the term-based model, Newron etch also shows significant accuracy improvement.

关键词： AEI litho-etch bias deep learning etch model sublayer aware high-quality EP gauges fast metrology flow OPC model accuracy and stability etch OPC

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Mitigation of the etch-induced intra-field overlay contribution 11

Mitigation of the etch-induced intra-field overlay contribut...

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conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： van Haren, Richard Yildirim, Oktay Mouraille, Orion van Dijk, Leon Kumar, Kaushik Feurprier, Yannick Jehoul, Christiane Hermans, Jan ASML Flight Forum 1900 5846 NL-5657 EZ Eindhoven Netherlands Tokyo Electron Ltd Minato Ku Akasaka Biz Tower3-1 Akasaka 5 Chome Tokyo 1076325 Japan IMEC Kapeldreef 75 B-3001 Leuven Belgium

ISBN: (纸本)9781510649880;9781510649873

In order to fully utilize the potential of the latest and greatest scanner overlay performance capability in a manufacturing environment, all other (process-induced) overlay contributors should be well understood and eliminated where possible. While overlay penalties that slowly vary across the wafer and/or within each exposure field can easily be corrected with the available scanner correction knobs, this is less likely going to happen for overlay signatures that manifest themselves on a much shorter length scale. We refer to length scales that are comparable to the floorplan of the integrated circuit itself. A deep understanding of these process induced overlay contributions is required to take away their root causes. Several non-scanner overlay contributors are known that may have an impact on the scanner exposure field overlay performance. Of course, the quality of the mask itself plays an important role. Mask writing errors correlate one-to-one with the on-wafer overlay performance. Local stress effects may contribute to the intra-die overlay performance too. We extensively addressed the layer stress impact on the intra-field overlay in an earlier publication. In that work, an interesting observation was made. The etch-induced overlay contribution turned out to be largely independent of the layer stress in which the pattern was etched. The conclusion was drawn that the etch-induced overlay penalties can be optimized separately from layer stress related overlay effects. In this work, the focus will be on the etch-induced overlay penalties only. We addressed the etch-induced overlay impact already before. Surprisingly, the etch-induced overlay penalties showed up in every exposure field despite the fact that the etch tool itself is not exposure field aware. For the use-case we investigated, the magnitude of the etch-induced intra-field overlay penalty was around 1-nm. This comes close to the scanner baseline overlay performance. A relation was found with the patt

关键词： Overlay On-product etch Intra-field Metrology to Device offset Exposure field

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Dielectric material etch selectivity control in dual-frequency capacitively coupled plasmas with dc-superposition 11

Dielectric material etch selectivity control in dual-frequen...

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conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Zhang, Du Kim, Hojin McInerney, Kathleen Luan, Pingshan Rogalskyj, George Wang, Mingmei America LLC TEL Technol Ctr Albany NY 12203 USA

ISBN: (纸本)9781510649880;9781510649873

Selective plasma etching among different dielectric materials is crucial to the manufacturing of advanced logic and memory devices. For instance, in self-aligned contact (SAC) etching, achieving highly selective SiO2 etching over Si3N4 is essential. By contrast, in self-aligned multi-patterning ( SAMP), selective Si3N4 spacer removal over SiO2 and Si is necessary. To effectively control the relative etch rates of various dielectric materials, etch gas chemistry optimization [for instance, see J. Vac. Sci. Technol. A 36, 040601 (2018), J. Vac. Sci. Technol. A 34, 041307 (2016)., J. Vac. Sci. Technol. A 35, 01A102 (2017), etc.] has been extensively investigated. On the other hand, hardware capabilities such as direct current superposition (DCS) and must also be considered for their effects on plasma physics and plasma-surface interactions. In this study, we examine the etch behavior for various dielectric materials e.g. SiO2, Si3N4, and low-k dielectrics in a TEL dual-frequency CCP chamber. Specifically, we focus on the gas ratio and DCS effects in a CF4/H-2/ Ar plasma. Contrary to the monotonically decreasing etch rates for SiO2 and low-k vs. increasing H-2/CF4 flow ratio in accordance with decreasing F/CFx density ratio, the experimental blanket Si3N4 etch rate exhibits a local maximum at H-2/( CF4+H-2) = 15%. Chamber-scale plasma simulations using the Hybrid Plasma Equipment Model (HPEM) indicate that the HF density is peaked at almost the same gas ratio. In addition, atomistic molecular dynamics (MD) and density functional theory ( DFT) simulations reveal hydrogen's role in modifying the Si3N4 surface through N-H bond formation, thereby creating a hydrophilic surface on which HF adsorption is enhanced. Finally, computed reactant flux trends also demonstrate that the effect of DC superposition (DCS) on the relative orders of various ion and neutral reactant fluxes to the wafer is significantly weaker compared to that of the H-2/(CF4+H-2) flow ratio. This suggests t

关键词： Dielectric etching etch selectivity plasma chemistry plasma-surface interactions multi-scale modeling

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Buried Power Rail integration for CMOS Scaling beyond the 3 nm Node 11

Buried Power Rail Integration for CMOS Scaling beyond the 3 ...

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conference on advanced etch technology and process integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Gupta, A. Tao, Z. Radisic, D. Mertens, H. Pedreira, O. Varela Demuynck, S. Boemmels, J. Devriendt, K. Heylen, N. Wang, S. Kenis, K. Teugels, L. Sebaai, F. Lorant, C. Jourdan, N. Chan, B. T. Subramanian, S. Schleicher, F. Peter, A. Rassoul, N. Siew, Y. Briggs, B. Zhou, D. Rosseel, E. Capogreco, E. Mannaert, G. Sepulveda, A. Dupuy, E. Vandersmissen, K. Chehab, B. Murdoch, G. Sanchez, E. Altamirano Biesemans, S. Tokei, Zs Litta, E. Dentoni Horiguchi, N. IMEC Kapeldreef 75 B-3001 Leuven Belgium

ISBN: (纸本)9781510649880;9781510649873

As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.

关键词： Ruthenium Metals Molybdenum etching Tungsten Front end of line Chemical mechanical planarization Silicon

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Cleaning chamber walls after ITO plasma etching process 9

Cleaning chamber walls after ITO plasma etching process

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conference on advanced etch technology for nanopatterning IX

作者： Younesy, Salma Petit-Etienne, Camille Barnola, Sebastien Gouraud, Pascal Cunge, Gilles STMicroelectronics 850 Rue Jean Monnet F-38926 Crolles France LTM CNRS 17 Ave Martyrs F-38054 Grenoble 09 France CEA LETI 17 Ave Martyrs F-38054 Grenoble 09 France

ISBN: (纸本)9781510634268

The integration of new materials in the next generation of optoelectronic devices leads to several challenges. For instance, the etching of indium tin oxide (ITO, In2O3:Sn) faces the issue of the low volatility of In- and Sn-based etch products at room temperature. This is challenging for the etching process itself, but even more problematic when the inductively coupled plasma (ICP) reactor must be cleaned after etching: since the reactor walls are bombarded by low energy ions only, the removal of In- and Sn-based products redeposited on the walls can be very long and laborious. Therefore, we have investigated several plasma chemistries to find the most efficient reactor cleaning process suitable for ITO plasma etching. The results show that after ITO plasma etching the walls are indeed contaminated by indium. At the low temperature at which the reactor walls are regulated, BCl3/Cl-2 cleaning plasma is ineffective to remove this deposit while HBr and CH4/Cl-2 chemistries provide promising results.

关键词： Plasma etching chamber walls ITO cleaning process ICP

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FEOL dry etch process challenges of ultimate FinFET scaling and next generation device architectures beyond N3 9

FEOL dry etch process challenges of ultimate FinFET scaling ...

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conference on advanced etch technology for nanopatterning IX

作者： Tao, Z. Zhang, L. Dupuy, E. Chan, B. T. Altamirano-Sanchez, E. Lazzarino, F. IMEC Kapeldreef 75 B-3001 Heverlee Belgium

ISBN: (纸本)9781510634268

FinFETs have demonstrated significant performance improvement compared to planar devices, because of its superior short channel control and higher driving capability at a much smaller footprint. It has become the mainstream technology in CMOS industry since N20 node onward. Contact Poly Pitch (CPP) scaling used to be the main driving force in extending Moore's law. However, severe limitations are foreseen from N3 node in terms of electrical performance, process requirements and manufacturing complexity. At N3 node, both fin and gate pitches are expected to reach their ultimate values, respectively 21 nm and 42 nm. Therefore, complex plasma etching processes using advanced plasma pulsing modes or atomic layer etching ( ALE) are deployed to achieve high aspect ratio patterning capability with a detrimental effect on both process control and throughput. As an alternative, device architecture innovation will become the main scaling driving force for N3 node and beyond. 2D scaling like horizontal Gate-All-Around (GAA) devices, such as nanosheet (NS) and forksheet (FS) have demonstrated the potential for further device performance improvement [1,2]. The major NS patterning challenges are the SiGe lateral etch in the Si/SiGe superlattice stack and severe depth micro-loading due to the etch rate difference of SiGe and Si. In addition, 3D hybrid device architectures like Complementary FET ( CFET) and Surrounding-Gate-Transistors (SGT) are proposed as revolutionary innovations to scale the devices in the vertical direction. For CFET devices, the N/P separation is moved to the vertical direction by stacking nMOS on top of pMOS or vice versa to achieve aggressive device scaling. This requires extremely high aspect ratio fin and gate patterning compared to horizontal-GAA NS devices. For SGT device, the channel is switched to the vertical direction, which can decouple the Gate length (Lg) from CPP scaling and eliminate the diffusion break to deeply scale the cell size. High aspec

关键词： Plasma etching Scaling FinFET GAA Nanosheet Forksheet Nanowire CFET SGT advanced plasma pulsing Atomic layer etching

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Virtual Fabrication and advanced process Control Improve Yield for SAQP process Assessment with 16 nm Half-Pitch 8

Virtual Fabrication and Advanced Process Control Improve Yie...

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conference on advanced etch technology for nanopatterning VIII

作者： Vincent, Benjamin Lariviere, S. Wilson, C. Kim, R. H. Ervin, J. Coventor 3 Ave Quebec ZI Courtaboeuf F-91140 Villebon Sur Yvette France IMEC VZW Kapeldreef 75 B-3001 Leuven Belgium

ISBN: (纸本)9781510625747

This paper uses Virtual Fabrication to assess the imec 7 nm node (iN7) Self-Aligned Quadruple Patterning (SAQP) integration scheme for the 16 nm half-pitch Metal 2 line formation. We present first the technical challenge of obtaining defect-free M2 lines with SAQP, and then provide a solution to achieve a <1% failure rate using a combination of advanced process Control and Virtual Fabrication.

关键词： Back End of Line advanced Patterning Self-Aligned Quadruple Patterning Yield Forecast Yield Optimization

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etch aware computational patterning in the era of atomic precision processing 8

Etch aware computational patterning in the era of atomic pre...

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conference on advanced etch technology for nanopatterning VIII

作者： Ventzek, P. L. G. Shinagawa, J. Ranjan, A. Tokyo Electron Amer Inc 2400 Grove Blvd Austin TX 78741 USA

ISBN: (纸本)9781510625747

etch processes have always involved inherent process trade-offs related to fundamental plasma parameters to achieve planar patterning metrics related to damage, aspect ratio dependences and profile. Today, we are in a new era of "area selective etch." advanced patterning (SAXP, (LELE) n), logic, memory and interconnect applications beyond 3 nm involve, in one way or another, topographies that require etch "control" at every surface. Achieving profile specifications will require the ability to conjure isotropy control at will. Vehicles to achieving this include novel precursors and hybrid processes involving combinations of deposition and plasma etch as we know it. Ultimately, to differentiate surfaces comprising silicon, silicon oxides and nitrides, and organics require active modification at the first surface reactive monolayer to be able to differentiate them in each process step with respect to any surface normal on the wafer plane. This presentation will start with a review of today's state-of-the-art means for atomic precision processing of surfaces. A simulation science perspective to process integration modeling introduces methods for surface chemistry control that lend themselves to achieving area selective etch. In the end, surface chemistry control is not a cure-all. Finally, a combination of plasma diagnostics and simulation will be needed to assist plasma process controls for scaling at 3 nm and beyond.

关键词： plasma etch simulation patterning first-principles models

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