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检索条件"任意字段=Conference on Advanced Etch Technology and Process Integration for Nanopatterning XIII"

共 51 条记录，以下是31-40 订阅

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Plasma etch selectivity study and material screening for Self-Aligned Gate Contact (SAGC) 8

Plasma etch selectivity study and material screening for Sel...

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conference on advanced etch technology for nanopatterning VIII

作者： Radisic, Dunja Demand, Marc Chan, Shihsheng Demuynck, Steven Kumar, Kaushik Metz, Andrew Teugels, Lieve Sun, Junling Smith, Jeffrey Sebaai, Farid Hopf, Toby Sanchez, Efrain Altamirano IMEC Kapeldreef 75 B-3001 Heverlee Belgium Tokyo Electron Ltd Minato Ku Akasaka Biz Tower3-1 Akasaka 5 Chome Tokyo 1076325 Japan

ISBN: (纸本)9781510625747

Self-Aligned Gate Contact (SAGC) integration is design based on formation of the two separate contacts to the source/drain (S/D) and to the gate (G), which are realized in two separate plasma etch steps. Essentially, the first one is the contact plug (CP) etch over S/D contact selective to the gate plug (GP) and sidewall spacer (SWS), and the second one is the gate plug (GP) etch selective to the contact plug (CP) and the sidewall spacer (SWS). Therefore, the high selectivity plasma etch processing for the CP and GP towards the other two relevant, neighboring films is a key requirement for successful SAGC integration. In this paper we present plasma etch process development required for SAGC implementation, primarily focusing on the multi-color selectivity studies, i.e., selective CP (towards GP and SWS) as well as selective GP (towards CP and SWS) at contacted poly pitch (CPP) 42nm. The primary ('standard') integration scheme uses SiO2 CP, Si3N4 GP and SiCO SWS. Furthermore, we investigate the " alternative' integration scheme with SiCxNy films as replacement of the traditionally used SiO2 CP material aiming to simplify the patterning sequence and ease high selectivity requirements. We report the selectivity values obtained on the CP/GP/SWS multi-color stack for the CP plasma processing (SiO2 or SiCxNy) towards Si3N4 and SiCO;as well as for GP (Si3N4) plasma dry etch process towards SiO2 or SiCxNy and SiCO. Using a Quasi-ALE (Q-ALE) approach for selective SiO2 etch process is developed with a selectivity of 8 to 1 towards Si3N4 and SiCO. For the selective Si3N4 etch continuous wave plasma CH3F-based process is developed and selectivity of 9 to 1 towards SiO2 and SiCO achieved. In the case of the integration scheme with SiCxNy CP, the selectivity for SiCxNy etch towards Si3N4 GP and SiCO SWS higher than 20 to 1 is accomplished using continuous RF source NF3/O-2-based process. As for the Si3N4 plasma etch in the 'alternative' scheme using CH3F/O-2-based process, the

关键词： Self-aligned gate contact Selective SiO2 plasma etch Selective Si3N4 plasma etch Selective SiC plasma etch Selective SiCN plasma etch CPP42nm

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Self-Aligned Blocking integration Demonstration for Critical sub 30nm pitch Mx Level Patterning with EUV self-aligned double patterning 7

Self-Aligned Blocking Integration Demonstration for Critical...

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conference on advanced etch technology for nanopatterning VII

作者： Raley, Angelique Lee, Joe Smith, Jeffrey T. Sun, Xinghua Farrell, Richard A. Shearer, Jeffrey Xu, Yongan Ko, Akiteru Metz, Andrew W. Biolsi, Peter Devilliers, Anton Arnold, John Felix, Nelson IBM Res Semicond Technol Res San Jose CA USA Tokyo Elect Ltd Austin TX 78741 USA

ISBN: (数字)9781510616714

ISBN: (纸本)9781510616714

We report a sub-30nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology (SAB) targeting the back end of line (BEOL) metal line patterning applications for logic nodes beyond 5nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193nm immersion SADP targeting a 40nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, Spin on carbon, spin on glass). The multi-color integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and more generally edge placement error (EPE) as a whole for advanced process nodes. Unbiased LER/LWR analysis comparison between EUV SADP and 193nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open and dielectric etch compared to 193nm immersion SADP, the final process performance is matched in terms of LWR (1.08nm 3 sigma unbiased) and is only 6% higher than 193nm immersion SADP for average unbiased LER. Using EUV SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged, and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.

关键词： Self-aligned block SAB EUV SADP multi-color LER LWR PSD

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Graphoepitaxy integration and pattern transfer of lamellar silicon-containing high-χ block copolymers 7

Graphoepitaxy integration and pattern transfer of lamellar s...

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conference on advanced etch technology for nanopatterning VII

作者： Bezard, P. Chevalier, X. Legrain, A. Navarro, C. Nicolet, C. Fleury, G. Cayrefourcq, I. Tiron, R. Zelsmann, M. Univ Grenoble Alpes CNRS LTM Minatec Campus317 Rue Martyrs F-38000 Grenoble France Grp Rech Lacq ARKEMA F-64170 Lacq France Univ Bordeaux ENSCPB CNRS LCPO F-33607 Pessac France CEA LETI Minatec Campus17 Rue Martyrs F-38000 Grenoble France

ISBN: (数字)9781510616714

ISBN: (纸本)9781510616714

In this work, we present our recent achievements on the integration and transfer etching of a novel silicon-containing high-chi block copolymer for lines/spaces applications. Developed carbo-silane BCPs are synthesized under industrial conditions and present periodicities as low as 14 nm. A full directed self-assembly by graphoepitaxy process is shown using standard photolithography stacks and all processes are performed on 300 mm wafer compatible tools. Specific plasma processes are developed to isolate perpendicular lamellae and sub-12 nm features are finally transferred into silicon substrates. The quality of the final BCP hard mask (CDU, LWR, LER) are also investigated. Finally, thanks to the development of dedicated neutral layers and top-coats allowing perpendicular orientations, it was possible to investigate plasma etching experiments on full-sheets at 7 nm resolution, opening the way to the integration of these polymers in chemoepitaxy stacks.

关键词： directed self-assembly (DSA) block copolymers (BCPs) PS-b-PDMSB high-chi plasma etching graphoepitaxy

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Self-Aligned Blocking integration Demonstration for Critical sub 40nm pitch Mx Level Patterning 6

Self-Aligned Blocking Integration Demonstration for Critical...

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SPIE conference on advanced etch technology for Nano-patterning VI (SPIE etch) held as Part of the International Symposium on advanced Lithography

作者： Raley, Angelique Mohanty, Nihar Sun, Xinghua Farrell, Richard A. Smith, Jeffrey T. Ko, Akiteru Metz, Andrew W. Biolsi, Peter Devilliers, Anton America LLC TEL Technol Ctr Albany NY 12203 USA

ISBN: (纸本)9781510607491;9781510607491

Multipatterning has enabled continued scaling of chip technology at the 28nm node and beyond. Self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as well as Litho-etch/Litho-etch (LELE) iterations are widely used in the semiconductor industry to enable patterning at sub 193 immersion lithography resolutions for layers such as FIN, Gate and critical Metal lines. Multipatterning requires the use of multiple masks which is costly and increases process complexity as well as edge placement error variation driven mostly by overlay. To mitigate the strict overlay requirements for advanced technology nodes (7nm and below), a self-aligned blocking integration is desirable. This integration trades off the overlay requirement for an etch selectivity requirement and enables the cut mask overlay tolerance to be relaxed from half pitch to three times half pitch. Self-alignement has become the latest trend to enable scaling and self-aligned integrations are being pursued and investigated for various critical layers such as contact, via, metal patterning. In this paper we propose and demonstrate a low cost flexible self-aligned blocking strategy for critical metal layer patterning for 7nm and beyond from mask assembly to low -K dielectric etch. The integration is based on a 40nm pitch SADP flow with 2 cut masks compatible with either cut or block integration and employs dielectric films widely used in the back end of the line. As a consequence this approach is compatible with traditional etch, deposition and cleans tools that are optimized for dielectric etches. We will review the critical steps and selectivities required to enable this integration along with bench-marking of each integration option (cut vs. block).

关键词： etching Dielectrics Optical lithography Metals System on a chip Plasma Photomasks Plasma etching Lithography Back end of line Double patterning technology Immersion lithography Optical alignment Overlay metrology Semiconductors

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NanoImprint, DSA and Multi-Beam Lithography: Patterning Technologies with New integration Challenges 6

NanoImprint, DSA and Multi-Beam Lithography: Patterning Tech...

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SPIE conference on advanced etch technology for Nano-patterning VI (SPIE etch) held as Part of the International Symposium on advanced Lithography

作者： Landis, S. Teyssedre, H. Claveau, G. Servin, I. Delachat, F. Pourtreau, M. L. Gharbi, A. Barros, P. Pimenta Tiron, R. Nouri, L. Posseme, N. May, M. Brianceau, P. Barnola, S. Blancquaert, Y. Pradelles, J. Essomba, P. Bernadac, A. Dal'zotto, B. Bos, S. Argoud, M. Chamiot-Maitral, G. Sarrazin, A. Tallaron, C. Lapeyre, C. Pain, L. CEA LETI Minatec Campus17 Rue Martyrs Grenoble F-38054 Grenoble 9 France

ISBN: (纸本)9781510607491;9781510607491

Through three collaborative R&D programs, IDEAL for Directed Self-Assembly Lithography, IMAGINE for Massively Parallel Electron Beam Lithography and INSPIRE for NanoImprint Lithography, CEA-LETI is currently assessing and boosting the development of these alternative technologies through strategic partnerships and innovative mix of them. This paper will present the latest process developments achieved on both chemically and non-Chemically Amplified Resist exposed with a low accelerating voltage (5 kV) exposure platform developed by Mapper Lithography. Several approaches will be presented to manage the Resolution-Sensitivity-Line Width Roughness challenge as well as the etching transfer in the underneath stacks required at the 28 nm node. For the Directed Self-Assembly (DSA) of Block Copolymers (BCP) patterning solution, even if it is considered as a promising patterning solutions due to its simplicity, low cost of processing and capability to generate high density patterns, some challenges (DSA-friendly design, low defectivity and accurate placement error) still need to be addressed for a complete adoption of DSA in manufacturing. We propose to discuss the advanced integration flows using DSA of block copolymer for PS-PMMA materials, like "DSA planarization" approach and also surface guide affinity tuning. Then, NIL wafer scale technology will be assessed thought CDU and printed resist feature height measurements. These result will underline the key process parameters that will define the integration scheme of such technology in high volume manufacturing. This paper will also highlight the specific metrology requirements and method needed to properly evaluate such patterning technology.

关键词： Directed self assembly Lithography Line width roughness Nanoimprint lithography Semiconducting wafers etching Electron beam lithography System on a chip Critical dimension metrology Photoresist processing

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Optical metrology for advanced process control: full module metrology solutions 5

Optical metrology for advanced process control: full module ...

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SPIE conference on advanced etch technology for nanopatterning V held as part of the International Symposium on advanced Lithography

作者： Bozdog, Cornel Turovets, Igor ReVera Inc 3090 Oakmead Village Dr Santa Clara CA 95051 USA Nova Measuring Instruments LTD Weizmann Sci Pk IL-7610201 Rehovot Israel

ISBN: (纸本)9781510600171

Optical metrology is the workhorse metrology in manufacturing and key enabler to patterning process control. Recent advances in device architecture are gradually shifting the need for process control from the lithography module to other patterning processes (etch, trim, clean, LER/LWR treatments, etc..). Complex multi-patterning integration solutions, where the final pattern is the result of multiple process steps require a step-by-step holistic process control and a uniformly accurate holistic metrology solution for pattern transfer for the entire module. For effective process control, more process "knobs" are needed, and a tighter integration of metrology with process architecture.

关键词： OCD scatterometry reference metrology hybrid metrology APC in-situ integrated metrology

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Reactive ion etching challenges for half-pitch sub-10-nm line-and-space pattern fabrication using directed self-assembly lithography 5

Reactive ion etching challenges for half-pitch sub-10-nm lin...

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SPIE conference on advanced etch technology for nanopatterning V held as part of the International Symposium on advanced Lithography

作者： Kasahara, Yusuke Seino, Yuriko Sato, Hironobu Kubota, Hitoshi Kanai, Hideki Kihara, Naoko Minegishi, Shinya Miyagi, Ken Tobana, Toshikatsu Shiraishi, Masayuki Kobayashi, Katsutoshi Kodera, Katsuyoshi Yamano, Hitoshi Kawamonzen, Yoshiaki Azuma, Tsukasa EUVL Infrastruct Dev Ctr Inc DSA Res Dept 16-1 Onogawa Tsukuba Ibaraki 3058569 Japan

ISBN: (纸本)9781510600171

Directed self-assembly is a candidate process for sub-15-nm patterning applications. It will be necessary to develop the DSA process fully and consider process integration to adapt the DSA process for use in semiconductor manufacturing. We investigated the reactive ion etching (RIE) process for the fabrication of sub-10-nm metal wires using the DSA process and the process integration requirements for electrical yield verification. We evaluated the process using an organic high-chi block copolymer (BCP) with a lamellar structure. One critical issue during DSA pattern transfer involves the BCP bottom connection. The BCP bottom connections could be removed without BCP mask loss by using the optimum bias power and the optimum BCP film thickness. The sub-10-nm DSA line-and-space (L/S) patterns were successfully transferred to a SiO2 layer with sufficient film thickness for the fabrication of the metal wire. We also evaluated the overlay technique used in the process. The connect patterns and cut patterns were overlaid on 10-nm trenches fabricated by the DSA process.

关键词： directed self-assembly high-chi BCP line-and-space pattern pattern transfer DSA process integration metal wire electrical yield verification

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Self-aligned Quadruple Patterning integration using spacer on spacer pitch splitting at the resist level for sub 32nm pitch applications 5

Self-aligned Quadruple Patterning Integration using spacer o...

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SPIE conference on advanced etch technology for nanopatterning V held as part of the International Symposium on advanced Lithography

作者： Raley, Angelique Thibaut, Sophie Mohanty, Nihar Subhadeep, Kal Nakamura, Satoru Ko, Akiteru O'Meara, David Tapily, Kandabara Consiglio, Steve Biolsi, Peter America LLC TEL Technol Ctr Albany NY 12203 USA

ISBN: (纸本)9781510600171

Multiple patterning integrations for sub 193nm litho pitch resolution are becoming increasingly creative in pursuit of cost reduction and achieving desired critical dimension. Implementing these schemes into production can be a challenge. Aimed at reducing cost associated with multiple patterning for the 10nm node and beyond, we will present a self-aligned quadruple patterning strategy which uses 193nm immersion lithography resist pattern as a first mandrel and a spacer on spacer integration to enable a final pitch of 30nm. This option could be implemented for front end or back end critical layers such as Fin and Mx. Investigation of combinations of low temperature ALD films such as TiO, Al2O3 and SiO2 will be reviewed to determine the best candidates to meet the required selectivities, LER/LWR andCDs. Several challenges arise with spacer on spacer pitch splitting such as first spacer shape impact on second spacer deposition profile and final etch profiles as well as pitch walking control. In this paper we will highlight the unique etch challenges associated with spacer on spacer SAQP patterning strategy and summarize our efforts in optimizing the patterning stack, etch chemistries and process steps to provide a viable alternative to other conventional multiple patterning schemes. We will compare this new integration scheme with previously presented SAQP flows and show the benefits / disadvantages of pursuing this new strategy in terms of LER/LWR performance, CD targeting, final etch profiles and cost benefits.

关键词： etching Optical lithography Silicon Plasma Silica Atomic layer deposition Line width roughness Titanium dioxide Photoresist materials Semiconducting wafers

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Plasma etching processes for the integration of InP based compounds on 200mm Si wafer for photonic applications 5

Plasma etching processes for the integration of InP based co...

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SPIE conference on advanced etch technology for nanopatterning V held as part of the International Symposium on advanced Lithography

作者： Pargon, E. Gay, G. Petit-Etienne, C. Brihoum, M. Bizoueme, M. Burtin, P. Barnola, S. Univ Grenoble Alpes CNRS CEA Leti Minatec LTM 17 Rue Martyrs F-38054 Grenoble France CEA Leti 17 Rue Martyrs F-38054 Grenoble 9 France

ISBN: (纸本)9781510600171

Ar/Cl-2/CH4 gas mixture has been investigated for the development of plasma etching process dedicated to the patterning of 3 mu m-deep InP structures integrated on 200mm SiO2 carrier wafer. The plasma process requirements are: high InP etch rates (>***(-1)), high InP/SiO2 selectivity (>40), anisotropic profiles and smooth bottom and sidewalls surfaces. The process development mainly focuses on the impact of the gas ratio and gas flow on the etch rates, selectivity, pattern profile and surface roughness. It is demonstrated that the CH4 flow drives the process performance and that by adjusting it properly, a narrow process window provides acceptable selectivity of 25, anisotropic profiles and smooth surface. The difficulty of the process development using Ar/Cl-2/CH4 gas mixture is to combine high InP/SiO2 selectivity and anisotropic profiles since to passivate efficiently the InP sidewalls and prevent from lateral etching, it seems that a SiOC like deposition is needed, which is only possible if the SiO2 wafer is etched.

关键词： InP plasma etching hybrid III-V/Si photonic integrated circuit

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RIE challenges for sub-15 nm line-and-space patterning using directed self-assembly lithography with coordinated line epitaxy (COOL) process 4

RIE challenges for sub-15 nm line-and-space patterning using...

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SPIE conference on advanced etch technology for nanopatterning IV held as part of the International Symposium on advanced Lithography

作者： Kasahara, Y. Seino, Y. Kobayashi, K. Kanai, H. Sato, H. Kubota, H. Tobana, T. Minegishi, S. Miyagi, K. Kihara, N. Kodera, K. Shiraishi, M. Kawamonzen, Y. Nomura, S. Azuma, T. EUVL Infrastruct Dev Ctr Inc Tsukuba Ibaraki 3058569 Japan

ISBN: (纸本)9781628415308

Directed self-assembly (DSA) is one of the promising candidates for next-generation lithography. We developed a novel simple sub-15 nm line-and-space (L/S) patterning process, the "coordinated line epitaxy (COOL) process," using grapho-and chemo-hybrid epitaxy. In this study we evaluate the DSA L/S pattern transfer margin. Since defect reduction is difficult in the case of the DSA pattern transfer process, there is a need to increase the pattern transfer margin. We also describe process integration for electrical yield verification.

关键词： directed self-assembly pattern transfer reactive ion etching process margin roughness defect COOL process electrical yield verification

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