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51 篇 会议

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检索条件"任意字段=Conference on Advanced Etch Technology and Process Integration for Nanopatterning XIII"

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Challenges and mitigation strategies for resist trim etch in resist-mandrel based SAQP integration scheme 4

Challenges and mitigation strategies for resist trim etch in...

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SPIE conference on advanced etch technology for nanopatterning IV held as part of the International Symposium on advanced Lithography

作者： Mohanty, Nihar Franke, Elliott Liu, Eric Raley, Angelique Smith, Jeffrey Farrell, Richard Wang, Mingmei Ito, Kiyohito Das, Sanjana Ko, Akiteru Kumar, Kaushik Ranjan, Alok Meara, Dave O' Nawa, Kenjiro Scheer, Steven DeVillers, Anton Biolsi, Peter America LLC TEL Technol Ctr Albany NY 12203 USA

ISBN: (纸本)9781628415308

Patterning the desired narrow pitch at 10nm technology node and beyond, necessitates employment of either extreme ultra violet (EUV) lithography or multi-patterning solutions based on 193nm-immersion lithography. With enormous challenges being faced in getting EUV lithography ready for production, multi-patterning solutions that leverage the already installed base of 193nm-immersion-lithography are poised to become the industry norm for 10 and 7nm technology nodes. For patterning sub-40nm pitch line/space features, self-aligned quadruple patterning (SAQP) with resist pattern as the first mandrel shows significant cost as well as design benefit, as compared to EUV lithography or other multi-patterning techniques. One of the most critical steps in this patterning scheme is the resist mandrel definition step which involves trimming /reformation of resist profile via plasma etch for achieving appropriate pitch after the final pattern. Being the first mandrel, the requirements for the Line Edge Roughness (LER)/Line Width Roughness (LWR);critical dimension uniformity (CDU);and profile in 3-dimensions for the resist trim /reformation etch is extremely aggressive. In this paper we highlight the unique challenges associated in developing resist trim/reformation plasma etch process for SAQP integration scheme and summarize our efforts in optimizing the trim etch chemistries, process steps and plasma etch parameters for meeting the mandrel definition targets. Finally, we have shown successful patterning of 30nm pitch patterns via the resist-mandrel SAQP scheme and its implementation for Si-fin formation at 7nm node.

关键词： etching Lithography Optical lithography Plasma etching Vacuum ultraviolet Line edge roughness Plasma Semiconducting wafers Line width roughness Photomasks

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Spectral analysis of the linewidth and line edge roughness transfer during a self-aligned double patterning process 4

Spectral analysis of the linewidth and line edge roughness t...

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SPIE conference on advanced etch technology for nanopatterning IV held as part of the International Symposium on advanced Lithography

作者： Dupuy, E. Pargon, E. Fouchier, M. Grampeix, H. Pradelles, J. Darnon, M. Pimenta-Barros, P. Barnola, S. Joubert, O. Uni Grenoble Alpes CNRS CEA LTM F-38054 Grenoble 9 France CEA LETI F-38054 Grenoble 9 France

ISBN: (纸本)9781628415308

We report a 20 nm half-pitch self-aligned double patterning (SADP) process based on a resist-core approach. Line/space 20/20 nm features in silicon are successfully obtained with CDvariation, LWR and LER of 0.7 nm, 2.4 nm and 2.3 nm respectively. The LWR and LER are characterized at each technological step of the process using a power spectral density fitting method, which allows a spectral analysis of the roughness and the determination of unbiased roughness values. Although the SADP concept generates two asymmetric populations of lines, the final LWR and LER are similar. We show that this SADP process allows to decrease significantly the LWR and the LER of about 62% and 48% compared to the initial photoresist patterns. This study also demonstrates that SADP is a very powerful concept to decrease CD uniformity and LWR especially in its low-frequency components to reach sub-20 nm node requirements. However, LER low-frequency components are still high and remain a key issue to address for an optimized integration.

关键词： SADP LER LWR spectral analysis PSD CD-SEM

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A way to integrate multiple block layers for middle of line contact patterning 4

A way to integrate multiple block layers for middle of line ...

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SPIE conference on advanced etch technology for nanopatterning IV held as part of the International Symposium on advanced Lithography

作者： Kunnen, E. Demuynck, S. Brouri, M. Boemmels, J. Versluijs, J. Ryckaert, J. IMEC B-3001 Heverlee Belgium Lam Res Corp B-3001 Heverlee Belgium

ISBN: (纸本)9781628415308

It is clear today that further scaling towards smaller dimensions and pitches requires a multitude of additional process steps. Within this work we look for solutions to achieve a middle of line 193i based patterning scheme for N7 logic at a contacted poly pitch of 40-45 nm. At these pitches, trenches can still be printed by means of double patterning. However, they need to be blocked at certain positions because of a limited line end control below 90 nm pitch single print. Based on the 193i patterning abilities, the proposed SRAM (Static Random Access Memory) cell requires 5 blocking layers. Integrating 5 blocking layers is a new challenge since down to N10 one blocking layer was usually sufficient. The difficulty with multiple blocking layers is the removal of the masked parts, especially in cases of overlap. As a solution a novel patterning approach is proposed and tried out on relaxed dimensions (patent pending). The proposed solution is expected not to be sensitive to the number of blocking layers used, and tolerates their overlap. The stack is constructed to be compatible with N7 substrates such as SiGe or P: Si. Experimental results of the stack blocking performance on relaxed pitch will be presented and discussed.

关键词： N7 N10 block patterning integration scheme SRAM MOL contact multiple

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Effect of etch pattern transfer on local overlay (OVL) margin in 28nm gate integration

Effect of etch pattern transfer on local overlay (OVL) margi...

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conference on advanced etch technology for nanopatterning III held as part of the SPIE advanced Lithography Symposium

作者： Ros, Onintza Gouraud, Pascal Le-Gratiet, Bertrand Gardin, Christian Ducote, Julien Pargon, Erwine STMicroelectronics F-38926 Crolles France LTM CNRS Grenoble France

ISBN: (纸本)9780819499776

One of the main process control challenges in logic process integration is the contact to gate overlay. Usual ways for overlay control are run to run corrections (high order process corrections) and scanner control (baseliner control loop) to keep overlay within the very tight ITRS specifications, i.e. 7nm mean+3sigma. It is known that process integration can lead to specific overlay distortion (CMP, thermal treatment etc.) which are usually partly handled by high order process corrections at scanner level. In addition, recently we have shown that etch process can also lead to local overlay distortions, especially at the wafer edge [1]. In this paper we look into another overlay distortion level which can happen during etch processes. We will show that resist cure steps during gate patterning affect lithography defined profiles leading to local pattern shifting. This so called gate shifting has been characterized by etch process partitioning during a typical high-K metal gate patterning with spinon carbon and Si-ARC lithography stack onto a high-K metal gate /poly-silicon /oxide hard mask stack. We will show that modifying the resist-cure /Si-ARC open chemistry strongly contributes to gate shifting reduction by an equivalent of 40% overlay margin reduction.

关键词： overlay pattern shifting etch gate patterning

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Precision integrated thickness control with gas cluster ion beam etch

Precision integrated thickness control with gas cluster ion ...

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conference on advanced etch technology for nanopatterning III held as part of the SPIE advanced Lithography Symposium

作者： Russell, N. M. Gizzo, V. LaRose, J. D. Pfeifer, B. D. Dasaka, R. Economikos, L. Wise, R. TEL Technol Ctr Amer LLC TEL Epion Inc 225 Fuller RdSte 214 Albany NY 12203 USA IBM Syst & Technol Grp Hopewell Jct NY 12533 USA

ISBN: (纸本)9780819499776

Gas cluster ion beam (GCIB) etching is a technique, which among other attributes, enables advanced process control of feature height uniformity, increasingly critical to sub 16nm FINFET performance. GCIB can have a high local etch rate in a focused beam, which combined with location specific processing (LSP) algorithms, enables high-precision correction of incoming or downstream thickness uniformity. Applications of this technique include trimming of RF filter devices (in production now for over 10 years), as well as emerging applications in thickness control enabling for FINFET device integration. Here we describe the GCIB etch technology and the LSP method and capabilities.

关键词： Gas cluster ion beam GCIB Location specific processing LSP

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Large-Radius Neutral Beam Enhanced Chemical Vapor Deposition process for Non-Porous Ultra-low-k SiOCH

Large-Radius Neutral Beam Enhanced Chemical Vapor Deposition...

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conference on advanced etch technology for nanopatterning III held as part of the SPIE advanced Lithography Symposium

作者： Kikuchi, Yoshiyuki Sakakibara, Yasuaki Samukawa, Seiji Tokyo Electron Ltd TEL Technol Ctr Sendai Izumi Ku 3-2-1 Osawa Sendai Miyagi Japan Tohoku Univ Inst Fluid Sci Aoba Ku Sendai Miyagi 9808577 Japan Tohoku Univ Adv Inst Mat Res World Premier Int Ctr Initiat Aoba Ku Sendai Miyagi 9808577 Japan

ISBN: (纸本)9780819499776

Pores in ultra-low-k carbon-doped silicon oxide (SiOCH) film have been a serious problem because they produce fragile film strength, with the film incurring damage from integration and diffusion of Cu atoms in thermal annealing. To address this problem, we developed a practical large-radius neutral beam enhanced CVD process to precisely control the film structure so as to eliminate any pores in the film. We used the process with dimethoxy-tetramethyl-disiloxane (DMOTMDS) as a precursor to form a SiOCH film on an 8-inch Si wafer and obtained a non-porous film having an ultra-low k-value of 2.2 with sufficient modulus (> 10 GPa). Analyzing the film structure by experimental and theoretical techniques showed that symmetric polymethylsilaxane (PMS) chains were grown and cross-linked to each other in the film. This particular film did not incur any damage from acid or alkali solution or oxygen plasma. Furthermore, the dense film almost completely resisted Cu diffusion into it during thermal annealing.

关键词： porous low-k Interconnect SiOCH neutral beam CVD microwave plasma

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etch challenges for DSA implementation in CMOS via patterning

Etch challenges for DSA implementation in CMOS via patternin...

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conference on advanced etch technology for nanopatterning III held as part of the SPIE advanced Lithography Symposium

作者： Barros, P. Pimenta Barnola, S. Gharbi, A. Argoud, M. Servin, I. Tiron, R. Chevalier, X. Navarro, C. Nicolet, C. Lapeyre, C. Monget, C. Martinez, E. CEA LETI 17 Rue Martyrs F-38054 Grenoble France ARKEMA FRANCE F-64170 Lacq France ST Microlect F-38920 Crolles France

ISBN: (纸本)9780819499776

This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer's Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti's 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching.

关键词： block copolymer PS-b-PMMA contact-hole shrink PMMA removal CMOS integration etching

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advanced Plasma etch for the 10nm node and Beyond

Advanced Plasma Etch for the 10nm node and Beyond

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2nd advanced etch technology for nanopatterning conference (AETNC) held as part of the SPIE advanced Lithography Symposium

作者： Joseph, E. A. Engelmann, S. U. Miyazoe, H. Bruce, R. L. Nakamura, M. Suzuki, T. Hoinkis, M. IBM Corp TJ Watson Res Ctr Yorktown Hts NY USA

ISBN: (纸本)9780819494672

As 14nm node devices begin to permeate into the semiconductor industry, it is becoming increasingly evident that continued pitch scaling is getting more complex throughout the FEOL, MOL and BEOL. The adoption of patterning schemes and pitch splitting techniques such as double exposure/double etch and sidewall image transfer (SIT) are already underway to extend 193nm immersion lithography and enable 3D FinFET / Trigate devices. In addition, BEOL scaling of damascene copper is facing its own challenges, between the patterning and integration of porous ULK materials and the issue of increased resistivity emanating from grain boundary and surface scattering. As such, this paper will present work on novel etch methods envisioned to enable the successful extension of patterning and device integration for the 10nm node and beyond. Work related to the exploration of novel feedgas chemistries to extend etch performance for SiN spacer and oxide etch applications will be reviewed in detail. Specifically, the realization of a silicon nitride etch process which no longer depends on an oxidation mechanism, but rather a polymerization based etch mechanism will be shown. The process exhibits high selectivity to SiO2, Si and photoresist and results in reduced SOI loss while simultaneously maintaining all SiN on the gate sidewall and significantly reducing SiN footing. In addition, the feasibility of novel patterning methods such as the introduction of subtractive etching of copper will be reviewed in detail. Subtractive etching of Cu has the potential to overcome current interconnect integration difficulties by enabling blanket Cu film deposition with large grains, and by minimizing plasma damage during ULK etch, respectively. Successful patterning of copper at 25-50nm critical dimension (CD) with smaller than 100nm in pitch is demonstrated using a novel high density plasma based dry etch process.

关键词： etching Copper Optical lithography Plasma etching Plasma Silicon Sputter deposition Oxides Back end of line Argon

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Yield enhancement of 3D flash devices through broadband brightfield inspection of the channel hole process module

Yield enhancement of 3D flash devices through broadband brig...

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2nd advanced etch technology for nanopatterning conference (AETNC) held as part of the SPIE advanced Lithography Symposium

作者： Lee, Jung-Youl Seo, Il-Seok Ma, Seong-Min Kim, Hyeon-Soo Kim, Jin-Woong Kim, Dooh Cross, Andrew SK Hynix Inc Icheon Si 467701 Gyeonggi Do South Korea

ISBN: (纸本)9780819494672

The migration to a 3D implementation for NAND flash devices is seen as the leading contender to replace traditional planar NAND architectures. However the strategy of replacing shrinking design rules with greater aspect ratios is not without its own set of challenges. The yield-limiting defect challenges for the planar NAND front end were primarily bridges, protrusions and residues at the bottom of the gates, while the primary challenges for front end 3D NAND is buried particles, voids and bridges in the top, middle and bottom of high aspect ratio structures. Of particular interest are the yield challenges in the channel hole process module and developing an understanding of the contribution of litho and etch defectivity for this challenging new integration scheme. The key defectivity and process challenges in this module are missing, misshapen channel holes or under-etched channel holes as well as reducing noise sources related to other none yield limiting defect types and noise related to the process integration scheme. These challenges are expected to amplify as the memory density increases. In this study we show that a broadband brightfield approach to defect monitoring can be uniquely effective for the channel hole module. This approach is correlated to end-of-line (EOL) Wafer Bin Map for verification of capability.

关键词： 3D NAND FLASH memory Channel hole Yield enhancement Defect inspection Defect reduction

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Patterning and etch challenges for future DRAM and other high aspect ratio memory device fabrication

Patterning and etch challenges for future DRAM and other hig...

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2nd advanced etch technology for nanopatterning conference (AETNC) held as part of the SPIE advanced Lithography Symposium

作者： Rueger, N. R. McGinnis, A. Good, F. Schrinsky, A. J. Kiehlbauch, M. Micron Technol Inc Boise ID 83707 USA

ISBN: (纸本)9780819494672

Current challenges are outlined for masking materials that enable future high aspect ratio (AR> 25) etch requirements. At such high aspect ratios, and 20nm to 30nm feature sizes, ion energy flux loss due to sidewall collisions, feature gap necking, polymerization, and feature charging in deep via-like structures has driven etch process conditions into very high bias voltage regimes. At these ion energies (keV), lateral removal of mask material due to faceting is the dominating mask erosion mechanisms. Using carbon as our baseline hard mask film, we present here normalized performance comparisons of 13 alternative films. We demonstrate that feature CD changes that correlate to lateral mask loss on the test structure also correlate to lateral mask loss on a real patterned structure and that we can therefore use these test structures as a tool for hard mask film evaluation without having the capability to pattern the hard mask under investigation. We propose that such test structures can be a valuable tool for film development as they relate to hard mask applications in dry etch patterning, and should be used in future development efforts rather than the more classical methods of blanket etch rate analysis. Such test structures can also be used to study film etch properties in general and we show that they are capable of capturing ARDE and sputter redeposition phenomena. Correlations between surface loss/addition as a function of sidewall position are presented and results of in-practice applications are shown. Key issues for future hard mask film implementation are discussed from the perspective of photo patterning, dry etching, wet etching, and integration.

关键词： etching Data centers Ions Optical lithography Carbon Critical dimension metrology Sputter deposition Argon Dry etching Wet etching

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