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检索条件"任意字段=Conference on Advanced Etch Technology for Nanopatterning IX"

共 96 条记录，以下是1-10 订阅

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Green Chemistry for SiN etch 13

Green Chemistry for SiN Etch

引用

conference on advanced etch technology and Process Integration for nanopatterning XIII

作者： Stafford, Nathan Jennings, Colin Biltek, Scott Phong Nguyen Yao, Yichen Amer Air Liquide Inc 200 GBC Dr Newark DE 19702 USA

ISBN: (纸本)9781510672239;9781510672222

Over the past few years, numerous countries and semiconductor manufacturing entities have unveiled their commitments to achieving net-zero carbon emissions by 2050 or even sooner. When it comes to manufacturing chips, plasma etch processes contribute significantly to emissions, especially in dielectric etching. These processes typically involve the use of high global warming potential (GWP) fluorocarbon gasses like CHF3, CF4, and CH2F2. Air Liquide's research and development (R&D) endeavors have led to the creation of multiple alternative etch chemistries for SiN and SiO2 etching applications that boast remarkably low GWPs. Despite strides in developing these alternative chemistries, accurately forecasting the gases emitted post-plasma remains elusive. The complexities inherent in the breakdown and recombination processes within the plasma make it challenging to predict the specific emissions, regardless of whether the gas introduced into the plasma etch chamber carries a high or low GWP. This research showcases the utilization of Fourier Transform Infrared Spectroscopy (FTIR) to analyze and measure the emission gas stream from the plasma etch chamber. Moreover, the innovative chemistries developed by Air Liquide have exhibited enhanced etch performance while resulting in lower CO2 equivalent emissions compared to the current baseline in dielectric etching

关键词： Emissions GWP etch

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Dry etch Challenges for Patterning Middle-of-line (MOL) Contact Trench in Monolithic CFET (complementary FET) 13

Dry Etch Challenges for Patterning Middle-of-line (MOL) Cont...

引用

conference on advanced etch technology and Process Integration for nanopatterning XIII

作者： Sarkar, T. Radisic, D. Gonzalez, V. Vega Stiers, K. Sheng, C. Montero, D. Jenkins, H. Demand, M. Wang, P. Lazzarino, F. Horiguchi, N. IMEC Kapeldreef 75 B-3001 Leuven Belgium TEL Technol Ctr Amer LLC Albany NY 12203 USA Tokyo Elect Europe Ltd Kapeldreef 75 B-3001 Leuven Belgium

ISBN: (纸本)9781510672239;9781510672222

In a complementary FET (CFET), n- and p-type transistors are stacked on top of each other to enable device scaling. This stacking approach requires very high aspect ratio vertical feature pattering, namely, active gate, spacer source/drain cavity and contact patterning. We report contact trench patterning and plasma etch process development for contacting bottom and top transistors relevant to middle-of-line (MOL) integration in monolithic nanosheet based CFET. First, deep trenches (M0) with aspect ratio (AR) similar to 13 - 15 are etched into SiO2 dielectric layer between tall gates for routing bottom device. After the formation of bottom device, MOL contact patterning (M0T, AR similar to 8 - 9) for top device is performed. The main etch challenges are to preserve gate and gate spacer (SiN) and achieve good depth uniformity, especially when the M0 trench CD is reduced at tight pitches. At pitch 50nm, M0 etch development results are shown for four different etch processes (named as etch Recipe 1 - 4) in which M0 etch depth is increased gradually targeting minimal SiN loss. To reduce gate spacer (SiN) loss, fluorocarbon plasma passivation and hydrocarbon polymer deposition step is used during M0 trench patterning.

关键词： CFET plasma dry etch contact patterning passivation selectivity

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Active area patterning for CFET - Nanosheet etch 13

Active area patterning for CFET - Nanosheet etch

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conference on advanced etch technology and Process Integration for nanopatterning XIII

作者： Brissonneau, V. Koo, Il Gyo Hosseini, M. Batuk, D. Veloso, A. Mannaert, G. Lazzarino, F. IMEC Kapeldreef 75 B-3001 Heverlee Belgium

ISBN: (纸本)9781510672239;9781510672222

Nanosheet device architectures such as complementary FET (CFET) are candidates to replace FinFET, improving device performance while allowing a higher density of devices for a similar footprint. Two main challenges can be highlighted in the definition of the active area (AA) patterning for CFET. First the presence of stacked nanosheets generates the need for a higher aspect-ratio compared to FinFET. Secondly, the nanosheets layers, composed of silicon and silicon-germanium with varied thicknesses and concentrations, require new approaches in terms of process definition and control. The first results of an active area patterning for a full CFET device have been demonstrated at imec. Thicker nanosheet stacks are patterned opening the path to the creation of a complete CFET device.

关键词： CFET Nanosheet Active Area

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Investigation of the Influence of Hardmask Morphology on Bowing Effect in Nano-scale Silicon Plasma etching Process 13

Investigation of the Influence of Hardmask Morphology on Bow...

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conference on advanced etch technology and Process Integration for nanopatterning XIII

作者： Hu, Ziyi Li, Junjie Shao, Hua Chen, Rui Wei, Yayi Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuit Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China

ISBN: (纸本)9781510672239;9781510672222

Bowing is one of plasma etching effects that negatively impact device performance. Although there has been plenty of research work on micro-feature surface etch modeling to investigate bowing effect, limited research has been reported on the influence of hardmask morphology on bowing effect. In this paper, we present a plasma etching model based on Monte Carlo simulation with cellular method in order to simulate the feature profile evolution of etching process in nano-scale. The relationship among hardmask angle, open CD and distribution of reflected ion flux on the sidewall from the opposite hardmask was calculated. The reflected ion flux was heavily concentrated in the upper part of the sidewall in the case of a tapered hardmask, and this was the main mechanism of the bowing formation. This model considers chemical reactions and a novel particle reflection algorithm which is a prominent mechanism. This model is capable of reproducing the feature in periodic dense trenches with dimension of tens of nanometers. The hardmask morphology considered in our study includes hardmask angle (theta) and pattern (CD and pitch). As the hardmask angle decreases, the bowing becomes severe, when CD equals to 90nm and theta equals to 70 degrees, the bowing deviation (D=(W-CD)/2) and relative deviation (Delta D=D/CDx100 %) are 23.86nm (26.51 %). In contrast, as the CD increases, the bowing becomes slight. However, bowing moves toward the bottom of the hole as the CD increases. When CD equals to 150nm and theta equals to 70 degrees, the bowing deviation is 18.95nm (12.63 %). Accordingly, a vertical hardmask is very important for a small CD trench.

关键词： plasma etching etch model bowing hardmask morphology particle reflection

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Metalens Manufacturing Complexities and Costs 13

Metalens Manufacturing Complexities and Costs

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conference on advanced etch technology and Process Integration for nanopatterning XIII

作者： Melvin, Lawrence S., III Chalony, Maryvonne Dawes, Andrew M. C. Kuechler, Bernd Zimmermann, Rainer Viasnoff, Emilie Zhou, Ying Blais, Al Synopsys EV Pole Act Hyerois 1128 F-83400 Hyeres France Synopsys GmbH Karl Hammerschmidt Str 34 D-85609 Aschheim Dornach Germany Synopsys Inc 675 Almanor Ave Sunnyvale CA 94085 USA Synopsys Inc 2025 Cornelius Pass Rd Hillsboro OR 97124 USA Synopsys Inc 400 Execut BlvdSuite 101 Ossining NY 10562 USA

ISBN: (纸本)9781510672239;9781510672222

Background: Metalenses are flat devices that focus and manipulate optical waves. Unlike reflective and refractive optics, metalenses rely on phase shifts introduced by subwavelength metastructures. Aim: Demonstrate the cost and performance impact of using manufactured metaatoms from two lithography processes to design and manufacture metalenses. Approach: Design two types of metalenses, the first type (ideal) uses an ideal design made up of square metaatoms. This lens design is then simulated using both 193 nm and 248 nm lithography processes. The second type (manufacture-aware) uses a design that is built around metaatom profiles produced by the corresponding lithography process (193 nm and 248 nm respectively). By comparing the performance of these two approaches (ideal and manufacture-aware) we demonstrate the process performance impact can be reduced. Results: Comparing 193 nm and 248 nm processes show a up to a 27% difference in monochromatic metalens performance for a design derived from ideal metaatoms. However, by simulating manufactured metaatoms and using them in the design stage, manufactured metalens performance returns to within 7% of ideal. Conclusions: When designing with manufactured metaatoms rather than ideal metaatoms, metalens performance is similar between both 193 nm and 248 nm processes and manufacture-aware design makes either process viable for visible-light metalens manufacturing.

关键词： Metalens metaatom photolithography reactive ion etch manufacturing process design aware flow

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Patterning spacer source drain cavities in CFET devices 13

Patterning spacer source drain cavities in CFET devices

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conference on advanced etch technology and Process Integration for nanopatterning XIII

作者： Choudhury, S. Mannaert, G. Lima, L. P. B. Demuynck, S. Koo, I. G. Lazzarino, F. IMEC B-3001 Leuven Belgium

ISBN: (纸本)9781510672239;9781510672222

In conventional gate-all-around FET architecture, p-type and n-type devices are stacked on top of each other on separate devices. In Complementary FET (CFET) architecture, n-MOS and p- MOS devices are stacked in the same device on top of each other. This allows for reduction in footprint and power consumption. One of the most high aspect ratio (HAR) patterning in CFET processing comes from patterning of the gate spacer, followed by nanosheet (NSH) patterning. The HAR Spacer Source/Drain cavity area is a Si/SiGe/Dielectric superlattices bringing quite a few patterning challenges. This work discusses the challenges for the spacer opening, optimization of the profile of the source drain (SD) cavity and strategies to improve selectivity with the gate hard mask (HM). The first patterning challenge includes etching of a superlattice consisting of numerous materials, including dielectrics, while maintaining selectivity to HM. This means switching of chemistries to accommodate the patterning of these multilayers. Secondly, this patterning step needs to be highly selective to the gate HM to allow enough margin for downstream processes. The patterning step also needs to deliver vertical cavity profile. All these challenges require us to explore complex etch processes including in-situ isolation, passivation, and other etching sequences. The results and challenges for a fully patterned spacer & SD cavity as demonstrated at Imec are presented in this proceeding.

关键词： CFET HAR Spacer Nanosheet etch

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advanced etch technology for nanopatterning ix

Advanced Etch Technology for Nanopatterning IX

引用

advanced etch technology for nanopatterning ix 2020

ISBN: (纸本)9781510634251

The proceedings contain 14 papers. The topics discussed include: Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning;reduction of systematic defects with machine learning from design to fab;intra-field etch induced overlay penalties;optimal etch recipe prediction for 3D NAND structures;cycling of implantation step and remote plasma process step for nitride spacer etching applications;simulation of photoresist defect transfer through subsequent patterning processes;low damage etching by inductively coupled plasma reactive ion etch (ICP-RIE) and atomic layer etching (ALE) of III-V materials to enable next generation device performance;FEOL dry etch process challenges of ultimate FinFET scaling and next generation device architectures beyond N3;and hydrocarbon layer formation and removal studies on SiN films etched in halogen/hydrofluorocarbon plasmas.

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Tone reversal patterning for advanced technology nodes 11

Tone reversal patterning for advanced technology nodes

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conference on advanced etch technology and Process Integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Schleicher, F. Bekaert, J. Thiam, A. Decoster, S. Blanc, R. Lazzarino, F. Santaclara, J. Garcia Rispens, G. Maslow, M. IMEC Kapeldreef 75 B-3001 Leuven Belgium ASML De Run 6501 NL-5504 DR Veldhoven Netherlands

ISBN: (纸本)9781510649880;9781510649873

As technology nodes continue to scale down, maintaining roughness and defectivity during the pattern transfer becomes more challenging. For the smallest features, Metal-Organic Resists (MOR) are preferred due to their better selectivity than Chemically Amplified Resists (CAR). However, MORs are usually negative tone resists. Primarily based on defectivity reasons, dark field Extreme Ultraviolet (EUV) masks are strongly preferred over light field EUV masks. Therefore, the MOR resist is more suited for pillar patterning than hole patterning. The purpose of this paper is to show that exposing pillars with MOR and converting them into holes can yield better roughness and defectivity than patterning holes with CAR directly. A similar comparison is done for the tone reversal of lines and spaces. It is shown that the Local Critical Dimension Uniformity (LCDU) of holes and the Line Edge Roughness (LER) of lines/spaces are well conserved throughout the tone inversion process.

关键词： hole patterning pillar patterning lines and spaces tone reversal tone inversion LER dry etch LCDU EUV metal-organic resist

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OPC accuracy improvement through deep-learning based etch model 11

OPC accuracy improvement through deep-learning based etch mo...

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conference on advanced etch technology and Process Integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Shi, Weina Zhu, Liang Chen, Yuqian Huang, Jiao Wang, Jinze Xie, Qian Zhang, Bilun Xi, Yunfei Pan, Wenhao Zheng, Yuanxia Fan, Yongfa Cheng, Jin Zhao, Yu Zheng, Leiwu ChangXin Memory Technol Inc Hefei Anhui Peoples R China ASML China Shenzhen 3023 Chuangye Rd Shenzhen Guangdong Peoples R China ASML US 80 W Tasman San Jose CA 95131 USA

ISBN: (纸本)9781510649880;9781510649873

This paper demonstrates a full-chip OPC correction flow based on deep-learning etch model in a DUV litho-etch case. The flow leverages SEM metrology (eP5 fast E-beam tool, ASML- HMI) to collect massive data, automated metrology software (MXP, ASML-Brion) to extract high quality gauges, and deep-learning etch modeling (Newron etch, ASML-Brion) to capture complicated etch behaviors. The model calibration and verification are performed using a combined data from a test and real chip wafer to ensure sufficient pattern coverage. The model performance of Newron etch is benchmarked against a term-based etch model, wherein Newron etch model shows significant accuracy improvement in the model calibration (>50% for test patterns and >35% for real chip pattern). The Newron etch model is proven stable with a comparable performance in the model verification. Particularly, strong loading effects from underlying sublayer are observed in the full chip wafer, and effectively captured by the Newron etch with a sublayer-aware model form. The calibrated Newron etch model is successfully applied in a model-based etch OPC tape-out with new mask design rules but the same litho-etch process conditions. Compared to the term-based model, Newron etch also shows significant accuracy improvement.

关键词： AEI litho-etch bias deep learning etch model sublayer aware high-quality EP gauges fast metrology flow OPC model accuracy and stability etch OPC

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Control of sidewall roughness formation in through-silicon via etch at non-cryogenic temperatures 11

Control of sidewall roughness formation in through-silicon v...

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conference on advanced etch technology and Process Integration for nanopatterning XI Part of SPIE advanced Lithography and Patterning conference

作者： Papalia, John M. Koty, Devi Marchack, Nathan LeFevre, Scott Yang, Qingyun Mosden, Aelan Engelmann, Sebastian U. Bruce, Robert L. IBM TJ Watson Res Ctr 1101 Kitchawan Rd Yorktown Hts NY 10598 USA America LLC TEL Technol Ctr Albany NY USA

ISBN: (纸本)9781510649880;9781510649873

Through-silicon via etch (TSV) is critical to current and future advanced packaging schemes. For heterogeneous integration approaches in particular, where modular components are tightly packed together, these processes play an integral role.1 While etch processes for silicon appear well understood and the frontiers of plasma etch have led us to advanced cyclic processes for device fabrication such as atomic layer etching, TSV applications are fundamentally different due to their relative size and aspect ratio targets. Unlike small-scale etching, TSV feature etching has not shown exponential change over time.(2) To achieve TSV targets such as high etch rate, high aspect ratio, and clean profiles to support filling, known solutions are employed such as cryogenic wafer temperatures(3), alternative hard mask schemes(4), and extremely short gas cycle times(5);these solutions require specialized equipment and/or a more complex integration scheme. We explore the creation of high-aspect ratio, diffusion-limited TSV etches with high PR selectivity (>50:1) and high aspect ratios while simultaneously aiming for a high etch rate all while using non-cryogenic temperatures and a standard photoresist mask. A focus on sidewall profile and sidewall damage is maintained.

关键词： TSV sidewall damage profile aspect ratio selectivity

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