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检索条件"任意字段=Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations XVII"

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Adaptive array beamforming with fixed-point arithmetic matrix inversion using Givens rotations

Adaptive array beamforming with fixed-point arithmetic matri...

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conference on advanced signal processing algorithms, architectures, and implementations XI

作者： Rabinkin, DV Song, W Vai, MM Nguyen, H MIT Lincoln Lab Lexington MA 02420 USA

ISBN: (纸本)0819441880

Adaptive array systems require the periodic solution of the well-known w = (R) over tilde (-1)v equation in order to compute optimum adaptive array weights. The covariance matrix (R) over tilde is estimated by forming a product of noise sample matrices X : (R) over tilde = (XX)-X-H. The operations-count cost of performing the required matrix inversion in real time can be prohibitively high for a high bandwidth system with a large number of sensors. Specialized hardware may be required to execute the requisite computations in real time. The choice of algorithm to perform these computations must be considered in conjunction with the hardware technology used to implement the computation engine. A systolic architecture implementation of the Givens rotation method for matrix inversion was selected to perform adaptive weight computation. The bit-level systolic approach enables a simple ASIC design and a very low power implementation. The bit-level systolic architecture must be implemented with fixed-point arithmetic to simplify the propagation of data through the computation cells. The Givens rotation approach has a highly parallel implementation and is ideally suited for a systolic implementation. Additionally, the adaptive weights are computed directly from the sample matrix X in the voltage domain, thus reducing the required dynamic range needed in carrying out the computations. An analysis was performed to determine the required fixed-point precision needed to compute the weights for an adaptive array system operating in the presence of interference. Based on the analysis results. it was determined that the precision of a floating-point computation can be well approximated with a 13-bit to 19-bit word length fixed point computation for typical system jammer-to-noise levels. This property has produced an order-of-magnitude reduction in required hardware complexity. A synthesis-based ASIC design process was used to generate preliminary layouts. These layouts were used t

关键词： Very large scale integration Chemical elements Computing systems Sensors Statistical analysis Computer architecture Matrices Radar Electroluminescence signal processing

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Superresolution imaging: a survey of current techniques

Superresolution imaging: a survey of current techniques

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conference on advanced signal processing algorithms, architectures, and Implementantions xviiI

作者： Cristobal, G. Gil, E. Sroubek, F. Flusser, J. Miravet, C. Rodriguez, F. B. CSIC Inst Opt Serrano 121 E-28006 Madrid Spain ASCR Inst Informat Theory & Automat Prague Czech Republic Univ Autonoma Madrid Escuela Politecn Super Madrid Spain

ISBN: (纸本)9780819472946

Imaging plays a key role in many diverse areas of application, such as astronomy, remote sensing, microscopy, and tomography. Owing to imperfections of measuring devices (e.g., optical degradations, limited size of sensors) and instability of the observed scene (e.g., object motion, media turbulence), acquired images can be indistinct, noisy, and may, exhibit insufficient spatial and temporal resolution. In particular, several external effects blur images. Techniques for recovering the original image include blind deconvolution (to remove blur) and superresolution (SR). The stability of these methods depends on having more than one image of the same frame. Differences between images are necessary to provide new information, but they can be almost unperceivable. State-of-the-art SR techniques achieve remarkable results in resolution enhancement by estimating the subpixel shifts between images, but they lack any apparatus for calculating the blurs. In this paper, after introducing a review of current SR, techniques we describe two recently developed SR methods by the authors. First, we introduce a variational method that minimizes a regularized energy function with respect to the high resolution image and blurs. In this way we establish a unifying way to simultaneously estimate the blurs and the high resolution image. By estimating blurs we automatically estimate shifts with subpixel accuracy, which is inherent for good SR performance. Second, an innovative learning-based algorithm using a neural architecture for SR is described. Comparative experiments on real data illustrate the robustness and utilization of both methods.

关键词： superresolution deconvolution energy minimization probabilistic neural network sequence processing

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Hardware/software trade-offs for advanced 3G channel coding

Hardware/software trade-offs for advanced 3G channel coding

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Design, Automation and Test in Europe conference and Exhibition

作者： H. Michel A. Worm M. Munch N. Wehn Institute of Microelectronic System Design University of Kaiserslautern Kaiserslautern Germany ASIC Design Laboratories Zaventem Belgium

ISBN: (纸本)0769514715

Third generation's wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G's systems. Numerous existing and emerging standards require flexible implementations ("software radio"). Thus efficient implementations of the performance-critical parts as Turbo decoding on programmable architectures are of great interest. Besides high-performance DSPs, application-customized RISC cores offer the required performance while still maintaining the aspired flexibility. This paper presents for the first time Turbo decoder implementations on customized RISC cores and compares the results with implementations on state-of-the-art VLIW DSPs. The results of our studies show that the Log-MAP performance is about 50% higher that on an ST120, a current VLIW architecture.

关键词： Hardware Channel coding Decoding Digital signal processing Reduced instruction set computing VLIW signal generators Wireless communication signal processing algorithms Software standards

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Correctly rounded floating-point division for DSP-enabled FPGAs

Correctly rounded floating-point division for DSP-enabled FP...

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International conference on Field Programmable Logic and Applications

作者： Bogdan Pasca Altera European Technology Centre High Wycombe UK

Floating-point division is a very costly operation in FPGA designs. High-frequency implementations of the classic digit-recurrence algorithms for division have long latencies (of the order of the number fraction bits) and consume large amounts of logic. Additionally, these implementations require important routing resources, making timing closure difficult in complete designs. In this paper we present two multiplier-based architectures for division which make efficient use of the DSP resources in recent Altera FPGAs. By balancing resource usage between logic, memory and DSP blocks, the presented architectures maintain high frequencies is full designs. Additionally, compared to classical algorithms, the proposed architectures have significantly lower latencies. The architectures target faithfully rounded results, similar to most elementary functions implementations for FPGAs but can also be transformed into correctly rounded architectures with a small overhead. The presented architectures are built using the Altera DSP Builder advanced framework and will be part of the default blockset.

关键词： Digital signal processing Polynomials Field programmable gate arrays Approximation error Memory management

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Trends in design of massively parallel coprocessors implemented in digital ASICs

Trends in design of massively parallel coprocessors implemen...

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International Joint conference on Neural Networks (IJCNN)

作者： P. Foldesy Analogic and Neural Computing Laboratory Computer and Automation Research Institute Hungarian Academy of Sciences (ATOMKI) Budapest Hungary

This paper collects the most recent parallel coprocessors and highlights the recent trends. It is shown that the single chip massively parallel processor implementations seem to disappear from the scientific investigations (with the exception of low-level near-sensor image processing). Meanwhile, the formerly developed architectures have moved inside complex system-on-chips/microprocessors. The common aspect of the recent architectures is the advanced processing element and internal interconnection solutions, and the dominant mid-grain parallelism (i.e. up to a hundred processing element per chip).

关键词： Coprocessors Application specific integrated circuits Concurrent computing Parallel processing Systolic arrays Radar signal processing signal processing algorithms Laboratories Automation Image processing

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Low power implementation of a turbo-decoder on programmable architectures

Low power implementation of a turbo-decoder on programmable ...

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Asia and South Pacific Design Automation conference

作者： F. Gilbert A. Worm N. Wehn Institute of Microelectronic Systems Department of Electrical Engineering and Information Technology University of Kaiserslautern Germany

ISBN: (纸本)0780366336

Low power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on the system level by the use of an intelligent cancellation technique, and on the implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case energy consumption to 55% using data of state-of-the-art processors. Our approach is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of turbo-decoders based on voltage scheduling for third generation wireless systems.

关键词： Dynamic voltage scaling Turbo codes Iterative decoding Processor scheduling Forward error correction signal processing algorithms Channel coding Error correction Redundancy Bit error rate

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Energy-Efficient Synthetic-Aperture Radar processing on a Manycore Architecture

Energy-Efficient Synthetic-Aperture Radar Processing on a Ma...

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International conference on Parallel processing (ICPP)

作者： Zain-Ul-Abdin Anders Åhlander Bertil Svensson Centre for Research on Embedded Systems (CERES) Halmstad University Halmstad Sweden Saab AB Gothenburg Sweden

The next generation radar systems have high performance demands on the signal processing chain. Examples include the advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in real time. Many core architectures are gaining attention as a means to overcome the computational requirements of the complex radar signal processing by exploiting massive parallelism inherent in the algorithms in an energy efficient manner. In this paper, we evaluate a many core architecture, namely a 16-core Epiphany processor, by implementing two significantly large case studies, viz. an auto focus criterion calculation and the fast factorized back-projection algorithm, both key components in modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance and programmability. One of the Epiphany implementations demonstrates the usefulness of the architecture for the streaming based algorithm (the auto focus criterion calculation) by achieving a speedup of 8.9x over a sequential implementation on a state-of-the-art general-purpose processor of a later silicon technology generation and operating at a 2.7x higher clock speed. On the other case study, a highly memory-intensive algorithm (fast factorized back projection), the Epiphany architecture shows a speedup of 4.25x. For embedded signal processing, low power dissipation is equally important as computational performance. In our case studies, the Epiphany implementations of the two algorithms are, respectively, 78x and 38x more energy efficient.

关键词： signal processing algorithms Computer architecture Synthetic aperture radar Parallel processing Radar imaging Image resolution

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advanced receiver algorithms for MIMO wireless communications 06

Advanced receiver algorithms for MIMO wireless communication...

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Design, Automation and Test in Europe conference and Exhibition

作者： A. Burg M. Borgmanr M. Wenk C. Studer H. Bolcskei Integrated Systems Laboratory ETH Zurich Zurich Switzerland Communication Technology Laboratory ETH Zurich Zurich Switzerland

ISBN: (纸本)9783981080100

We describe the VLSI implementation of MIMO detectors that exhibit close-to optimum error-rate performance, but still achieve high throughput at low silicon area. In particular, algorithms and VLSI architectures for sphere decoding (SD) and K-best detection are considered, and the corresponding trade-offs between uncoded error-rate performance, silicon area, and throughput are explored. We show that SD with a per-block run-time constraint is best suited for practical implementations

关键词： MIMO Wireless communication signal processing algorithms Detectors Throughput Very large scale integration Silicon Receiving antennas Laboratories Maximum likelihood decoding

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