Achieving the performance required from a modern digital signalprocessing system often necessitates the real time application of reliable numerical algorithms for least squares estimation, solving linear systems, per...
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ISBN:
(纸本)0852965192
Achieving the performance required from a modern digital signalprocessing system often necessitates the real time application of reliable numerical algorithms for least squares estimation, solving linear systems, performing singular value decomposition and so on. In order to perform such computations at the required data rate it is often necessary to introduce a high degree of parallel processing. For many real time applications, it is necessary to design a highly dedicated parallel processor which can be implemented using advanced VLSI technology. It is in this context that the concept of algorithmic engineering has started to emerge. It describes the hybrid discipline of deriving stable numerical algorithms which are suitable for parallel computation and then mapping them onto parallel processing architectures capable of performing the computation efficiently at the required throughput rate.
Several aspects of the design of filters for burst error control for television signals in new or existing, analog or digital formats, are described. The error control capability is provided by prefiltering, so no red...
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Several aspects of the design of filters for burst error control for television signals in new or existing, analog or digital formats, are described. The error control capability is provided by prefiltering, so no redundant information need be transmitted. Prefilters which minimize distortion of the image and optimize effectiveness in estimating errors are discussed. Postfilters which can compensate for the prefiltering, further minimizing the small distortion are introduced. These error control methods can implement very efficient real-number outer codes that provide burst or impulse noise protection for signals in digital format that may employ standard finite-field inner codes, data compression algorithms, and other digital or analog processing. This inner processing can exacerbate impulse noise or cause substantial burst errors, which should be removed by outer codes, such as the described ones, in order to achieve the desired subjective improvement of advanced television.
The authors describe a high-speed systolic-based computer system designed to process real-life radar data in near real time. At the heart of the system is a ten-cell Warp (systolic) machine. A digital recorder is used...
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ISBN:
(纸本)0818690895
The authors describe a high-speed systolic-based computer system designed to process real-life radar data in near real time. At the heart of the system is a ten-cell Warp (systolic) machine. A digital recorder is used to input data to the system, and a color monitor displays the output of the processingalgorithms. The system permits the processing of large volumes of radar data in real time, displays the results of advancedsignal-processingalgorithms in an insightful and understandable fashion, and has the effect of bringing a radar environment inside the laboratory for experimental studies or, equivalently, taking a sophisticated computer outside into an operational radar environment. The authors briefly describe research efforts built around this facility and highlight the elements of the powerful signalprocessing neural network software that are basic to their execution.
The design and the performance evaluation of a parallel architecture for digital signalprocessing (DSP) are described. Many DSP applications cannot be efficiently solved by using standard DSP sequential microprocesso...
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ISBN:
(纸本)0818621419
The design and the performance evaluation of a parallel architecture for digital signalprocessing (DSP) are described. Many DSP applications cannot be efficiently solved by using standard DSP sequential microprocessors. In this case, using dedicated parallel architectures is the best way to obtain high performance, but they need flexibility to apply different DSP algorithms efficiently. The Pandora architecture provides a high degree of flexibility both for the system architecture (a mixed SIMD/MIMD technique is exploited) and for the node capability to implement different DSP algorithms (due to the writable control store). The node architecture and its VLSI implementation are described, focusing on the architectural aspects and the performance evaluation.
The purpose of the Enhanced Bottom Sonar System is to locate, via sonar signals of high intensity, communication cables buried in the ocean floor. The DSP2 is one of the remotely operated digital signal processors emp...
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ISBN:
(纸本)0780302028
The purpose of the Enhanced Bottom Sonar System is to locate, via sonar signals of high intensity, communication cables buried in the ocean floor. The DSP2 is one of the remotely operated digital signal processors employed with the system. The architecture and real-time operating system, VCOS, of the DSP3210 Digital signal Processor, the heart of the DSP2 which is used for the processing of sonar data, is presented. The artificial intelligence (AI) algorithms employed within the processor are discussed, and the results of at-sea experiments are also presented.
A systematic framework for mapping a class of iterative algorithms onto processor array architectures is presented. The iterative algorithm is directly mapped on the array without the requirement of transforming it in...
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ISBN:
(纸本)0818621419
A systematic framework for mapping a class of iterative algorithms onto processor array architectures is presented. The iterative algorithm is directly mapped on the array without the requirement of transforming it into any intermediate form, such as a uniform recurrent equation (URE). The principles of Lamport's coordinate method are used. The important subclass of algorithms known as weak single assignment codes (WSACs) is treated in an optimal way. Due to the structure of the algorithm and/or the multidimensional mapping, the resulting architectures can be either regular arrays (RAs) or piecewise regular arrays (PRAs).
The feasibility of using nontraditional methods of helicopter transmission fault classification is studied. Various signalprocessing and classifier techniques are investigated. All algorithms successfully classified ...
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The feasibility of using nontraditional methods of helicopter transmission fault classification is studied. Various signalprocessing and classifier techniques are investigated. All algorithms successfully classified the fault samples from a tail rotor transmission dataset. A hardware neural network system was designed and implemented. The relatively low resolution of the neural network circuitry required extensive preprocessing and scaling of the large dynamic range input signal. Results from the hardware system were similar to those achieved in simulation. It is pointed out that a true test of the techniques presented may require a dataset that is statistically richer.< >
A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for e...
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A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.< >
A parallel processing scheme is proposed for a FORTRAN program on a multiprocessor system named OSCAR (optimally scheduled advanced multiprocessor). The scheme combines parallel processing of fine grain tasks (each of...
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A parallel processing scheme is proposed for a FORTRAN program on a multiprocessor system named OSCAR (optimally scheduled advanced multiprocessor). The scheme combines parallel processing of fine grain tasks (each of which consists of an assignment statement), macro-data-flow computation (which uses parallelism among coarse grain tasks), and the traditional loop concurrentization. A parallelizing compiler that accomplishes the proposed scheme has been implemented on OSCAR. OSCAR has been designed to effectively support task-scheduling, which has been an obstacle to the realization of efficient parallel processing. A performance evaluation of the scheme on OSCAR is also described.< >
The authors describe a novel modular design and a VLSI implementation of a bit-serial pipelined fast Fourier transform (FFT) coprocessor. The proposed architecture is based on a distributed hardwired control mechanism...
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The authors describe a novel modular design and a VLSI implementation of a bit-serial pipelined fast Fourier transform (FFT) coprocessor. The proposed architecture is based on a distributed hardwired control mechanism. The control of various subunits in the processor is done by local controllers and the synchronization of operations is provided by a global controller. This FFT processor is a custom-built chip which has a built-in self-test (BIST) capability. BIST is provided using a coprocessor to a microprocessor, and the data transfer is controlled by asynchronous signals. A prototype of the proposed processor was implemented in 3- mu m SCMOS technology; it can operate at a maximum frequency of 50 MHz. The chip is a 32-pin square package, and it has a total area of 2.2 cm/sup 2/.< >
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