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检索条件"任意字段=Conference on Advanced Signal Processing Algorithms"
3487 条 记 录,以下是3371-3380 订阅
排序:
ALGORITHMIC ENGINEERING IN DIGITAL signal-processing
ALGORITHMIC ENGINEERING IN DIGITAL SIGNAL-PROCESSING
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2ND INTERNATIONAL SPECIALISTS SEMINAR ON THE DESIGN AND APPLICATION OF PARALLEL DIGITAL PROCESSORS
作者: MCWHIRTER, JG Royal Signals and Radar Establishment United Kingdom
Achieving the performance required from a modern digital signal processing system often necessitates the real time application of reliable numerical algorithms for least squares estimation, solving linear systems, per... 详细信息
来源: 评论
ERROR CONTROL CODES FOR advanced TELEVISION signalS BASED UPON PRELIMINARY AND POST FILTERING
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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 1991年 第3期37卷 464-468页
作者: MARSHALL, TG Center for Digital Signal Processing Research Rutgers University Piscataway NJ USA
Several aspects of the design of filters for burst error control for television signals in new or existing, analog or digital formats, are described. The error control capability is provided by prefiltering, so no red... 详细信息
来源: 评论
Systolic-based computing machinery for radar signal processing studies
Systolic-based computing machinery for radar signal processi...
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Proceedings of the 1990 International conference on Application Specific Array Processors
作者: Haykin, Simon Weber, Peter Cho, Bob Greenlay, Terry Orlando, Jim Deng, Cong Mann, Richard Commun Res Lab McMaster Univ Hamilton Ont Canada
The authors describe a high-speed systolic-based computer system designed to process real-life radar data in near real time. At the heart of the system is a ten-cell Warp (systolic) machine. A digital recorder is used... 详细信息
来源: 评论
Pandora--A microprogrammable node for DSP oriented architectures
Pandora--A microprogrammable node for DSP oriented architect...
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Proceedings of the 5th European Computer conference on advanced Computer Technology, Reliable Systems and Applications - CompEuro 91
作者: Piccinini, G. Roch, M.Ruo Zamboni, M.
The design and the performance evaluation of a parallel architecture for digital signal processing (DSP) are described. Many DSP applications cannot be efficiently solved by using standard DSP sequential microprocesso... 详细信息
来源: 评论
A REAL-TIME DIGITAL signal PROCESSOR FOR THE ENHANCED BOTTOM SONAR SYSTEM
A REAL-TIME DIGITAL SIGNAL PROCESSOR FOR THE ENHANCED BOTTOM...
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CONF ON OCEANS 91 : OCEAN TECHNOLOGIES AND OPPORTUNITIES IN THE PACIFIC FOR THE 90S
作者: EARP, RL AT&T Federal Systems Advanced Technologies Greensboro NC USA
The purpose of the Enhanced Bottom Sonar System is to locate, via sonar signals of high intensity, communication cables buried in the ocean floor. The DSP2 is one of the remotely operated digital signal processors emp... 详细信息
来源: 评论
Design methodology for mapping iterative algorithms on piecewise regular processor arrays
Design methodology for mapping iterative algorithms on piece...
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Proceedings of the 5th European Computer conference on advanced Computer Technology, Reliable Systems and Applications - CompEuro 91
作者: Soudris, Dimitrios J. Birbas, Michael K. Goutis, Costas E.
A systematic framework for mapping a class of iterative algorithms onto processor array architectures is presented. The iterative algorithm is directly mapped on the array without the requirement of transforming it in... 详细信息
来源: 评论
Detection and classification of faults from helicopter vibration data using recently developed signal processing and neural network techniques
Detection and classification of faults from helicopter vibra...
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Asilomar conference on signals, Systems & Computers
作者: M.R. Solorzano D.K. Ishii N.R. Nickolaisen W.Y. Huang Naval Ocean Systems Center Advanced Technology Development San Diego CA USA
The feasibility of using nontraditional methods of helicopter transmission fault classification is studied. Various signal processing and classifier techniques are investigated. All algorithms successfully classified ... 详细信息
来源: 评论
A VLSI architecture for multiplication, division and square root
A VLSI architecture for multiplication, division and square ...
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International conference on Acoustics, Speech, and signal processing (ICASSP)
作者: S.E. McQuillan J.V. McCanny Institute of Advanced Microelectronics Department of Electrical and Electronic Engineering Queen''s University Belfast Belfast UK
A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for e... 详细信息
来源: 评论
Parallel processing scheme for a FORTRAN program on a multiprocessor system OSCAR
Parallel processing scheme for a FORTRAN program on a multip...
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IEEE Pacific Rim conference on Communications, Computers and signal processing
作者: H. Honda A. Mogi A. Ogura H. Kasahara S. Narita Department of Electrical Engineering Waseda University Tokyo Japan
A parallel processing scheme is proposed for a FORTRAN program on a multiprocessor system named OSCAR (optimally scheduled advanced multiprocessor). The scheme combines parallel processing of fine grain tasks (each of... 详细信息
来源: 评论
A high speed pipelined FFT processor
A high speed pipelined FFT processor
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International conference on Acoustics, Speech, and signal processing (ICASSP)
作者: S.R. Malladi S.R. Myneni P.V. Pothana M.A. Bayoumi Advanced Computer Studies University of Southwestern Louisiana Lafayette LA USA
The authors describe a novel modular design and a VLSI implementation of a bit-serial pipelined fast Fourier transform (FFT) coprocessor. The proposed architecture is based on a distributed hardwired control mechanism... 详细信息
来源: 评论