Techniques for testing EDTV and IDTV (enhanced and improved definition television) systems are examined. The utility of past practices, current requirements, and future directions for fully evaluating the complex mult...
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Techniques for testing EDTV and IDTV (enhanced and improved definition television) systems are examined. The utility of past practices, current requirements, and future directions for fully evaluating the complex multidimensional signalprocessing techniques of today's and tomorrow's television environments are discussed. Particular attention is given to the evaluation of step responses in advanced TV systems and to bandwidth measurements in the spatial-temporal frequency domains. It is noted that conventional procedures for testing and measuring the performance of television equipment are not suitable for a full evaluation of all effects which can be introduced by complex digital signalprocessing in advanced television systems. Test slides and stationary test patterns of yesterday's practices do not show any of the temporal band limitations which are imposed by some filtering techniques. More elaborate images must be developed to analyze picture sharpness and artifacts in the multidimensional spectrum of video images processed for EDTV and IDTV. Similar test patterns and sequences can also be used for evaluating some aspects of HDTV (high-definition TV) systems. The frequency domain images are useful in gaining a coherent understanding of the signalprocessingalgorithms currently being developed.< >
In this paper, we have discussed a parallel processor design using DSP microprocessors and dual-port RAMs(DPRs) for image processing applications and scientific computations. This parallel processor uses eight TMS320C...
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The prospect of multi-channel/multi-user speech communication via the emerging ISDN has raised a lot of interest in advanced coding algorithms for 7KHz wideband speech. The capability of 32Kb/s wideband speech coding ...
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An examination is made of the current approaches to sensor line supervision and their relative effectiveness against the range of easily available circumvention techniques is assessed, compared to encrypted line super...
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An examination is made of the current approaches to sensor line supervision and their relative effectiveness against the range of easily available circumvention techniques is assessed, compared to encrypted line supervision. Features of high security encrypted line supervision, including encryption techniques, interactive polling, the generation of random data, proprietary algorithms and keys, serial numbers and the processing of such an approach are discussed, including the flexibility offered by miniaturization of the microprocessor controlled circuits and modular system design. Highlighted are how an encryption module can be deployed within an overall high security system. Examples of practical applications provide insight into the effective and efficient use of this advanced security technology.
The author presents a systems-level approach to integrating state-of-the-art rocket engine technology with advanced computational techniques to develop an integrated diagnostic system (IDS) for space propulsion system...
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The author presents a systems-level approach to integrating state-of-the-art rocket engine technology with advanced computational techniques to develop an integrated diagnostic system (IDS) for space propulsion systems. The key feature of this IDS is the use of advanced diagnostic algorithms for failure detection as opposed to the practice of redline-based failure detection methods. The author presents a top-down analysis of rocket engine diagnostic requirements, rocket engine operation, sensor technologies, and applicable diagnostic algorithms which serve as a basis for the IDS. The concepts of hierarchical, model-based information processing are described together with the use of signalprocessing, pattern recognition, and artificial intelligence techniques which are an integral part of this diagnostic systems.< >
The authors describe a high-speed systolic-based computer system designed to process real-life radar data in near real time. At the heart of the system is a ten-cell Warp (systolic) machine. A digital recorder is used...
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The authors describe a high-speed systolic-based computer system designed to process real-life radar data in near real time. At the heart of the system is a ten-cell Warp (systolic) machine. A digital recorder is used to input data to the system, and a color monitor displays the output of the processingalgorithms. The system permits the processing of large volumes of radar data in real time, displays the results of advancedsignal-processingalgorithms, and has the effect of bringing a radar environment inside the laboratory for experimental studies or, equivalently, taking a sophisticated computer outside into an operational radar environment. The authors briefly describe research efforts built around this facility and highlight the elements of the powerful signalprocessing neural network software that are basic to their execution.< >
An approach is presented for high-level synthesis of digital signalprocessing (DSP) algorithms. Two features are provided by the approach: completeness and correctness. A given algorithm is represented in a newly dev...
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An approach is presented for high-level synthesis of digital signalprocessing (DSP) algorithms. Two features are provided by the approach: completeness and correctness. A given algorithm is represented in a newly developed language termed the algorithm specification language (ASL). ASL had the ability to describe any general algorithm. An automatic procedure is used to transform an ASL representation into a specific realization specification using a correctness preserving set of transformations. The realization format is based on representing the digital architectures by another language called the realization specification language (RSL). Logic programming is used as a user interface for the synthesis procedure.< >
The authors describe the decomposition of six algorithms: two partial differential equations (PDE) solvers (successive over-relaxation (SOR) and alternating direction implicit (ADI)), fast Fourier transform (FFT), Mon...
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The authors describe the decomposition of six algorithms: two partial differential equations (PDE) solvers (successive over-relaxation (SOR) and alternating direction implicit (ADI)), fast Fourier transform (FFT), Monte Carlo simulations, simplex linear programming, and sparse solvers. They present the performance results of these algorithms on two shared-memory VAX/VMS multiprocessor prototypes: VAX 6300 series with up to eight processors and M31 with up to 22 processors. It is demonstrated that by efficient decomposition it is possible to achieve high performance for all algorithms on both prototypes. The efficient decomposition techniques applied to optimize the performance of parallel algorithms are described. The performance implications of different cache designs for two multiprocessors are discussed.< >
A number of high-performance VLSI architectures for real-time image coding applications are described. In particular, attention is focused on circuits for computing the 2D DCT (discrete cosine transform) and for 2-D v...
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A number of high-performance VLSI architectures for real-time image coding applications are described. In particular, attention is focused on circuits for computing the 2D DCT (discrete cosine transform) and for 2-D vector quantization. The former circuits are based on Winograd algorithms and compromise a number of bit-level systolic arrays with a bit-serial, word-parallel input. The latter circuits exhibit a similar data organization and consist of a number of inner product array circuits. Both circuits are highly regular and allow extremely high data rates to be achieved through extensive use of parallelism.< >
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