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IEEE/Cornell conference on advanced Concepts in High Speed Semiconductor Devices and Circuits

作者： M.B. Steer G.L. Bilbro R.J. Trew S.G. Skaggs High Frequency Electronics Laboratory and the Center for Communications and Signal Processing Department of Electrical and Computer Engineering North Carolina State University Raleigh NC USA

The authors have developed an alternative formulation of simulated annealing using a tree-based Metropolis procedure called tree annealing. Tree annealing is suited to continuous optimization problems and, in particular, to transistor parameter extraction. The tree annealing optimization algorithm was used to extract the parameters of the HBT (heterojunction bipolar transistor) of U.K. Mishra et al. (IEDM Tech. Dig., p.180-3, Dec. 1988) using a physically based equivalent circuit and deembedded scattering parameter measurements from 45 MHz to 26.5 GHz. Good results were obtained from the parameter extraction technique, and the ability of MFA not to be locked in local minima enabled a physically based equivalent circuit model to be used. Tree annealing is essentially a smart random search technique and so requires many more functional evaluations than do gradient-based minimization algorithms. However, no startling guess is required, and the bounds on parameter values can be widely separated with little effect on optimization time.< >

关键词： Parameter extraction Microwave transistors Simulated annealing Equivalent circuits Combinatorial mathematics Robustness Frequency Laboratories Microwave communication signal processing

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GENERAL-SYNTHESIS PROCEDURES FOR FIR LOSSLESS TRANSFER-MATRICES, FOR PERFECT-RECONSTRUCTION MULTIRATE FILTER BANK APPLICATIONS

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IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND signal processing 1988年第10期36卷 1561-1574页

作者： DOGANATA, Z VAIDYANATHAN, PP NGUYEN, TQ Department of Electrical Engineering California Institute of Technology Pasadena CA USA

A recently reported procedure (see ibid., ***-35, p.476-492, Apr. 1987 and Proc. IEEE Int. Conf. Acoust., Speech, Sig processing, Apr. 1987, p.2169-2172) for the design of M-channel perfect-reconstruction quadrature mirror filter (QMF) bands uses the concept of lossless alias-component matrices. The synthesis of such QMF banks centers around the generation of a lossless M*M finite-impulse response (FIR) transfer matrix E(z). Recent results for such generation have been somewhat ad hoc, i.e. not sufficiently general. A general procedure is outlined for the generation of such transfer matrices. The procedure is based on a cascaded-lattice structure, derived from a state-space viewpoint. The structure is such that it generates only M*M lossless FIR transfer matrices (regardless of parameter values), and conversely, any M*M lossless FIR transfer matrix can be obtained by a suitable choice of parameters. These parameters turn out to be angles theta /sub k/, and the structure is such that the number of angles is minimal. A design example is presented to demonstrate the main results.< >

关键词： Finite impulse response filter Filter bank Mirrors signal processing algorithms Algorithm design and analysis conference proceedings Speech processing Acoustic signal processing

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High speed signal processor supports filtering in time and frequency domains

High speed signal processor supports filtering in time and f...

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IEEE Global Telecommunications conference & Exhibition: Communications for the Information Age - conference Record

作者： Gomez, Steven A. Gonzales, Steven R. Hsu, De D. Kuo, Alfred Eai-Hsin TRW LSI Products Inc La Jolla CA USA

A monolithic integrated circuit has been developed which supports a variety of signal processing algorithms. The advanced architecture of the TMC2310 FFT-Plus, fabricated in 1.2-μmCMOS technology, provides the capability to perform signal processing operations at bit-slice speeds while providing a system design as simple as a single-chip, programmable DSP (digital signal processor). The authors describe the architecture and performance of the TMC2310 and how it can be used to implement high-speed, nonrecursive digital filters.

关键词： signal processing

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WAFER-SCALE SYSTOLIC ARRAY FOR ADAPTIVE ANTENNA processing.

WAFER-SCALE SYSTOLIC ARRAY FOR ADAPTIVE ANTENNA PROCESSING.

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ICASSP '88: 1988 International conference on Acoustics, Speech, and signal processing. V 1, Speech processing;v 2, Multidimensional signal processing;v 3, Digital signal processing;v 4, VLSI Spectral Estimation;v 5, Audio & Electroacoustics

作者： Rader, Charles M. MIT Lexington MA USA MIT Lexington MA USA

A wafer-scale VLSI system is being built to determine the weights for an adaptive antenna application. The data are sampled N-component vector time series X(n), with components that are time functions observed at N individual antenna ports. The processed output, y(n), is a weighted sum of the components, e. g. , W**tX(n). In practice, the author expects to computer W a few hundred times per second, based on observations of many exponentially windowed samples of X which arrive two-orders-of-magnitude more frequently. The algorithm used for determining W is based on the use of Givens transformations to rotate the original data into a lower triangular matrix, after which the desired weights are the solution to a triangular set of linear equations. The computational cost of this algorithm (and of almost all other algorithms which find the optimum weights) increases with N, the number of degrees of freedom, as N**3, so for sufficiently large N, some degree of parallelism must be used. An advanced architecture which uses N/2 processors connected in a linear chain, suitable for realizing this algorithm for N equals 64 in a systolic VLSI wafer-scale design, is described.

关键词： ANTENNAS

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SPARTA: MULTIPLE signal PROCESSORS FOR HIGH-PERFORMANCE ROBOTIC CONTROL.

SPARTA: MULTIPLE SIGNAL PROCESSORS FOR HIGH-PERFORMANCE ROBO...

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Proceedings - 1988 IEEE International conference on Robotics and Automation.

作者： Ish-Shalom, Jehuda Kazanzides, Peter IBM Yorktown Heights NY USA IBM Yorktown Heights NY USA

ISBN: (纸本)0818608528

The SPARTA (signal Processors for advanced Robot Technology Applications) system is a hybrid computer which includes: (1) program development environment on an IBM VM/CMS mainframe computer;(2) user interface and runtime support on an IBM PC;and (3) real-time computation and I/O using multiple IBM Hermes signal processors situated on the IBM PC bus. The program-development environment includes the PLH high-level language for generating efficient real-time Hermes code. The runtime supports symbolic debugging, dynamic loading, and synchronous switching of control algorithms during real-time program execution. The real-time environment includes an operating system which supports foreground and background task execution and real-time data collection and display. A SPARTA system with three Hermes signal processors is currently being used to develop control algorithms for a two-axis fast direct-drive Cartesian robot at sample rates in excess of 10 kHz.

关键词： signal processing

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1988 IEEE international conference on computer design: VLSI in computers & processors (ICCD '88), proceedings

1988 IEEE international conference on computer design: VLSI ...

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IEEE International conference on Computer Design: VLSI in Computers & Processors (ICCD '88), 1988 Proceedings

作者： Anon

ISBN: (纸本)0818608722

The proceedings contains 125 papers. The following topics are dealt with: parallel processing for VLSI CAD and testing;supercomputer technology;analog design techniques;test generation;advanced system interconnect and packaging microprocessor architecture;simulation;VLSI array testing;system applications of high-Tc superconductors;cell layout techniques;high-level synthesis;design for test;systolic arrays;placement;computer design;arithmetic algorithms;multiprocessing;simulated annealing;reconfigurable VLSI processor arrays;signal processing;and formal verification.

关键词： INTEGRATED CIRCUITS, VLSI

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Development of advanced HD-MAC coding algorithms

Development of advanced HD-MAC coding algorithms

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IBC 1988 - International Broadcasting Convention

作者： Hurault, J.-P. Arragon, J.-P. Lab d'Electronique et de Physique Appliquee France

Among the different subprojects of the Eureka 95 HDTV project, subproject 5 has been given the task of formulating the detailed algorithm to be used for coding the HDTV signal into a MAC compatible form to be submitted to the CCIR. This paper describes the organization of the working group within subproject 5, the separation of the problem into its various aspects and the contributions being made by the participating organizations. The main lines of investigations to improve HD MAC performance will be reported as well as the various options of the coding system to which these investigations have given birth, and have been worked out as 'candidate systems' by several companies. The procedure used for selection of the final system will be reported.

关键词： signal processing

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Multi-dimensional systolic networks for DSP algorithms

Multi-dimensional systolic networks for DSP algorithms

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International conference on Acoustics, Speech, and signal processing (ICASSP)

作者： N. Ling M.A. Bayoumi The Center for Advanced Computer Studies University of Southwestern Louisiana Lafayette LA USA

The authors present a novel technique for transforming a class of digital signal processing (DSP) algorithms, and some arithmetic algorithms, to specific forms that can be directly mapped onto higher-dimensional systolic networks. The latency, as well as the order of complexity of computation time, can be significantly improved through implementing these algorithms on higher-dimensional systolic networks. At the same time, the order of area complexity is kept constant. The technique can be applied to problems such as 1-D convolution, k-point discrete Fourier transform (DFT), finite-impulse response (FIR) filters, and matrix-vector multiplication. The k-point DFT algorithm example is illustrated along with other examples. Implementation issues of high-dimensional systolic networks on 2-D or 3-D VLSI are discussed.< >

关键词： Digital signal processing signal processing algorithms Discrete Fourier transforms Finite impulse response filter Systolic arrays Convolution Very large scale integration Digital arithmetic Delay Equations

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Reliable modulo systolic arrays for DSP algorithms

Reliable modulo systolic arrays for DSP algorithms

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International conference on Acoustics, Speech, and signal processing (ICASSP)

作者： M.A. Bayoumi The Center for Advanced Computer Studies University of Southwestern Louisiana Lafayette LA USA

The algebraic and structural properties of a residue number system (RNS) to optimize the design of DSP (digital signal processing) systolic arrays is discussed. RNS establishes parallelism on the algorithmic level by decomposing the original computational field into a set of finite fields, in which arithmetic operations are performed independently for each field. The impact of the moduli size on the structural choices is analyzed. Three different structures, namely, word-parallel, bit-parallel, and bit-serial, are presented. Redundant RNS has fault tolerance capabilities. An efficient fault-detection technique is developed as an alternative to the standard procedure based on a mixed radix algorithm. A finite-impulse-response (FIR) filter algorithm is used as a case study.< >

关键词： Systolic arrays Digital signal processing signal processing algorithms Finite impulse response filter Design optimization signal design Parallel processing Concurrent computing Galois fields Arithmetic

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High speed signal processor supports filtering in time and frequency domains

High speed signal processor supports filtering in time and f...

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IEEE Global Telecommunications conference and Exhibition. Communications for the Information Age

作者： S.A. Gomez S.R. Gonzales D.D. Hsu A.E.-H. Kuo TRW LSI Products Inc. La Jolla CA USA TRW LSI Products Inc. La Jolla CA USA

A monolithic integrated circuit has been developed by TRW which supports a variety of signal processing algorithms. The advanced architecture of the TMC2310 FFT-Plus, fabricated in 1.2- mu m CMOS technology, provides the capability to perform signal processing operations at bit-slice speeds while providing a system design as simple as a single-chip, programmable DSP (digital signal processor). The authors describe the architecture and performance of the TMC2310 and how it can be used to implement high-speed, nonrecursive digital filters.< >

关键词： signal processing Filtering signal processing algorithms CMOS technology Digital signal processing Monolithic integrated circuits CMOS process Integrated circuit technology Digital signal processors Digital filters

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