In this paper we describe our initial efforts to make SPHINX, the CMU continuous speech recognition system, environmentally robust. Our work has two major goals: to enable SPHINX to adapt to changes in microphone and ...
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This publication contains 249 conference papers. The following topics are dealt with: protocol and applications and packet switching;TDX-10 digital switching system technology;artificial intelligence and expert system...
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This publication contains 249 conference papers. The following topics are dealt with: protocol and applications and packet switching;TDX-10 digital switching system technology;artificial intelligence and expert systems;image processing;computer architecture;software for parallel processing;token passing LAN and applications;optimization and neural networks;digital modulation and modems;functional programming languages;architectures for parallel processing;application and implementation of Petri net concepts;signalprocessing and filters;array spectral analysis;advanced communication networks;TROPICO digital switching system;high performance computing theory and applications;pattern recognition;fault tolerant computing;instrumentation and process control;data communication networks;speech analysis and recognition;computer hardware systems;robotics and automation;mobile radio;theoretical computer science and algorithms;distributed processing;LAN/WAN networking;applied expert systems;coding;C-DOT digital switching system;power delivery systems;rural communication;radar;parallel execution of functional programs;VLSI, ASICS and devices;transmission media and communication systems;office automation and databases;program transformation, synthesis and analysis;and power electronics.
The authors present a technique for transforming DSP (digital signalprocessing) algorithms to a form suitable for multidimensional systolic array implementation. The aim of the transformation is to speed up computati...
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The authors present a technique for transforming DSP (digital signalprocessing) algorithms to a form suitable for multidimensional systolic array implementation. The aim of the transformation is to speed up computation without much increase in area requirement. The price to be paid is the small amount of additional circuitry (usually in the form of adders and interconnection wires) required for interrow or interplane communications. The application of the technique to some DSP algorithms is presented. The systolic networks produced are implemented using NORA CMOS logic structure and laid out using 3- mu m CMOS p-well technology. Areas and times for the resulting architectures are evaluated and discussed.< >
A description is given of the architecture and the instruction set of the ST18940/41 processor. The use of an advanced CMOS technology (1.2 mu m) combined with a highly parallel architecture provides a powerful and ef...
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A description is given of the architecture and the instruction set of the ST18940/41 processor. The use of an advanced CMOS technology (1.2 mu m) combined with a highly parallel architecture provides a powerful and efficient DSP as demonstrated on the usual signalprocessingalgorithms. To cover a wide range of applications, two versions are provided: a closed version with on-chip masked program ROM and an open version, which can access 64 K works of external program memory.< >
A least-mean-square algorithm, the stochastic gradient search least-mean-square (SGSLMS) algorithm, is proposed. It is robust to noise in the gradient estimate and has fast convergence without having to use an optimal...
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A least-mean-square algorithm, the stochastic gradient search least-mean-square (SGSLMS) algorithm, is proposed. It is robust to noise in the gradient estimate and has fast convergence without having to use an optimal step size. The SGSLMS algorithm is realized by estimating the correlation between the adaptive error and the input signals using as proposed new adaptive one-pole correlator. The correlator is used for fast, efficient gradient estimation rather than to control the step size, as in some other LMS variants. In the convergence process, the adaptive error, being initially large and highly nonstationary, results in a large gradient estimate. After convergence, the adaptive error is small, almost random, and almost stationary, yielding a small gradient estimate. The correlator is designed to optimize the rate of convergence under these two conditions. The performance of this algorithm is compared to those of the conventional and normalized LMS algorithms.< >
A computation engine (V8) based on eight VLSI vector signal processors (ZSP-322) was developed for dedicated DSP (digital signalprocessing) applications in areas such as nonparametric spectral estimation, beamforming...
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A computation engine (V8) based on eight VLSI vector signal processors (ZSP-322) was developed for dedicated DSP (digital signalprocessing) applications in areas such as nonparametric spectral estimation, beamforming, Doppler, etc. A design methodology and a set of tools were implemented and tested, facilitating multiprocessor algorithm development and hardware implementation. A novel scheme for assessment of the noise model of a complete system is reported. Multi-V8 implementation schemes for enhanced performance, such as pipelining, computation wave, and interleaving, are discussed and mapped to a quantitative performance space. The internal details of the ZSP-322 device are provided.< >
A high-sample-rate robot controller has been designed to resolve computational requirements in advancedalgorithms, such as the computed torque method or various impedance control algorithms. An active stiffness contr...
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A high-sample-rate robot controller has been designed to resolve computational requirements in advancedalgorithms, such as the computed torque method or various impedance control algorithms. An active stiffness control algorithm for a six-degree-of-freedom manipulation has been implemented on the controller, and a 1 kHz sampling rate has been achieved. The design assumes no specific algorithm and robot configuration, and it is easy to increase the number of drive joints. The controller is equipped with a general-purpose vector/matrix calculation engine, servo drivers, and a 16-bit microcomputer system. The calculation engine, which accelerates hole computation for advanced control methods, is based on a 13.4 MFLOPS single-chip floating-point digital signal processor (DSP). This engine was developed to simplify DSP programming without degrading its high-performance computation capabilities. Basic vector/matrix functions and general functions for scalar value computation are mask ROMed on the DSP chip. The controller construction and calculation engine functions, and their performance, are addressed.< >
Describes a parallel computer architecture targeted at signal pattern analysis applications, scalable to configurations capable of TeraFLOP (10/sup 12/ floating point operations per second) throughput. An important at...
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Describes a parallel computer architecture targeted at signal pattern analysis applications, scalable to configurations capable of TeraFLOP (10/sup 12/ floating point operations per second) throughput. An important attribute of the architecture is its low interconnection overhead, making it well suited to miniaturization using advanced packaging. Preliminary design and thermal tests project a computing density of 300 GigaFLOPS per cubit foot. The architecture is reconfigurable as a tree machine, one or more rings, or a set of linear systolic arrays. Fault tolerance is achieved by embedding these topologies within a four-connected lattice, growing around any faults. A performance model is derived and used to analyze the impact of skewness of the embedded trees on the execution time of parallel recognition algorithms.< >
An efficient and fast algorithm for implementing the Discrete Fourier Transform (DFT) on a binary tree parallel computer is presented. The algorithm achieves an almost linear increase in speed-up factors as processing...
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An efficient and fast algorithm for implementing the Discrete Fourier Transform (DFT) on a binary tree parallel computer is presented. The algorithm achieves an almost linear increase in speed-up factors as processing elements are added.
The authors discuss the role of transputers in high-speed, high-volume data processing and describe the software design methodology necessary to support a fully engineered implementation. An advanced microdensitometer...
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The authors discuss the role of transputers in high-speed, high-volume data processing and describe the software design methodology necessary to support a fully engineered implementation. An advanced microdensitometer, SuperCOSMOS, is currently under development, and provides data at rates of 500 kbytes/s from a linear 2048 element CCD (charge coupled device) array. Particular attention is given to the operation of the current COSMOS machine, the development of SuperCOSMOS, the ported process, topologies, and the interface. Porting of algorithms for the real-time processing required by SuperCOSMOS has proved straightforward, and it seem likely that offline processing will be transferred to another array of transputers in order to exploit the processing power available. Each offline domain will consist of one or more transputers and 24 Mbytes of memory and will have access to those sections of the disk farm not being used for data acquisition.< >
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