Two algorithms are presented for online estimation of the optimal gain of the Kalman filter applied to sensor signals when the signal-to-noise ratio is unknown. First-order spectra of a pure signal and coloured measur...
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Two algorithms are presented for online estimation of the optimal gain of the Kalman filter applied to sensor signals when the signal-to-noise ratio is unknown. First-order spectra of a pure signal and coloured measurement noise are assumed. The proposed adaptive Kalman filtering algorithms have been tested for errors of the pure signal estimation. Although the tests have been performed for stationary signals, the algorithms can also be used successfully for time-varying sensor signals when the signal-to-noise ratio varies in comparison to the length of the adaptation step.< >
This paper introduces a logic programming approach for specifying, simulating, and testing Digital signalprocessing (DSP) systems. Prolog is used as a Hardware Description Language and a, host one, too. Backtracking ...
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This paper introduces a logic programming approach for specifying, simulating, and testing Digital signalprocessing (DSP) systems. Prolog is used as a Hardware Description Language and a, host one, too. Backtracking and pattern matching of Prolog are employed for simulation and testing, respectively. Prolog provides homogeneity to the developed system as it supports hierarchical development and mixing of description at various hierarchical levels. The developed sys tem belongs to Algorithmic Specific CAD family. It can be employed for many DSP algorithms and applications development.
A description is given of the TLC32040, a programmable analog interface system fabricated with advanced LinCMOS technology and capable of serving a significant portion of the speech and modem markets. Its versatility ...
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A description is given of the TLC32040, a programmable analog interface system fabricated with advanced LinCMOS technology and capable of serving a significant portion of the speech and modem markets. Its versatility lends its use to a wide variety of digital signalprocessing (DSP) systems, providing each with a lower cost solution than its own volume could drive. The direct interface of TLC32040/1 to the TMS320C25 and TMS320C17 DSP processors is illustrated.< >
The evoked potentials recorded on the scalp are generally so disturbed by different biological noises that they require more and more advancedsignal-processing methods, whose efficiency does not in all cases compensa...
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The evoked potentials recorded on the scalp are generally so disturbed by different biological noises that they require more and more advancedsignal-processing methods, whose efficiency does not in all cases compensate the unavoidable drawbacks due to the increasing modeling complexity. A proposed alternative is the use of a simple suitable statistical model whose principal aim is to allow the design of a robust and efficient processing algorithm. The authors show that the robustness of the algorithm can largely compensate for the simplicity of the chosen model.< >
The authors propose a bit-serial structure using systolic arrays in the implementation of a finite-impulse-response (FIR) algorithm for large sizes of data and higher-order filters. The bit cells are arranged in a 2-D...
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The authors propose a bit-serial structure using systolic arrays in the implementation of a finite-impulse-response (FIR) algorithm for large sizes of data and higher-order filters. The bit cells are arranged in a 2-D array which enhances the extensibility and provides efficiency for high-precision data. Barrel shifters are used on the cell level which increases the throughput of the proposed pipelined structure. Moreover, the proposed architecture has distributed error-control features. The necessity of such distributed fault-tolerance in DSP (digital signalprocessing) architectures is due to its susceptibility to permanent and intermittent errors caused by the high complexity of these circuit structures.< >
The SPARTA (signal processor for advanced robot technology applications) system is a hybrid computer which includes: (1) program development environment on an IBM VM/CMS mainframe computer; (2) user interface and runt...
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The SPARTA (signal processor for advanced robot technology applications) system is a hybrid computer which includes: (1) program development environment on an IBM VM/CMS mainframe computer; (2) user interface and runtime support on an IBM PC; and (3) real-time computation and I/O using multiple IBM Hermes signal processors situated on the IBM PC bus. The program-development environment includes the PLH high-level language for generating efficient real-time Hermes code. The runtime supports symbolic debugging, dynamic loading, and synchronous switching of control algorithms during real-time program execution. The real-time environment includes an operating system which supports foreground and background task execution and real-time data collection and display. A SPARTA system with three Hermes signal processors is currently being used to develop control algorithms for a two-axis fast direct-drive Cartesian robot at sample rates in excess of 10 kHz;.< >
A new 32-bit floating point (IEEE standard) (digital signalprocessing) DSP vector signal processor architecture is described. The internal architecture is highly parallel. It is based on six well coordinated, indepen...
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A new 32-bit floating point (IEEE standard) (digital signalprocessing) DSP vector signal processor architecture is described. The internal architecture is highly parallel. It is based on six well coordinated, independent machines. The ALU (arithmetic logic unit) has a pipeline structure optimized for the execution of DSP and matrix operations (FFT butterflies in particular). The highly flexible set of vectorized instructions allows for most efficient utilization of the internal assets. Together these features yield a high performance, high throughput processor with 31-Mflops computation power and very minimal overhead. A description is given of the architecture of the device, the different internal units and their coordination. The instruction set basic features are presented, and a few benchmarks of a single processor are given. A simple, minimal system architecture combining two processors sharing a single bus, doubling the throughput of a single processor system, is suggested.< >
A full-duplex analog speech-scrambling system is proposed for the application to mobile communication systems and public-switched telephone networks. The scrambling algorithm is based on the rearrangement of the fast ...
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A full-duplex analog speech-scrambling system is proposed for the application to mobile communication systems and public-switched telephone networks. The scrambling algorithm is based on the rearrangement of the fast Fourier transform (FFT) coefficients accompanied by adaptive dummy spectrum insertion and companding operations. Simulations results indicate that the scrambled speech has no residual intelligibility and the unscrambled speech quality is satisfactory. The hardware unit is implemented by using seven advanced digital signalprocessing (DSP) chips, including those for an echo canceller for full-duplex operation and an adaptive equalizer.< >
A wafer-scale VLSI system is being built to determine the weights for an adaptive antenna application. The data are sampled N-component vector time series X(n), with components that are time functions observed at N in...
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A wafer-scale VLSI system is being built to determine the weights for an adaptive antenna application. The data are sampled N-component vector time series X(n), with components that are time functions observed at N individual antenna ports. The processed output, y(n), is a weighted sum of the components, e.g. W/sup t/X(n). In practice, the author expects to computer W a few hundred times per second, based on observations of many exponentially windowed samples of X which arrive two-orders-of-magnitude more frequently. The algorithm used for determining W is based on the use of Givens transformations to rotate the original data into a lower triangular matrix, after which the desired weights are the solution to a triangular set of linear equations. The computational cost of this algorithm (and of almost all other algorithms which find the optimum weights) increases with N, the number of degrees of freedom, as N/sup 3/, so for sufficiently large N, some degree of parallelism must be used. An advanced architecture which uses N/2 processors connected in a linear chain, suitable for realizing this algorithm for N=64 in a systolic VLSI wafer-scale design, is described.< >
An architecture for advancedsignalprocessing is presented that combines a linear systolic array, a global data path, and local memory into a highly flexible programming processor. Block algorithms provide a useful a...
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ISBN:
(纸本)0818608161
An architecture for advancedsignalprocessing is presented that combines a linear systolic array, a global data path, and local memory into a highly flexible programming processor. Block algorithms provide a useful approach for mapping algorithms into this architecture. Some of the performance tradeoffs associated with these algorithms are discussed.
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