A recently reported procedure (see ibid., ***-35, p.476-492, Apr. 1987 and Proc. IEEE Int. Conf. Acoust., Speech, Sig processing, Apr. 1987, p.2169-2172) for the design of M-channel perfect-reconstruction quadrature m...
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A recently reported procedure (see ibid., ***-35, p.476-492, Apr. 1987 and Proc. IEEE Int. Conf. Acoust., Speech, Sig processing, Apr. 1987, p.2169-2172) for the design of M-channel perfect-reconstruction quadrature mirror filter (QMF) bands uses the concept of lossless alias-component matrices. The synthesis of such QMF banks centers around the generation of a lossless M*M finite-impulse response (FIR) transfer matrix E(z). Recent results for such generation have been somewhat ad hoc, i.e. not sufficiently general. A general procedure is outlined for the generation of such transfer matrices. The procedure is based on a cascaded-lattice structure, derived from a state-space viewpoint. The structure is such that it generates only M*M lossless FIR transfer matrices (regardless of parameter values), and conversely, any M*M lossless FIR transfer matrix can be obtained by a suitable choice of parameters. These parameters turn out to be angles theta /sub k/, and the structure is such that the number of angles is minimal. A design example is presented to demonstrate the main results.< >
A monolithic integrated circuit has been developed which supports a variety of signalprocessingalgorithms. The advanced architecture of the TMC2310 FFT-Plus, fabricated in 1.2-μmCMOS technology, provides the capabi...
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A monolithic integrated circuit has been developed which supports a variety of signalprocessingalgorithms. The advanced architecture of the TMC2310 FFT-Plus, fabricated in 1.2-μmCMOS technology, provides the capability to perform signalprocessing operations at bit-slice speeds while providing a system design as simple as a single-chip, programmable DSP (digital signal processor). The authors describe the architecture and performance of the TMC2310 and how it can be used to implement high-speed, nonrecursive digital filters.
A wafer-scale VLSI system is being built to determine the weights for an adaptive antenna application. The data are sampled N-component vector time series X(n), with components that are time functions observed at N in...
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A wafer-scale VLSI system is being built to determine the weights for an adaptive antenna application. The data are sampled N-component vector time series X(n), with components that are time functions observed at N individual antenna ports. The processed output, y(n), is a weighted sum of the components, e. g. , W**tX(n). In practice, the author expects to computer W a few hundred times per second, based on observations of many exponentially windowed samples of X which arrive two-orders-of-magnitude more frequently. The algorithm used for determining W is based on the use of Givens transformations to rotate the original data into a lower triangular matrix, after which the desired weights are the solution to a triangular set of linear equations. The computational cost of this algorithm (and of almost all other algorithms which find the optimum weights) increases with N, the number of degrees of freedom, as N**3, so for sufficiently large N, some degree of parallelism must be used. An advanced architecture which uses N/2 processors connected in a linear chain, suitable for realizing this algorithm for N equals 64 in a systolic VLSI wafer-scale design, is described.
The SPARTA (signal Processors for advanced Robot Technology Applications) system is a hybrid computer which includes: (1) program development environment on an IBM VM/CMS mainframe computer;(2) user interface and runt...
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ISBN:
(纸本)0818608528
The SPARTA (signal Processors for advanced Robot Technology Applications) system is a hybrid computer which includes: (1) program development environment on an IBM VM/CMS mainframe computer;(2) user interface and runtime support on an IBM PC;and (3) real-time computation and I/O using multiple IBM Hermes signal processors situated on the IBM PC bus. The program-development environment includes the PLH high-level language for generating efficient real-time Hermes code. The runtime supports symbolic debugging, dynamic loading, and synchronous switching of control algorithms during real-time program execution. The real-time environment includes an operating system which supports foreground and background task execution and real-time data collection and display. A SPARTA system with three Hermes signal processors is currently being used to develop control algorithms for a two-axis fast direct-drive Cartesian robot at sample rates in excess of 10 kHz.
The proceedings contains 125 papers. The following topics are dealt with: parallel processing for VLSI CAD and testing;supercomputer technology;analog design techniques;test generation;advanced system interconnect and...
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ISBN:
(纸本)0818608722
The proceedings contains 125 papers. The following topics are dealt with: parallel processing for VLSI CAD and testing;supercomputer technology;analog design techniques;test generation;advanced system interconnect and packaging microprocessor architecture;simulation;VLSI array testing;system applications of high-Tc superconductors;cell layout techniques;high-level synthesis;design for test;systolic arrays;placement;computer design;arithmetic algorithms;multiprocessing;simulated annealing;reconfigurable VLSI processor arrays;signalprocessing;and formal verification.
Among the different subprojects of the Eureka 95 HDTV project, subproject 5 has been given the task of formulating the detailed algorithm to be used for coding the HDTV signal into a MAC compatible form to be submitte...
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Among the different subprojects of the Eureka 95 HDTV project, subproject 5 has been given the task of formulating the detailed algorithm to be used for coding the HDTV signal into a MAC compatible form to be submitted to the CCIR. This paper describes the organization of the working group within subproject 5, the separation of the problem into its various aspects and the contributions being made by the participating organizations. The main lines of investigations to improve HD MAC performance will be reported as well as the various options of the coding system to which these investigations have given birth, and have been worked out as 'candidate systems' by several companies. The procedure used for selection of the final system will be reported.
The authors present a novel technique for transforming a class of digital signalprocessing (DSP) algorithms, and some arithmetic algorithms, to specific forms that can be directly mapped onto higher-dimensional systo...
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The authors present a novel technique for transforming a class of digital signalprocessing (DSP) algorithms, and some arithmetic algorithms, to specific forms that can be directly mapped onto higher-dimensional systolic networks. The latency, as well as the order of complexity of computation time, can be significantly improved through implementing these algorithms on higher-dimensional systolic networks. At the same time, the order of area complexity is kept constant. The technique can be applied to problems such as 1-D convolution, k-point discrete Fourier transform (DFT), finite-impulse response (FIR) filters, and matrix-vector multiplication. The k-point DFT algorithm example is illustrated along with other examples. Implementation issues of high-dimensional systolic networks on 2-D or 3-D VLSI are discussed.< >
The algebraic and structural properties of a residue number system (RNS) to optimize the design of DSP (digital signalprocessing) systolic arrays is discussed. RNS establishes parallelism on the algorithmic level by ...
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The algebraic and structural properties of a residue number system (RNS) to optimize the design of DSP (digital signalprocessing) systolic arrays is discussed. RNS establishes parallelism on the algorithmic level by decomposing the original computational field into a set of finite fields, in which arithmetic operations are performed independently for each field. The impact of the moduli size on the structural choices is analyzed. Three different structures, namely, word-parallel, bit-parallel, and bit-serial, are presented. Redundant RNS has fault tolerance capabilities. An efficient fault-detection technique is developed as an alternative to the standard procedure based on a mixed radix algorithm. A finite-impulse-response (FIR) filter algorithm is used as a case study.< >
A monolithic integrated circuit has been developed by TRW which supports a variety of signalprocessingalgorithms. The advanced architecture of the TMC2310 FFT-Plus, fabricated in 1.2- mu m CMOS technology, provides ...
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A monolithic integrated circuit has been developed by TRW which supports a variety of signalprocessingalgorithms. The advanced architecture of the TMC2310 FFT-Plus, fabricated in 1.2- mu m CMOS technology, provides the capability to perform signalprocessing operations at bit-slice speeds while providing a system design as simple as a single-chip, programmable DSP (digital signal processor). The authors describe the architecture and performance of the TMC2310 and how it can be used to implement high-speed, nonrecursive digital filters.< >
Two algorithms are presented for online estimation of the optimal gain of the Kalman filter applied to sensor signals when the signal-to-noise ratio is unknown. First-order spectra of a pure signal and coloured measur...
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Two algorithms are presented for online estimation of the optimal gain of the Kalman filter applied to sensor signals when the signal-to-noise ratio is unknown. First-order spectra of a pure signal and coloured measurement noise are assumed. The proposed adaptive Kalman filtering algorithms have been tested for errors of the pure signal estimation. Although the tests have been performed for stationary signals, the algorithms can also be used successfully for time-varying sensor signals when the signal-to-noise ratio varies in comparison to the length of the adaptation step.< >
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