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Online adaptive Kalman filtering algorithms for sensor signals with coloured noise

Online adaptive Kalman filtering algorithms for sensor signa...

引用

IEEE conference on Decision and Control

作者： P. Wojcik Advanced Technologies Department Alberta Research Council Calgary AB Canada

Two algorithms are presented for online estimation of the optimal gain of the Kalman filter applied to sensor signals when the signal-to-noise ratio is unknown. First-order spectra of a pure signal and coloured measurement noise are assumed. The proposed adaptive Kalman filtering algorithms have been tested for errors of the pure signal estimation. Although the tests have been performed for stationary signals, the algorithms can also be used successfully for time-varying sensor signals when the signal-to-noise ratio varies in comparison to the length of the adaptation step.< >

关键词： Kalman filters Filtering algorithms Colored noise signal to noise ratio Noise measurement Nonlinear filters White noise Testing signal design signal processing

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A Logic Programming Approach For DSP Architectures Design

A Logic Programming Approach For DSP Architectures Design

引用

Asilomar conference on signals, Systems & Computers

作者： M.A. Bayoumi K.A. Elleithy The Center for Advanced Computer Studies University of Southwestern Louisiana Lafayette IA USA

This paper introduces a logic programming approach for specifying, simulating, and testing Digital signal processing (DSP) systems. Prolog is used as a Hardware Description Language and a, host one, too. Backtracking and pattern matching of Prolog are employed for simulation and testing, respectively. Prolog provides homogeneity to the developed system as it supports hierarchical development and mixing of description at various hierarchical levels. The developed sys tem belongs to Algorithmic Specific CAD family. It can be employed for many DSP algorithms and applications development.

关键词： Logic programming Digital signal processing Design methodology signal processing algorithms Design automation Very large scale integration Circuit simulation Hardware Pattern matching Natural languages

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DSP analog front end

DSP analog front end

引用

International conference on Acoustics, Speech, and signal processing (ICASSP)

作者： H. Davoody D. Ward D. Hester W. Rowand Texas Instruments Inc. Dallas TX USA

A description is given of the TLC32040, a programmable analog interface system fabricated with advanced LinCMOS technology and capable of serving a significant portion of the speech and modem markets. Its versatility lends its use to a wide variety of digital signal processing (DSP) systems, providing each with a lower cost solution than its own volume could drive. The direct interface of TLC32040/1 to the TMS320C25 and TMS320C17 DSP processors is illustrated.< >

关键词： Digital signal processing Filters Frequency Modems Data acquisition signal processing algorithms signal generators Speech Low-frequency noise Integrated circuit noise

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Adaptive smoothing of evoked potentials: a new approach

Adaptive smoothing of evoked potentials: a new approach

引用

Annual International conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： C. Doncarli L. Goerig LAN/UA CNRS 828 ENSM Nantes France

The evoked potentials recorded on the scalp are generally so disturbed by different biological noises that they require more and more advanced signal-processing methods, whose efficiency does not in all cases compensate the unavoidable drawbacks due to the increasing modeling complexity. A proposed alternative is the use of a simple suitable statistical model whose principal aim is to allow the design of a robust and efficient processing algorithm. The authors show that the robustness of the algorithm can largely compensate for the simplicity of the chosen model.< >

关键词： Smoothing methods Filtering signal processing Biological system modeling signal processing algorithms Noise robustness signal to noise ratio Brain modeling Wiener filter signal resolution

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A fault-tolerant bit-serial array structure for digital filters

A fault-tolerant bit-serial array structure for digital filt...

引用

International conference on Acoustics, Speech, and signal processing (ICASSP)

作者： R. Roy M.A. Bayoumi The Center for Advanced Computer Studies University of Southwestern Louisiana Lafayette LA USA

The authors propose a bit-serial structure using systolic arrays in the implementation of a finite-impulse-response (FIR) algorithm for large sizes of data and higher-order filters. The bit cells are arranged in a 2-D array which enhances the extensibility and provides efficiency for high-precision data. Barrel shifters are used on the cell level which increases the throughput of the proposed pipelined structure. Moreover, the proposed architecture has distributed error-control features. The necessity of such distributed fault-tolerance in DSP (digital signal processing) architectures is due to its susceptibility to permanent and intermittent errors caused by the high complexity of these circuit structures.< >

关键词： Fault tolerance Digital filters Digital signal processing Silicon Systolic arrays Finite impulse response filter Circuits signal processing algorithms Very large scale integration Delay

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SPARTA: multiple signal processors for high-performance robotic control

SPARTA: multiple signal processors for high-performance robo...

引用

IEEE International conference on Robotics and Automation (ICRA)

作者： J. Ish-halom P. Kazanzides IBM Thomas J. Watson Res. Center Yorktown Heights NY USA Brown University Providence RI USA

The SPARTA (signal processor for advanced robot technology applications) system is a hybrid computer which includes: (1) program development environment on an IBM VM/CMS mainframe computer; (2) user interface and runtime support on an IBM PC; and (3) real-time computation and I/O using multiple IBM Hermes signal processors situated on the IBM PC bus. The program-development environment includes the PLH high-level language for generating efficient real-time Hermes code. The runtime supports symbolic debugging, dynamic loading, and synchronous switching of control algorithms during real-time program execution. The real-time environment includes an operating system which supports foreground and background task execution and real-time data collection and display. A SPARTA system with three Hermes signal processors is currently being used to develop control algorithms for a two-axis fast direct-drive Cartesian robot at sample rates in excess of 10 kHz;.< >

关键词： signal processing Robots Computer interfaces Real time systems Runtime signal processing algorithms Application software Virtual manufacturing Collision mitigation User interfaces

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A new, highly parallel, 32 bit floating point DSP vector signal processor

A new, highly parallel, 32 bit floating point DSP vector sig...

引用

International conference on Acoustics, Speech, and signal processing (ICASSP)

作者： A. Genusov P. Feldman R. Friedlander V. Fruchter R. Jaliff A. Mohr R. Shenhav Advanced Technology Center Zoran Microelectronics Limited Haifa Israel

A new 32-bit floating point (IEEE standard) (digital signal processing) DSP vector signal processor architecture is described. The internal architecture is highly parallel. It is based on six well coordinated, independent machines. The ALU (arithmetic logic unit) has a pipeline structure optimized for the execution of DSP and matrix operations (FFT butterflies in particular). The highly flexible set of vectorized instructions allows for most efficient utilization of the internal assets. Together these features yield a high performance, high throughput processor with 31-Mflops computation power and very minimal overhead. A description is given of the architecture of the device, the different internal units and their coordination. The instruction set basic features are presented, and a few benchmarks of a single processor are given. A simple, minimal system architecture combining two processors sharing a single bus, doubling the throughput of a single processor system, is suggested.< >

关键词： Digital signal processing signal processing Pipelines Throughput Computer architecture Microelectronics High performance computing Vector processors signal processing algorithms Computer aided instruction

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An analog speech scrambler using the FFT technique with high-level security

An analog speech scrambler using the FFT technique with high...

引用

IEEE International conference on Communications (ICC)

作者： A. Matsunaga K. Koga M. Ohkawa Meguro Research and Development Laboratories Kokusai Denshin Denwa Company Limited Japan

A full-duplex analog speech-scrambling system is proposed for the application to mobile communication systems and public-switched telephone networks. The scrambling algorithm is based on the rearrangement of the fast Fourier transform (FFT) coefficients accompanied by adaptive dummy spectrum insertion and companding operations. Simulations results indicate that the scrambled speech has no residual intelligibility and the unscrambled speech quality is satisfactory. The hardware unit is implemented by using seven advanced digital signal processing (DSP) chips, including those for an echo canceller for full-duplex operation and an adaptive equalizer.< >

关键词： signal processing algorithms Communication system security Fast Fourier transforms Hardware Speech codecs Telephony Cryptography Modems Speech processing Frequency

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Wafer-scale systolic array for adaptive antenna processing

Wafer-scale systolic array for adaptive antenna processing

引用

International conference on Acoustics, Speech, and signal processing (ICASSP)

作者： C.M. Rader MIT Lincoln Laboratories Lexington MA USA

A wafer-scale VLSI system is being built to determine the weights for an adaptive antenna application. The data are sampled N-component vector time series X(n), with components that are time functions observed at N individual antenna ports. The processed output, y(n), is a weighted sum of the components, e.g. W/sup t/X(n). In practice, the author expects to computer W a few hundred times per second, based on observations of many exponentially windowed samples of X which arrive two-orders-of-magnitude more frequently. The algorithm used for determining W is based on the use of Givens transformations to rotate the original data into a lower triangular matrix, after which the desired weights are the solution to a triangular set of linear equations. The computational cost of this algorithm (and of almost all other algorithms which find the optimum weights) increases with N, the number of degrees of freedom, as N/sup 3/, so for sufficiently large N, some degree of parallelism must be used. An advanced architecture which uses N/2 processors connected in a linear chain, suitable for realizing this algorithm for N=64 in a systolic VLSI wafer-scale design, is described.< >

关键词： Systolic arrays Adaptive arrays Very large scale integration Laboratories Antenna accessories Equations Computational efficiency Parallel processing Computer architecture Algorithm design and analysis

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PROGRAMMABLE SYSTOLIC ARRAY FOR advanced signal processing.

PROGRAMMABLE SYSTOLIC ARRAY FOR ADVANCED SIGNAL PROCESSING.

引用

conference Record - Twentieth Asilomar conference on signals, Systems & Computers.

作者： Friedlander, Benjamin Saxpy Computer Corp Sunnyvale CA USA Saxpy Computer Corp Sunnyvale CA USA

ISBN: (纸本)0818608161

An architecture for advanced signal processing is presented that combines a linear systolic array, a global data path, and local memory into a highly flexible programming processor. Block algorithms provide a useful approach for mapping algorithms into this architecture. Some of the performance tradeoffs associated with these algorithms are discussed.

关键词： signal processing

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