Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signalprocessing units in mobile terminal architectures. Thus low power implement...
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ISBN:
(纸本)0780366336
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signalprocessing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (Turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on system level by the use of an intelligent cancellation technique, on implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case energy consumption to 55% using data of state-of-the-art processors. Our approach is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of Turbo-decoders based on voltage scheduling for third generation wireless systems.
Compressed video bitstreams require protection from channel errors in a wireless channel. The three-dimensional (3-D) SPIHT coder has proved its efficiency and its real-time capability in compression of video. A forwa...
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ISBN:
(纸本)0819441880
Compressed video bitstreams require protection from channel errors in a wireless channel. The three-dimensional (3-D) SPIHT coder has proved its efficiency and its real-time capability in compression of video. A forward-error-correcting (FEC) channel (RCPC) code combined with a single ARQ (automatic-repeat-request) proved to be an effective means for protecting the bitstream. In this paper, the need for ARQ is eliminated by making the 3-D SPIHT bitstream more robust and resistant to channel errors. Packetization of the bitstream and the reorganization of these packets to achieve scalability in bit rate and/or resolution in addition to robustness is demonstrated and combined with channel coding to not only protect the integrity of the packets, but also allow detection of packet decoding failures, so that only the cleanly recovered packets are reconstructed. In extensive comparative tests, the reconstructed video is shown to be superior to that of MPEG-2, with the margin of superiority growing substantially as the channel becomes noisier.
This Volume 2 of 2 of the conference proceedings contains 160 papers. Topics discussed include wireless communication and signalprocessing, algorithms for MIMO links, modulation and detection techniques, signal detec...
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This Volume 2 of 2 of the conference proceedings contains 160 papers. Topics discussed include wireless communication and signalprocessing, algorithms for MIMO links, modulation and detection techniques, signal detection and classification, adaptive communications and arrays, image segmentation and frequency domain processing, multiple user/multiple access techniques, digital signalprocessingarchitectures, hyperspectral processing and multisignals or data fusion, computer arithmetic implementations and FPGA designs, radar and sonar processing, equalization and synchronization techniques, higher order statistical signalprocessing for communications, adaptive signalprocessing in communication, speech coding and processing, wireless systems, special arithmetic techniques, biomedical imaging and advanced modulation and channel estimation.
Adaptive array systems require the periodic solution of the well-known w = (R) over tilde (-1)v equation in order to compute optimum adaptive array weights. The covariance matrix (R) over tilde is estimated by forming...
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ISBN:
(纸本)0819441880
Adaptive array systems require the periodic solution of the well-known w = (R) over tilde (-1)v equation in order to compute optimum adaptive array weights. The covariance matrix (R) over tilde is estimated by forming a product of noise sample matrices X : (R) over tilde = (XX)-X-H. The operations-count cost of performing the required matrix inversion in real time can be prohibitively high for a high bandwidth system with a large number of sensors. Specialized hardware may be required to execute the requisite computations in real time. The choice of algorithm to perform these computations must be considered in conjunction with the hardware technology used to implement the computation engine. A systolic architecture implementation of the Givens rotation method for matrix inversion was selected to perform adaptive weight computation. The bit-level systolic approach enables a simple ASIC design and a very low power implementation. The bit-level systolic architecture must be implemented with fixed-point arithmetic to simplify the propagation of data through the computation cells. The Givens rotation approach has a highly parallel implementation and is ideally suited for a systolic implementation. Additionally, the adaptive weights are computed directly from the sample matrix X in the voltage domain, thus reducing the required dynamic range needed in carrying out the computations. An analysis was performed to determine the required fixed-point precision needed to compute the weights for an adaptive array system operating in the presence of interference. Based on the analysis results. it was determined that the precision of a floating-point computation can be well approximated with a 13-bit to 19-bit word length fixed point computation for typical system jammer-to-noise levels. This property has produced an order-of-magnitude reduction in required hardware complexity. A synthesis-based ASIC design process was used to generate preliminary layouts. These layouts were used t
Low power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signalprocessing units in mobile terminal architectures. Thus low power implement...
详细信息
ISBN:
(纸本)0780366336
Low power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signalprocessing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on the system level by the use of an intelligent cancellation technique, and on the implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case energy consumption to 55% using data of state-of-the-art processors. Our approach is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of turbo-decoders based on voltage scheduling for third generation wireless systems.
In this paper we combine two recently developed multi-scale deconvolution algorithms, known as the scale-time domain method and the sum-of-cumulants domain method. We formulate the deconvolution problem in the scale-c...
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ISBN:
(纸本)0819437611
In this paper we combine two recently developed multi-scale deconvolution algorithms, known as the scale-time domain method and the sum-of-cumulants domain method. We formulate the deconvolution problem in the scale-cumulant domain using the Scale Transform (ST) and show that the procedure is simpler when the unknown source signal is non-minimum phase and robust if Gaussian noise exists.
Media signalprocessing requires high computing power and the algorithms exhibit a great deal of parallelism on low precision data. The basic components of multi-media objects are usually simple integers with 8, 12, o...
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ISBN:
(纸本)0819437611
Media signalprocessing requires high computing power and the algorithms exhibit a great deal of parallelism on low precision data. The basic components of multi-media objects are usually simple integers with 8, 12, or 16 bits of precision. In order to support efficient processing of media signals, Instructions Set Architecture (ISA) of the traditional processors requires modifications. In this paper, we present the quantitative analysis and the computational complexity required to perform media processing. Main classes of instructions that are needed for the required level of performance of the Media Processor are identified. Their efficient implementation and effect on the processor data-path is discussed. The main operations required in media processing are Addition (with or without saturation), Multiplication (with or without rounding), Sum of Products, and Average of two numbers.
We present a general procedure for obtaining equations of motion for the Wigner distribution of functions that are governed by ordinary and partial differential equations. For the case of fields we show that in genera...
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ISBN:
(纸本)0819437611
We present a general procedure for obtaining equations of motion for the Wigner distribution of functions that are governed by ordinary and partial differential equations. For the case of fields we show that in general one must consider Wigner distributions of the four variables, position, momentum, time and frequency. We also show that in general one cannot write an equation of motion for position and momentum however it can be done in some cases, the Schrodinger equation being one such case. Our method leads to an equation of motion for the Schrodinger equation with time dependent potentials in contrast to the result obtained by Wigner and Moyal which was for time independent potentials.
This study has been realized to improve industrial machines that allow to analyze planks by detecting their width and too important defects thanks to a computer vision system. These machines are currently piloted by s...
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ISBN:
(纸本)0819437611
This study has been realized to improve industrial machines that allow to analyze planks by detecting their width and too important defects thanks to a computer vision system. These machines are currently piloted by software with the help of PCs. The aim of our work is to realize a hardware card to increase the processing speed.
Let P be a symmetric positive definite Pick matrix of order n. The following facts will be proven here: 1. P is the Gram matrix of a set of rational functions, with respect to a inner product defined in terms of a &qu...
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ISBN:
(纸本)0819437611
Let P be a symmetric positive definite Pick matrix of order n. The following facts will be proven here: 1. P is the Gram matrix of a set of rational functions, with respect to a inner product defined in terms of a "generating function" associated to P;2. Its condition number is lower-bounded by a function growing exponentially in n. 3. P can be effectively preconditioned by the Pick matrix generated by the same nodes and a constant function.
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