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conference on Optoelectronic and microelectronic Materials and devices

作者： Milos Toth Aiden A. Martin Toby W. Shanley Igor Aharonovich School of Physics and Advanced Materials University of Technology Sydney New South Wales Australia

Controlled fabrication of semiconductor nanostructures is a prerequisite step in the engineering of next generation photonic and optoelectronic devices. Here we describe two advances in electron beam processing of single crystal diamond: (i) chemical dry etching of optically active nanostructures, and (ii) chemical switching of the charge state of nitrogen-vacancy centers by surface fluorination. Etching and fluorination are realized by irradiating diamond by kiloelectronvolt electrons at room temperature in the presence of H 2 O and NF 3 vapor, respectively. The techniques do not generate defects that quench luminescence, thereby enabling the fabrication and editing of optically active nanostructures and diamond-based devices.

关键词： Diamonds Electron beams Etching Optical device fabrication Nanostructures Nitrogen

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Assembly of mechanically compliant interfaces between optical fibers and nanophotonic chips

Assembly of mechanically compliant interfaces between optica...

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Electronic Components and technology conference (ECTC)

作者： Tymon Barwicz Yoichi Taira Hidetoshi Numata Nicolas Boyer Stephane Harel Swetha Kamlapurkar Shotaro Takenobu Simon Laflamme Sebastian Engelmann Yurii Vlasov Paul Fortier IBM T.J. Watson Research Center Yorktown Heights NY USA IBM Research - Tokyo Saiwai-ku Kawasaki Kanagawa Japan IBM Bromont Bromont QC Canada Asahi Glass Co. AGC Electronics Yokohama Japan

Silicon nanophotonics may bring disruptive advances to datacom, telecom, and high performance computing. However, the deployment of this technology is hampered by the difficulty of cost efficient optical inputs and outputs. To address this challenge, we have recently proposed a low-cost, mechanically compliant polymer interface between standard single mode fibers and nanophotonic waveguides. Our concept promises better mechanical reliability and better optical performance than existing technology. To manage the cost of assembly, we show here that self-alignment features can be effectively used to bridge the gap between the accuracy required by single-mode optics (1-2 um) and the capability of high-throughput microelectronic assembly equipment (~10 um). We describe the complaint interface, the assembly strategy, and the design of our re-alignment features. We demonstrate experimentally that misalignments at assembly as large as +/-10 um are re-aligned by our self-alignment structures to +/-1 to 2 um. Our approach enables existing microelectronics equipment to be used for singlemode optics assembly.

关键词： Optical waveguides Assembly Accuracy Optical polymers Optical fiber cables Optical device fabrication

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Temporary wafer bonding materials and processes

Temporary wafer bonding materials and processes

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8th Annual IMAPS International conference and Exhibition on device Packaging, DPC 2012 - In Conjunction with the Global Business Council, GBC 2012 Spring conference

作者： Lueck, Matthew Garrou, Phil Malta, Dean Huffman, Alan Butler, Marianne Temple, Dorota S. RTI International Center for Materials and Electronic Technologies Research Triangle Park NC 27709 United States Microelectronic Consultants Research Triangle Park NC 27709 United States

Recent years have seen significant advances in temporary wafer bonding with materials providers seeking to meet the growing demands of 2.5D and 3D applications. Many types of temporary bonding solutions have been developed that use different methodologies for bond and de-bond. We have examined four different types of temporary wafer bonding materials for use in two separate applications: a face-up, stackable 3D-IC application with TSVs and backside Cu/Sn interconnects, and a silicon interposer with large TSVs, polymer dielectrics, and solder balls. We present results of the fabrication of these two types of test vehicles and discuss the compatibility of the process flows with the temporary wafer bonding materials. For the 3D-IC application, 15 μm thin silicon wafers on three different temporary bond materials were processed through BEOL processes for the passivation, electroplating, and bonding of Cu/Sn microbumps. For the silicon interposer application, results will be reported from a test vehicle lot on the compatibility of two different temporary bond materials with three photoimageable polymer dielectrics and with the process for bumping and de-bonding.

关键词： Wafer bonding

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advances in CMP for TSV Reveal

Advances in CMP for TSV Reveal

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ICPT 2012 - International conference on Planarization/CMP technology

作者： Robert L. Rhoades Dean Malta Entrepix 2315 W. Fairmont Drive Tempe AZ 85282 USA RTI International 3040 Cornwallis Road Research Triangle Park

microelectronic devices using through silicon vias (TSV’s) are now available in the market for some advanced applications and many more are being developed. The design goals usually include reducing parasitic losses and shrinking final form factors. The process sequence for a TSV module generally requires a combination of deep via etch, liner deposition, barrier deposition, via fill, damascene CMP (Cu or other conductor), temporary carrier mounting, thinning, stress relief and via reveal steps. The last step, via reveal, is the focus of this presentation. After forming the TSV’s and finishing other process steps from the front or device side of the wafer, a typical process sequence then proceeds to mounting the device side to a carrier substrate and using backgrind to remove a substantial portion of the original device substrate. The Si remaining over the vias (from a few microns to several 10’s of microns) is driven by the original TSV etch depth and the target amount to be removed in the reveal step which are two of the design parameters. In some integrations, the via reveal step consists of a single step CMP process to remove the rest of the Si, as well as the liner and barrier layers in the original "bottom" of the via, exposing the conductive core at the center of the TSV. In this case, the via reveal step is performed entirely with CMP and must be developed to achieve the following: remove Si at a high rate to avoid overly long polish times, remove the oxide liner covering the bottom of the via, remove the barrier metal, planarize the Cu with the surrounding surface and provide controlled topography (low dishing), low roughness and low defectivity (no scratching). For several years, the common approach to this set of goals has been a multi-step polishing sequence with at least 2 and sometimes 3 different slurries on different pads on a multi-platen polisher. Data will show that all of these goals can be achieved using a single slurry on a single polishing pad.

关键词： Silicon Through-silicon vias Slurries Surface treatment Surface topography Films

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Editorial Special Section on the 2011 International conference on microelectronic Test Structures

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IEEE Transactions on Semiconductor Manufacturing 2012年第4期25卷 541-541页

作者： Luca Selmi Università Degli Studi di Udine Udine Italy

The six papers in this special section are extended papers from the 2011 International conference on microelectronic Test Structures, held in Amsterdam, The Netherlands. The papers cover new advances in variation and stress characterization for complementary metal-oxide-semiconductor technology, improved parameter extraction techniques, and new test structures for process, doping, and temperature characterization.

关键词： Special issues and sections microelectronics Semiconductor device modeling Integrated circuit modeling CMOS technology

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Quantum processing: Feasibility studies and solutions

Quantum processing: Feasibility studies and solutions

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2011 11th IEEE International conference on Nanotechnology, NANO 2011

作者： Lyshevski, Sergey Edward Department of Electrical and Microelectronic Engineering Rochester Institute of Technology Rochester NY 14623 United States

ISBN: (纸本)9781457715143

This paper studies fundamentals of quantum processing on measurable processable compatible observables in microscopic systems which undergo quantum state transitions. The aforementioned microscopic devices (processing primitives) form processing fabrics. We examine the premise of quantum processing by: (1) Unifying and enabling theoretical concepts of theoretical computer science, computer engineering and quantum mechanics;(2) Examining the first principles;(3) Researching device physics;(4) Fostering fundamentally-consistent and practical microscopic hardware solutions. Vertebrates and invertebrates exhibit extraordinary information processing which is performed by biomolecules and molecular aggregates. Information processing in natural systems has not been comprehended, while engineered quantum processing is an emerging paradigm. This paradigm focuses on developments of a great number of new solutions such as microscopic devices, processing arithmetics (calculi), system architectures, etc. The microscopic processing primitives must exhibit utilizable quantum-effect state transitions on observables which result in computable transforms from viewpoints of processing arithmetics, calculus and design. The reported paradigm: (i) Eases enormous challenges;(ii) Overcomes foremost inconsistencies of naive algorithmically-centric computing;(iii) Enables new inroads;(iv) Promises unprecedented processing capabilities ensuring far-reaching benchmarks;(v) Significant advances theory and practice of natural and engineered processing. Our findings support a broad spectrum of transformative research activities. © 2011 IEEE.

关键词： Calculations

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Room Temperature Magnetic-Semiconductors in Modified Iron Titanates: Their Properties and Potential microelectronic devices

Room Temperature Magnetic-Semiconductors in Modified Iron Ti...

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3rd International conference on Smart Materials, Structures and Systems

作者： Pandey, R. K. Stern, H. Geerts, W. J. Padmini, P. Kale, P. Dou, J. Schad, R. Texas State Univ 601 Univ Dr San Marcos TX 78666 USA Univ Alabama Tuscaloosa AL 35487 USA

ISBN: (纸本)9783908158202

The phenomenal growths of information technology and related fields have warranted the development of new class of materials. Multifunctional oxides, magnetic-semiconductors, multiferroics and smart materials are just a few examples of such materials. They are needed for the development of novel technologies such as spintronics, magneto-electronics, radhard electronics, and advanced microelectronics. For these technologies, of particular interest are some solid solutions of ilmenite-hematite (IH) represented by (I-x) FeTiO3 center dot xFe(2)O(3) where x varies from 0 to 1;Mn-doped ilmenite (Mn+3-FeTiO3) and Mn-doped pseudobrookite, Mn+3-Fe2TiO5 (PsB). These multifunctional oxides are ferromagnetic with the magnetic Curie points well above the room temperature as well as wide bandgap, semiconductors with band gap E-g > 2.5 eV. This paper outlines: (a) processing of device quality samples for structural, electrical and magnetic characterization, (b) fabrication and evaluation of an integrated structure for controlled magnetic switching, and (c) the response of the two terminal non-linear current-voltage (I-V) characteristics when biased by a dc voltage. Subsequently, we will identify a few microelectronic applications based on this class of oxides.

关键词： iron titanates magnetic semiconductors electrically tunable varistors magnetic switching and bipolar currents

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Indium gallium arsenide on silicon interband tunnel diodes for NDR-based memory and steep subthreshold slope transistor applications

Indium gallium arsenide on silicon interband tunnel diodes f...

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67th device Research conference, DRC 2009

作者： Pawlik, D.J. Bartlf, P. Thomas Barth, M. Johnsorf, K. Rommel, S.L. Mbokerjea, S. Date, S. Luisier, M. Klimeck, G. Cheng, Z. Park, J.S. Li, J. Hydrick, J.M. Fiorenza, J.G. Lochtefeld, A. Department of Microelectronic Engineering Rochester Institute of Technology Rochester NY United States Department of Electrical Engineering State College Pennsylvania State University PA United States Network for Computational Nanotechnology Purdue University W. Lafayette IN United States Amberwave Systems Corporation Salem NH United States

ISBN: (纸本)9781424435289

advances in materials growth techniques are enabling new de vice concepts, circuit approaches, and syste m architectures to enhance a nd extend CM OS technology such as tunneling-based static random access memory [1] and steep subthreshold slope III-V tunneling field effect transistors (TFETs) [2]. TFETs are essentially gated Esaki (orbackward) diodes operating in t he reverse (Zener) direction. Rece ntly the aut hors reported on record III-V tunnel diodes fabricated on Si [3] via a technique known as aspect ratio trapping (ART) [4, 5] To the knowledge of the authors, the high PVCR (56) was the fourth highest reported for any tunnel diode structure on any substrate. In the authors, the high PVCR (56) was the fourth highest reported for any tunnel diode structure on any substrate In this study, the authors report on (i) the tern perature dependence of these d evices, (ii) the insensitivity of tunnel current (forward and Zener) to temperature, and (iii) the absence of mid-gap states in the excess current. © 2009 IEEE.

关键词： Aspect ratio

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Indium gallium arsenide on silicon interband tunnel diodes for NDR-based memory and steep subthreshold slope transistor applications

Indium gallium arsenide on silicon interband tunnel diodes f...

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device Research conference

作者： D. J. Pawlik P. Thomas M. Barth K. Johnson S.L. Rommel S. Mookerjea S. Datta M. Luisier G. Klimeck Z. Cheng J. Li J.S. Park J.M. Hydrick J.G. Fiorenza A. Lochtefeld Department of Microelectronic Engineering Rochester Institute of Technology Rochester NY USA Department of Electrical Engineering Pennsylvania State University PA USA Network for Computational Nanotechnology Purdue University West Lafayette IN USA Amberwave Systems Corporation Salem NH USA

advances in materials growth techniques are enabling new device concepts, circuit approaches, and system architectures to enhance and extend CMOS technology such as tunneling-based static random access memory and steep subthreshold slope III-V tunneling field effect transistors (TFETs). TFETs are essentially gated Esaki (or backward) diodes operating in the reverse (Zener) direction. Recently, the authors reported on record III-V tunnel diodes fabricated on Si via a technique known as aspect ratio trapping (ART). To the knowledge of the authors, the high PVCR (56) was the fourth highest reported for any tunnel diode structure on any substrate. In this study, the authors report on (i) the temperature dependence of these devices, (ii) the insensitivity of tunnel current (forward and Zener) to temperature, and (iii) the absence of mid-gap states in the excess current.

关键词： Indium gallium arsenide Silicon Diodes III-V semiconductor materials CMOS technology Temperature dependence Transistors CMOS memory circuits SRAM chips Tunneling

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advances in CD-AFM scan algorithm technology enable improved CD metrology

Advances in CD-AFM scan algorithm technology enable improved...

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conference on Metrology, Inspection, and Process Control for Microlithography XXI

作者： Mininni, Lars Foucher, Johann Faurie, Pascal Veeco Instruments 112 Robin Hill Rd Santa Barbara CA 93117 USA CEA LETI MINATEC F-38054 Grenoble France

ISBN: (纸本)9780819466372

Improving device performance and yield is one of the primary goals of microelectronic research and development. In order to attain this goal, process engineers are focusing on the integration of new materials and the development of new device architectures. For production process control, the two main techniques to monitor device dimensions are CD-SEM and Scatterometry. Despite the excellent repeatability of these techniques, SEM and Scatterometry often suffer from unacceptably large measurement uncertainty, particularly when applied to newly developed device technologies. A consequence of these metrology limitations is a delay in the transition of new process technologies into production. Furthermore, these techniques have not been proven to be effective in measuring 3-dimensional characteristics such as Line Edge Roughness and Line Width Roughness in the Bottom-CD region. A potential alternative to SEM and Scatterometry in many applications is CD-AFM, a highly versatile metrology technique, which is capable of providing consistent, precise 3-dimensional measurements for a wide range of sample types and geometries. In this paper we present a recent CD-AFM scan algorithm enhancement that significantly improves Bottom-CD measurement bias and precision. In addition, we present a separate but complementary enhancement in the CD-AFM scan algorithm, which we have demonstrated to improve overall CD measurement resolution and precision, while increasing scan speed when using advanced CD-AFM Tips. Our results show that the use of these two techniques enhances Line-Edge Roughness and Line-Width Roughness resolution, precision and accuracy.

关键词： AFM critical dimension metrology accuracy bottom-CD LER LWR

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