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On-Chip Hardware Accelerators for Data Processing and Combinatorial Search 9

On-Chip Hardware Accelerators for Data Processing and Combin...

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9th International conference of Information and Communiation Technologies (AICT)

作者： Sklyarov, Valery Skliarova, Iouliia Univ Aveiro Dept Elect Telecommun & Informat IEETA Aveiro Portugal

ISBN: (纸本)9781467368551

Data processing and combinatorial search are widely used techniques in the scope of information and communication. Examples of practical applications are sorting, frequent items encountering, matrix/set covering, graph/map coloring, data mining, priority management, and many others. Often information/data processing that involves the listed above tasks has to be done in embedded systems where high performance needs to be achieved in portable and low-cost devices integrating multiple functions and capabilities. An efficient development technique for such systems is hardware/software co-design with the use of programmable systems-on-chip that are highly integrated, easily customizable/configurable and permit broad parallelism to be supported that is the primary way to accelerate computations. The tutorial is dedicated to such a design technique.

关键词： Data processing combinatorial search high-performance computing parallelism programmable systems-on-chip

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applications of the Illimitable Space System in the Context of Media technology and On-Stage Performance: a Collaborative Interdisciplinary Experience 7

Applications of the Illimitable Space System in the Context ...

引用

2015 IEEE Games Entertainment Media conference GEM

作者： Song, Miao Mokhov, Serguei A. Thomas, Jilson Mudur, Sudhir P. Concordia Univ Montreal PQ Canada

ISBN: (纸本)9781467374521

Real-time video production technology has to do with adding visual effects at the time of a performance production itself. This work describes research-creation, development and use of a software system, Illimitable Space System (ISS), in interactive artistic performance productions. ISS is a real-time interactive configurable toolbox used to create visual effects and musical visualizations based on input such as voice or gestures with the corresponding image mapping and also with multiple input devices. The production team created and used a subset of the features of the ISSv2 toolbox for an interactive artistic performance. ISS makes it easy to explore rapid prototyping of interactive graphical applications using Jitter/Max and Processing with OpenGL, shaders, and featuring connectivity with various devices. Such a rapid prototyping environment is ideal for entertainment computing, as well as for artists using interactive graphics for real-time performances. We share the expertise we developed in connecting real-time graphics with on-stage performance using the Illimitable Space System (ISS) v2.

关键词： ISSv2 Kinect Jitter/MAX Processing multi-modal interaction

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Design and auditing of Cloud computing security

Design and auditing of Cloud computing security

引用

2010 5th International conference on Information and Automation for Sustainability, ICIAfS 2010

作者： Gowrigolla, Bhagyaraj Sivaji, Sathyalakshmi Masillamani, M. Roberts Dept. of Computer Science and Engineering Hindustan Institute of Technology and Science India

ISBN: (纸本)9781424485512

Cloud computing is the long dreamed vision of computing as a utility, where data owners can remotely store their data in the cloud to enjoy on-demand high-quality applications and services from a shared pool of configurable computing resources. While data outsourcing relieves the owners of the burden of local data storage and maintenance, it also eliminates their physical control of storage dependability and security, which traditionally has been expected by both enterprises and individuals with high service-level requirements. This paper, gives a brief introduction to Cloud computing privacy issue being addressed is then introduced, by describing some of the unique factors to be considered when data enters the Cloud. Finally, a data protection scheme with public auditing scheme is outlined that will address a number of these factors, by providing a mechanism to allow for data to be encrypted in the Cloud without loss of accessibility or functionality for authorized parties. This scheme is not necessarily a replacement for traditional privacy and security measures for data, but rather an enhancement which allows users (again, at either the individual or enterprise level) a greater degree of confidence in the adoption of innovative, cost-saving Cloud computing technologies. © 2010 IEEE.

关键词： Data privacy

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Determining Energy Consumption in Heterogenous Cloud computing by Usage of RMRECFS Workflow with Cost Confinement 4

Determining Energy Consumption in Heterogenous Cloud Computi...

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4th International conference on Inventive Research in computing applications, ICIRCA 2022

作者： Kumar, N Praveen Sundra Arjun, S. Dhivya, B. Sri, S K Shruthi Dr. Mahalingam College of Engineering and Technology Department of Information Technology Coimbatore India

ISBN: (数字)9781665497077

ISBN: (纸本)9781665497077

For large-scale workflow applications, the cloud is a promising platform. The pay-per-use model is used. In cloud data centers, reducing the energy utilization of priority-limited cost-cutting workflows limits became a hot topic. The majority of existing scheduling algorithms focus on the completion time as well as cost of a particular workflow application while working within cost limitations;These algorithms, however, fail to account for energy savings. The critical task remapping and frequency scaling RMRECFS (Re-Mapping based Reducing Energy Consumption with Frequency Scaling) method is used in this work to provide an approach for reducing energy consumption. Energy utilization reduction and key task remap are two steps of this technique. The cost budget, critical work path, and expandable budget factor are all included to determine the adjustable cost budget and additional costs in the first stage. To execute a preliminary task and task mapping virtual machines when adhering to configurable budget restrictions, most workflow tasks are then distributed to VMs that spend some least amount of power. By reallocating key jobs and applying frequency scaling to virtual machines based on spare costs, the second phase minimizes power consumption owing to task relocation. Experiment with two different types of workflow applications at various ranges show that the provided RMRECFS algorithm efficiently saves energy usage while staying within budget limitations when compared to the conventional RMREC algorithm © 2022 IEEE.

关键词： Energy utilization

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Towards Asynchronously Triggered Spiking Neural Network on FPGA for Event-based Vision 22

Towards Asynchronously Triggered Spiking Neural Network on F...

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22nd International conference on Field Programmable technology (ICFPT)

作者： Wu, Zhenyu Song, Mo So, Hayden Kwok-Hay Univ Hong Kong Dept Elect & Elect Engn Hong Kong Peoples R China

ISBN: (纸本)9798350359114

In this paper, the design and implementation of an asynchronously-triggered spiking neuron tailored for FPGA implementations is presented. The asynchronous triggering mechanism is designed to effectively preserve the spatial-temporal information captured by event-based vision sensors. Neurons of the target network model are implemented using the configurable logic blocks of an FPGA spatially and communicate through an asynchronous handshaking protocol. Without using a global clock to synchronize operations of the neurons, energy consumption and inference latency are minimized. The proposed design is composable and scalable for applications with different spiking neural network (SNN) configurations. Experimental results show that the proposed design is able to achieve 95.76% accuracy on the N-MNIST dataset while consuming less than 1 mW dynamic power on an Xilinx ZCU102 board.

关键词： Spiking neural network asynchronous circuit FPGA dynamic vision sensor neuromorphic computing

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One Self-configurable Model to Solve Many Abstract Visual Reasoning Problems 38

One Self-Configurable Model to Solve Many Abstract Visual Re...

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38th AAAI conference on Artificial Intelligence (AAAI) / 36th conference on Innovative applications of Artificial Intelligence / 14th Symposium on Educational Advances in Artificial Intelligence

作者： Malkinski, Mikolaj Mandziuk, Jacek Warsaw Univ Technol Fac Math & Informat Sci Warsaw Poland AGH Univ Krakow Fac Comp Sci Krakow Poland

ISBN: (纸本)1577358872

Visual Reasoning (AVR) comprises a wide selection of various problems similar to those used in human IQ tests. Recent years have brought dynamic progress in solving particular AVR tasks, however, in the contemporary literature AVR problems are largely dealt with in isolation, leading to highly specialized task-specific methods. With the aim of developing universal learning systems in the AVR domain, we propose the unified model for solving Single-Choice Abstract visual Reasoning tasks (SCAR), capable of solving various single-choice AVR tasks, without making any a priori assumptions about the task structure, in particular the number and configuration of panels. The proposed model relies on a novel Structure-Aware dynamic Layer (SAL), which adapts its weights to the structure of the considered AVR problem. Experiments conducted on Raven's Progressive Matrices, Visual Analogy Problems, and Odd One Out problems show that SCAR (SAL-based models, in general) effectively solves diverse AVR tasks, and its performance is on par with the state-of-the-art task-specific baselines. What is more, SCAR demonstrates effective knowledge reuse in multi-task and transfer learning settings. To our knowledge, this work is the first successful attempt to construct a general single-choice AVR solver relying on self-configurable architecture and unified solving method. With this work we aim to stimulate and foster progress on task-independent research paths in the AVR domain, with the long-term goal of development of a general AVR solver.

关键词： Learning systems

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Circular Polarized Re-configurable Patch Antenna for Futuristic Wireless Communication 3

Circular Polarized Re-Configurable Patch Antenna for Futuris...

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3rd International conference on computing, Mathematics and Engineering Technologies, iCoMET 2020

作者： Ahmad, Arsalan Raza, Ali Farhat, Sidra Arshad, Farzana University of Engineering and Technology Department of Telecommunication Engineering Taxila Pakistan

ISBN: (纸本)9781728149707

A novel, compact circularly polarized elliptical patch antenna array for 5G applications is presented. The design is printed on mmrilly vilbl substrate Rogers RT/Duroid 5880 with 1.575 mm thickness. A single port microstrip feed is used to excite the structure. A ring is added at the center as a power divider and to make a circular arrangement of array elements. The 45° rotated slot is made at the right ellipse. Consequently, the electric field is divided into x and y components which provide circular polarization. The four vias are added in left upper ellipse to increase the gain. A Pin diode is used for switching purpose. The proposed structure can operate between (30.6-47.6) GHz with a gain of 9.84 dB. The design is simulated in Computer Simulation technology Microwave Studio (CST MWS). © 2020 IEEE.

关键词： Microstrip antennas

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SAT: A stream architecture template for embedded applications

SAT: A stream architecture template for embedded application...

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10th IEEE International conference on Computer and Information technology, CIT-2010, 7th IEEE International conference on Embedded Software and Systems, ICESS-2010, 10th IEEE Int. Conf. Scalable computing and Communications, ScalCom-2010

作者： Yang, Qianming Wu, Nan Wen, Mei He, Yi Su, Huayou Zhang, Chunyuan Computer School National University of Defense Technology Chang Sha Hu Nan 410073 China

ISBN: (纸本)9780769541082

The increase of embedded applications complexity has demanded hardware more flexible while providing higher performance. Reconfigurable architectures and stream processing have been showed significant progresses in exploiting these applications. This paper presents SAT, a stream architecture template that combines stream processing, clustered-VLIW, multi-core, and hardware reuse to achieve the capability of high performance and high flexibility. In order to enhance the efficiency of the auto-generated circuit, we introduced the idea of parameter and template in SAT. In this paper, we also demonstrated a flow of generating the target system based on SAT. The system is implemented in VerilogHDL, and consists of configurable stream core, RISC core, memory core, IO core, and interconnect core. The diverse stream-based implementation of stream core can be configured easily according to the requirements of applications. The system has also been synthesized into an Altera FPGA to verify resource utilization and performance. © 2010 IEEE.

关键词： Reconfigurable architectures

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Research of a Mixed-signal Programmable SoC Based on FPAA

Research of a Mixed-signal Programmable SoC Based on FPAA

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International conference on Mechatronics Engineering and computing technology (ICMECT)

作者： Deng, Jun Tan, Huayong Liu, Luncai Liu, Lintao Sichuan Inst Solid State Circuits Chongqing 400060 Peoples R China

ISBN: (纸本)9783038351153

This paper presents a novel architecture for mixed-signal SoC, which integrates a Field Programmable Analog Array (FPAA) into a SoC based on 32-bit RISC CPU. The FPAA unit can be configured as Filter, Comparator, Gain Amplifier, and so on. The proposed mixed-signal SoC can transform the intermediate frequency (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing, besides this, which can transmit the modulated IF signals which are converted from baseband signals by digital up-conversion (DUC). The proposed mixed-signal SoC is a transceiver on chip actually, due to the internal integrated IPs, such as ADC, DAC, DDC and DUC, which can provide smaller board area, lower power consumption and the system cost for the product development of transceiver. This design will have a good potential for wireless communication applications.

关键词： Field Programmable Analog Array configurable Analog Block Mixed-signal Programmable SoC Transceiver

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Development of an Open ISA GPGPU for Edge Device Machine Learning applications 11

Development of an Open ISA GPGPU for Edge Device Machine Lea...

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11th International conference on Ubiquitous and Future Networks (ICUFN)

作者： Su, Yu-Xiang Jheng, Jhi-Han Chen, Dun-Jie Chen, Chung-Ho Natl Cheng Kung Univ Dept Elect Engn Tainan Taiwan Natl Cheng Kung Univ Inst Comp & Commun Engn Tainan Taiwan

ISBN: (纸本)9781728113395

Hosting the deep learning model on the cloud may not be the best solution in many cases, for instance, IoT applications or autonomous system where low latency or enhanced security is desirable. Deep learning on the edge alleviates the above issues, and provides benefits of local computation. In this paper, we present the development of an open ISA (instruction set architecture) general purpose GPU aimed at edge computation. Our GPU, CASLab GPU, uses license-free, royalty-free HSAIL ISA specification and supports OpenCL1.2/2.0 APIs for heterogeneous computing. CASLab GPU also supports TensorFlow framework with CUDA-on-CL technology. CASLab GPU IP with configurable SIMT Core design tailors directly to the computing need of on-device learning and inference. The GPU is developed in ESL design methodology which incorporates GPU micro-architecture exploration, power modelling of the GPU, and the co-simulation of the GPU software stack.

关键词： Deep learning Edge computation ESL design methodology GPGPU SLUT operation

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