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检索条件"任意字段=Conference on Configurable Computing - Technology and Applications"

共 333 条记录，以下是151-160 订阅

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ERDB: An Embedded Routing Database for reconfigurable systems

ERDB: An Embedded Routing Database for reconfigurable system...

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21st International conference on Field Programmable Logic and applications, FPL 2011

作者： Kȩpa, Krzysztof Morgan, Fearghal Athanas, Peter Technology Center Nokia Siemens Networks Sp. Z O.o. Wroclaw Poland Electrical and Electronic Eng. National University of Ireland Galway Ireland Configurable Computing Lab. ECE Virginia Tech. Blacksburg VA United States

ISBN: (纸本)9780769545295

This work presents an Embedded Routing Database (ERDB), which contains the complete description of the inter-tile routing shapes available in various Xilinx FPGA tiles, and the mapping of Programmable Interconnection Point (PIP) bits within the FPGA configuration bitstream. ERDB provides the RC system with knowledge of its own architecture and facilitates RC systems in implementing autonomic (self-managing and adaptive) computing. ERDB also protects the integrity of the RC system and supports design Intellectual Property (IP) protection. The paper describes the automated generation of a size-optimised ERDB (3.7 MB memory footprint for the Virtex-5 LX50T device) and its application within the Secure Reconfiguration Controller (SeReCon), as a minimised FPGA fabric description for on-line verification of IP core's integrity during partial reconfiguration. Results demonstrate the feasibility and accuracy of the SeReCon/ERDB-based design (IP core) routing verification that, when applied to an example IP block, detects >99% of the configured PIPs. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Design and implementation of a production dynamically configurable testbed 10

Design and implementation of a production dynamically config...

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2010 TeraGrid conference, TG '10

作者： Welshons, Kenny Dorn, Patrick Hutanu, Andrei Holub, Petr Vollbrecht, John Allen, Gabrielle Louisiana Optical Network Initiative 200 Fred Frey Building Baton Rouge LA 70803 United States National Center for Supercomputing Applications University of Illinois at Urbana-Champaign Urbana IL 61801 United States Center for Computation and Technology Louisiana State University Baton Rouge LA 70803 United States Masaryk University CESNET Botanická 68a 621 00 Brno Czech Republic Internet2 1000 Oakbrook Drive Suite 300 Ann Arbor MI 48104 United States Department of Computer Science Center for Computation and Technology Louisiana State University Baton Rouge LA 70803 United States

ISBN: (纸本)9781605588186

Production quality high speed networks connecting end devices are needed to design and prototype new types of distributed applications. The eaviv testbed has been de-ployed to provide such a facility, connecting Louisiana State University, National Center for Supercomputing applications and Masaryk University, and enabling ser-vices for dynamic provisioning of dedicated bandwidth via Internet2 ION. This paper includes technical chal-lenges and solutions in deploying eaviv such as dealing with multiple administrative domains, network address-ing, and end-to-end connectivity. These issues apply not only to temporary testbeds, but also to networks which facilitate long-running experiments and research and whose infrastructure is global and at least partially dynamic. Copyright 2010 ACM.

关键词： HIgh speed networks

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A VLIW processor with reconfigurable instruction set for embedded applications

A VLIW processor with reconfigurable instruction set for emb...

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IEEE International Solid-State Circuits conference

作者： Lodi, A Toma, M Campi, F Cappelli, A Canegallo, R Guerrieri, R Univ Bologna ARCES I-40136 Bologna Italy

ISBN: (纸本)0780377079

This paper describes a new architecture for embedded reconfigurable computing, based on a very-long instruction word (VLIW) processor enhanced with an additional run-time configurable datapath. The reconfigurable unit is tightly coupled with the processor, featuring an application-specific instruction-set extension. Mapping computation intensive algorithmic portions on the reconfigurable unit allows a more efficient elaboration, thus leading to an improvement in both timing performance and power consumption. A test chip has been implemented in a standard 0.18-mum CMOS technology. The test of a signal processing algorithmic benchmark showed speedups ranging from 4.3 x to 13.5 x and energy consumption reduced up to 92%.

关键词： energy consumption field-programmable gatearray (FPGA) pipeline reconfigurable processor

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17th International conference on Software Engineering and Knowledge Engineering, SEKE 2005

17th International Conference on Software Engineering and Kn...

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17th International conference on Software Engineering and Knowledge Engineering, SEKE 2005

ISBN: (纸本)9781627486590

The proceedings contain 138 papers. The topics discussed include: software engineering strategies for seamless computing;a chronobot for time and knowledge exchange and management;software product line engineering;a post-auction negotiation mechanism for electronic marketplace;cricketbot - a configurable human interface software robot;towards method engineering for multi-agent systems: a preliminary validation of a generic MAS metamodel;spontaneous agent networking;a methodology for the development of multi-agent systems on wireless sensor networks;an evaluation of e-business metamodels;creating virtual collaborative team through the construction of expertise spaces;yet another purchasing specification construction in e-business;digital media - art and technology applications;an empirical study on limits of clone unification using generics;and a pattern-based approach for developing business object models with ontologies.

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The design and implementation of a reconfigurable convolution operator based on APU

The design and implementation of a reconfigurable convolutio...

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2017 China Semiconductor technology International conference, CSTIC 2017

作者： Huang, Yuqian Huang, Jipan Wang, Xin'an Yang, Zhiqiang Lu, Haifang Tian, Miren Key Laboratory of Integrated Micro-System Science and Engineering Applications Peking University Shenzhen Graduate School China

ISBN: (纸本)9781509066940

In order to achieve fast IC design, reduce development cycle and cost, Key Lab. of Integrated Microsystems in Peking University proposed Array Processing for Unification Architecture(APU) which consists of four kinds of operators: computation, data path, control and MEM operators to replace the configurable logic block in current FPGA fabric. In this paper, a reconfigurable convolution operator based on APU, is presented which is used to convolutional neural network computing. The reconfigurable convolution operator is with more coarse-grain and function changeable than APU. And the process of operator synthesis is verified by simulation-based verification and formal verification separately. With the verification method proposed in this paper, certainty and completeness have been achieved. The results show that compared with the hardware design at the cost of resources based APU, this methodology can obtain hardware of suitable performance with regular structure with the cost of 34.08% less area and 25.26% lower power. © 2017 IEEE.

关键词： Neural networks

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Design and implement of data acquisition system based on reconfigurable computing

Design and implement of data acquisition system based on rec...

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2012 International conference on Electrical Insulating Materials and Electrical Engineering, EIMEE 2012

作者： Xiong, Zhiwen Xu, Chenguang Zeng, Hong Nanchang Institute of Technology Nanchang China School of Computer Science Hangzhou Dianzi University Hangzhou China

ISBN: (纸本)9783037854518

Data acquisition begins with the physical phenomenon or physical property to be measured. Examples of this include temperature, gas pressure, and light intensity, and force, fluid flow, regardless of the type of physical property to be measured. Physical property converted into digital, and then by the computer for storage, processing, display or printing process, the corresponding system is called data acquisition system. With the rapid development of computer technology, data acquisition systems quickly gained popularity. A variety of products based on digital technology have been created. Digital System spread quickly;it's mainly the following two advantages: the first is the digital processing flexible and convenient;the second is a digital system is very reliable. The main idea of Reconfigurable computing technology [1] is using the FPGA [2][3] allows the system has a dynamically configurable capacity, suitable for harsh environment applications, improve the speed of data processing. By the use of dynamic reconfigurable FPGA devices can be realized on the hardware logic function modification, application of reconfigurable computing technology can improve the speed of data processing. Data acquisition system is widely applied in many fields, and often used the abominable working environment place. The reconfigurable computing technology, can greatly improve the data acquisition system reliability and safety. The paper introduces a kind of multi-channel data acquisition system based on USB bus and FPGA, the factors affecting the performance of system are discussed, and describes how to use reconfigurable computing technology to improve the efficiency of data acquisition system while reduce energy consumption. The system in this paper uses AD's AD9220, ALTERA's EP1C6-8 and IDT's IDT70V24, Cypress's CY7C68013. © (2012) Trans Tech Publications, Switzerland.

关键词： Energy utilization

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Development of a GT4-Based resource broker service: An application to on-demand weather and marine forecasting 1

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2nd International conference on Grid and Pervasive computing

作者： Montella, R. Univ Naples Parthenope Dept Appl Sci Naples Italy

ISBN: (数字)9783540723608

ISBN: (纸本)9783540723592

The discovery and selection of needed resources, taking into account optimization criteria, local policies, computing and storage availability, resource reservations, and grid dynamics, is a technological challenge in the emerging technology of grid computing. The Condor Project's ClassAd language is commonly adopted as a "lingua franca" for describing grid resources, but Condor itself does not make extensive use of Web Services. In contrast, the strongly service-oriented Globus Toolkit is implemented using the web services resource framework, and offers basic services for job submission, data replica and location, reliable file transfers and resource indexing, but does not provide a resource broker and matchmaking service. In this paper we describe the development of a Resource Broker Service based on the Web Services technology offered by the Globus Toolkit version 4 (GT4). We implement a fully configurable and customizable matchmaking algorithm within a framework that allows users to direct complex queries to the GT4 index service and thus discover any published resource. The matchmaking algorithm supports both the native simple query form and the Condor ClassAd notation. We achieve this flexibility via a matchmaking API java class framework implemented on the extensible GT4 index service, which maps queries over ClassAds in a customizable fashion. We show an example of the proposed grid application, namely an on demand weather and marine forecasting system. This system implements a Job How Scheduler and a Job Flow Description Language in order to access and exploit shared and distributed observations, model software, and 2D/3D graphical rendering resources. The system combines GT4 components and our Job Flow Scheduler and Resource Broker services to provide a fully grid-aware system.

关键词： Marine applications

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An object-oriented approach to deploying highly configurable Web interfaces for the ATLAS experiment 21

An object-oriented approach to deploying highly configurable...

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21st International conference on computing in High Energy and Nuclear Physics (CHEP)

作者： Lange, Bruno Maidantchik, Carmen Pommes, Kathy Pavani, Varlen Arosa, Breno Abreu, Igor Univ Fed Rio de Janeiro COPPE EE IF BR-21941 Rio De Janeiro Brazil CERN European Lab Particle Phys CH-1211 Geneva 23 Switzerland

The ATLAS Technical Coordination disposes of 17 Web systems to support its operation. These applications, whilst ranging from managing the process of publishing scientific papers to monitoring radiation levels in the equipment in the experimental cavern, are constantly prone to changes in requirements due to the collaborative nature of the experiment and its management. In this context, a Web framework is proposed to unify the generation of the supporting interfaces. FENCE assembles classes to build applications by making extensive use of JSON configuration files. It relies heavily on Glance, a technology that was set forth in 2003 to create an abstraction layer on top of the heterogeneous sources that store the technical coordination data. Once Glance maps out the database modeling, records can be referenced in the configuration files by wrapping unique identifiers around double enclosing brackets. The deployed content can be individually secured by attaching clearance attributes to their description thus ensuring that view/edit privileges are granted to eligible users only. The framework also provides tools for securely writing into a database. Fully HTML5-compliant multi-step forms can be generated from their JSON description to assure that the submitted data comply with a series of constraints. Input validation is carried out primarily on the server side but, following progressive enhancement guidelines, verification might also be performed on the client-side by enabling specific markup data attributes which are then handed over to the jQuery validation plug-in. User monitoring is accomplished by thoroughly logging user requests along with any POST data. Documentation is built from the source code using the phpDocumentor tool and made readily available for developers online. Fence, therefore, speeds up the implementation of Web interfaces and reduces the response time to requirement changes by minimizing maintenance overhead.

关键词： Fences

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Quality configurable Reduce-and-Rank for Energy Efficient Approximate computing

Quality Configurable Reduce-and-Rank for Energy Efficient Ap...

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conference on Design Automation Test in Europe (DATE)

作者： Raha, Arnab Venkataramani, Swagath Raghunathan, Vijay Raghunathan, Anand Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9783981537048

Approximate computing is an emerging design paradigm that exploits the intrinsic ability of applications to produce acceptable outputs even when their computations are executed approximately. In this work, we explore approximate computing for a key computation pattern, Reduce-and-Rank (RnR), which is prevalent in a wide range of workloads including video processing, recognition, search and data mining. An RnR kernel performs a reduction operation (e.g., distance computation, dot product, L1-norm) between an input vector and each of a set of reference vectors, and ranks the reduction outputs to select the top reference vectors for the current input. We propose two complementary approximation strategies for the RnR computation pattern. The first is interleaved reduction-and-ranking, wherein the vector reductions are decomposed into multiple partial reductions and interleaved with the rank computation. Leveraging this transformation, we propose the use of intermediate reduction results and ranks to identify future computations that are likely to have low impact on the output, and can hence be approximated. The second strategy, input similarity based approximation, exploits the spatial or temporal correlation of inputs (e.g., pixels of an image or frames of a video) to identify computations that are amenable to approximation. These strategies address a key challenge in approximate computing - identification of which computations to approximate - and may be used to drive any approximation mechanism such as computation skipping and precision scaling to realize performance or energy improvements. A second key challenge in approximate computing is that the extent to which computations can be approximated varies significantly from application to application, and across inputs for even a single application. Hence, quality configurability, or the ability to automatically modulate the degree of approximation at runtime is essential. To enable quality configurability in RnR kern

关键词： Digital storage

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AOSD 2005: 4th International conference on Aspect-Oriented Software Development - conference Proceedings

AOSD 2005: 4th International Conference on Aspect-Oriented S...

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AOSD 2005: 4th International conference on Aspect-Oriented Software Development

ISBN: (纸本)1595930434

The proceedings contain 19 papers. The topics discussed include: an analysis of modularity in aspect oriented design;an expressive aspect language for system applications with Arachne;empowering configurable QoS management in real-time systems;supporting autonomic computing functionality via dynamic operating system kernel aspects;towards just-in-time middleware architectures;adaptive programming in JasCo;towards a catalog of aspect-oriented refactorings;deriving refactorings for AspectJ;role-based refactoring of crosscutting concerns;weaving a social fabric into existing software;crosscutting techniques in program specification and analysis;and aspect language features for concern coverage profiling.

关键词： Software engineering

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