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Annual Hawaii International conference on System Sciences (HICSS)

作者： W. Mangione-Smith Electrical Engineering University of California Los Angeles USA

configurable computing is an area of active research that has sprung up over the last few years. By combining aspects of traditional computing, such as high performance microprocessor and commodity memory devices, with programmable hardware devices, configurable computing attempts to gain the benefits of both adaptive software and optimized hardware. Because the field is young it remains ill defined and often either misunderstood or misrepresented. Fortunately there currently exists a small number of applications which show significant improvement through the use of configurable computing technology, and have sparked much of the interest in the field. The article touches on some of the different types of configurable computing systems that have been either proposed or developed and consider applications that seem to be well suited to this approach, and discuss the open issues in tool design.

关键词： Hardware Adders Synthetic aperture radar Time sharing computer systems High performance computing Field programmable gate arrays Cryptography Target recognition Laser radar Microprocessors

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Energy Efficient Stream-based configurable Architecture for Embedded Platforms

Energy Efficient Stream-based Configurable Architecture for ...

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International conference on Embedded Computer Systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Pratas, Frederico Tomas, Pedro Trancoso, Pedro Sousa, Leonel Univ Tecn Lisboa INESC ID IST Lisbon Portugal Univ Cyprus Dept Comp Sci Nicosia Cyprus

ISBN: (纸本)9781467322973;9781467322966

Reconfigurable hardware can be used as an energy and performance efficient co-processing solution to accelerate certain types of applications. To facilitate the design of hardware accelerators we have proposed a methodology that adopts the stream-based computing model and the usage of Graphics Processing Units as prototyping platforms. In this paper we go a step further and propose a new modular architecture for low-power reconfigurable systems to easily map the stream-based algorithms. In particular, the architecture consists of a semi-programable accelerator set that can be adapted to the application needs in terms of functional units and number of streaming engines. The proposed embedded architecture mates the exibility of recon. gurable hardware with the advantages of stream computing for the strict needs of embedded recon. gurable devices. We show a possible organization for this architecture. Moreover, we provide a general case study to analyze the scalability of the proposed architecture in an Altera FPGA. Our experimental results show that a significant speed-up can be achieved compared to general purpose processors using low-power FPGA devices. Our preliminary estimates show that it is also possible to achieve energy savings of up to 118x.

关键词： reconfigurable hardware Building construction ARCHITECTURE configurability embedded platform hardware accelerator embedding Platform energy saving Energy efficiency Scalability Field programmable gate arrays LOW POWER

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A Case Study on Monitoring and Geolocation of Noise in Urban Environments Using the Internet of Things 17

A Case Study on Monitoring and Geolocation of Noise in Urban...

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2nd International conference on Internet of things, Data and Cloud computing (ICC)

作者： Alejandro Gomez, Jairo Talavera, Jesus Eduardo Tobon, Luis Alejandra Culman, Maria Quiroz, Luis A. Manuel Aranda, Juan Ernesto Garreta, Luis Pontificia Univ Javeriana Cali Valle Del Cauca Colombia Univ Autonoma Bucaramanga Bucaramanga Santander Colombia Pontificia Univ Javeriana Bogota Cundinamarca Colombia

ISBN: (纸本)9781450347747

This paper presents the development of a system to monitor and geo-reference noise in urban environments using the Internet-of-Oings (IoT). The system intends to help control agencies and citizens to monitor noise using smart devices and services available on the Cloud for data sharing. The system includes a mobile application that periodically captures the microphone's audio signal during a configurable time window, obtains the mobile's global position after each measurement using the built-in GPS, and assigns a timestamp from the operating system. Then, a Fast Fourier Transform is applied to recorded audio and the power spectrum in decibels is extracted. The resulting vector is sampled at specific frequencies to create a vector of audio features that can be used to assess noise pollution completely offline. If an Internet connection is available, a telemetry message is assembled and sent to an IoT Hub in Microsoft Azure Cloud containing a unique ID, a position stamp, a time stamp, and all audio features. The message is transferred to a Stream Analytics service, and from there it is sent to a Cloud SQL Database for permanent storage. The historical information collected and shared by different users can be examined online by any individual through a customized report developed in Microsoft Power BI.

关键词： Noise monitoring Mobile applications Internet of things Mobile crowd sensing

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Passive-Active Crosstalk Beyond Low-Frequency Breakdown in Mathematical-Physical Models of Liquid Crystal Phase Shifters at Low-Frequency applications

Passive-Active Crosstalk Beyond Low-Frequency Breakdown in M...

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International conference on Green Energy, computing and Intelligent technology 2024, GEn-CITy 2024

作者： Li, Jinfeng Li, Haorong Advanced Research Institute of Multidisciplinary Science Beijing Institute of Technology Beijing China School of Integrated Circuits and Electronics Beijing Institute of Technology Beijing China Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9781837242689

While most of the liquid crystal-based configurable and reconfigurable devices nowadays were designed to operate at the high-frequency microwave, millimetre-wave and optical wavelengths, there is a scarce of discussion on their feasibility at transmitting the low-frequency (LF) spectrum (low-data-rate but featuring lower attenuation and longer-range communication or detection). This work identifies a crosstalk vulnerability between the LF transmission signal and the LC-driving bias field for the first time. Furthermore, we comparatively quantify diverse line length requirements spanning the spectrum from 1 Hz to 100 GHz for the same LC coaxial phase shifters but fabricated by two different strategies, one with the conventional alignment agent-rubbing process (technically demanding, time-consuming, and costly), the other one featuring rubbing-free at the cost of a reduced tuning range of permittivity per unit length (i.e., requesting a larger physical size for 360ι shifting to feed a phased array antenna). © The Institution of Engineering & technology 2024.

关键词： Crosstalk

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embServe: Embedded Services for Constrained Devices 19

embServe: Embedded Services for Constrained Devices

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IEEE 19th International Workshop on Factory Communication Systems (WFCS)

作者： Oliveira, Joao Sousa, Filipe Almeida, Luis Fraunhofer Portugal AICOS Porto Portugal Univ Porto FEUP CISTER Porto Portugal

ISBN: (纸本)9781665464321

Implementing, managing and updating large-scale complex IoT applications is still a non-trivial challenge. Service Oriented Architectures (SOA) are increasingly used for this purpose, given their well-defined communication interfaces and configurable service-to-service links that ease the implementation of complex data flows. However, these architectures usually stop at the edge, not supporting far-edge resource-constrained devices. This paper proposes embServe, a new service-oriented framework that enables SOA on networks of constrained devices. It allows users to deploy services compiled independently of the base application and configure their connections using standard IoT protocols and data models. We compared a reference implementation against traditional approaches. Results show that embServe reduces resource overhead with a subtle impact on computing performance while improving application response time and uptime.

关键词： Internet of Things Constrained Devices Software-Oriented Architecture Edge computing Far-Edge

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Dynamic Power Control in a Hardware Neural Network with Error-configurable MAC Units 6

Dynamic Power Control in a Hardware Neural Network with Erro...

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6th Iranian International conference on Microelectronics, IICM 2024

作者： Ghaderi, Maedeh Delavari, Arvin Ghoreishy, Faraz Mirzakuchaki, Sattar School of Electrical Engineering Iran University of Science and Tech. Tehran Iran

ISBN: (纸本)9798331511371

Multi-Layer Perceptrons (MLP) are powerful tools for representing complex, non-linear relationships, making them essential for diverse machine learning and AI applications. Efficient hardware implementation of MLPs can be achieved through many hardware and architectural design techniques. These networks excel at predictive modeling and classification tasks like image classification, making them a popular choice. Approximate computing techniques are increasingly used to optimize critical path delay, area, power, and overall hardware efficiency in high-performance computing systems through controlled error and related trade-offs. This study proposes a hardware MLP neural network implemented in 45nm CMOS technology, in which MAC units of the neurons incorporate error and power controllable approximate multipliers for classification of the MNIST dataset. The optimized network consists of 10 neurons within the hidden layers, occupying 0.026mm2 of area, with 5.55mW at 100MHz frequency in accurate mode and 4.81mW in lowest accuracy mode. The experiments indicate that the proposed design achieves a maximum rate of 13.33% decrease overall and 24.78% in each neuron's power consumption with only a 0.92% decrease in accuracy in comparison with accurate circuit. © 2024 IEEE.

关键词： Power systems computer aided design

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Warp processors

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2006年第3期11卷 659-681页

作者： Lysecky, Roman Stitt, Greg Vahid, Frank Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA USA

We describe a new processing architecture, known as a warp processor, that utilizes a field-programmable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these improvements completely transparently and operates from a standard binary. A warp processor dynamically detects the binary's critical regions, reimplements those regions as a custom hardware circuit in the FPGA, and replaces the software region by a call to the new hardware implementation of that region. While not all benchmarks can be improved using warp processing, many can, and the improvements are dramatically better than those achievable by more traditional architecture improvements. The hardest part of warp processing is that of dynamically reimplementing code regions on an FPGA, requiring partitioning, decompilation, synthesis, placement, and routing tools, all having to execute with minimal computation time and data memory so as to coexist on chip with the main processor. We describe the results of developing our warp processor. We developed a custom FPGA fabric specifically designed to enable lean place and route tools, and we developed extremely fast and efficient versions of partitioning, decompilation, synthesis, technology mapping, placement, and routing. Warp processors achieve overall application speedups of 6.3X with energy savings of 66% across a set of embedded benchmark applications. We further show that our tools utilize acceptably small amounts of computation and memory which are far less than traditional tools. Our work illustrates the feasibility and potential of warp processing, and we can foresee the possibility of warp processing becoming a feature in a variety of computing domains, including desktop, server, and embedded applications.

关键词： design experimentation performance warp processors hardware/software partitioning FPGA configurable logic just-in-time (JIT) compilation dynamic optimization hardware/software codesign

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The configurable cloud - accelerating hyperscale datacenter services with FPGAs

The configurable cloud - accelerating hyperscale datacenter ...

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IEEE International conference on Field-Programmable technology (FPT)

作者： Andrew Putnam Microsoft Research Redmond WA US

ISBN: (纸本)9781509056033

Summary form only given. The Catapult project has brought the power and performance of FPGA-based reconfigurable computing to Microsoft's hyperscale datacenters, accelerating major production cloud applications such as Bing web search and Microsoft Azure, and enabling a new generation of machine learning and artificial intelligence applications. In this talk, I will describe the next generation of the Catapult configurable cloud architecture, show some of the applications have been accelerated by Catapult, and discuss the experiences and lessons learned while bringing up the first applications in the configurable cloud. I will also share stories of the evolution of Catapult - from its origins as a single development kit board through to the hyperscale deployment of hundreds of thousands of FPGAs across 15 countries and 5 continents - highlighting insights and experiences that transformed Catapult from a caffeine-fueled PowerPoint presentation into the largest deployment of reconfigurable computing in the world.

关键词： Horn antennas Dipole antennas Lenses Directive antennas Gallium arsenide Silicon

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On the Performance Effect of Loop Trace Window Size on Scheduling for configurable Coarse Grain Loop Accelerators 20

On the Performance Effect of Loop Trace Window Size on Sched...

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20th International conference on Field-Programmable technology (ICFPT)

作者： Santos, Tiago Paulino, Nuno Bispo, Joao Cardoso, Joao M. P. Ferreira, Joao C. Univ Porto INESC TEC Inst Engn Sistemas & Comp Tecnol & Cien Fac Engn Porto Portugal

ISBN: (纸本)9781665420105

By using Dynamic Binary Translation, instruction traces from pre-compiled applications can be offloaded, at runtime, to FPGA-based accelerators, such as Coarse-Grained Loop Accelerators, in a transparent way. However, scheduling onto coarse-grain accelerators is challenging, with two of current known issues being the density of computations that can be mapped, and the effects of memory accesses on performance. Using an in-house framework for analysis of instruction traces, we explore the effect of different window sizes when applying list scheduling, to map the window operations to a coarse-grain loop accelerator model that has been previously experimentally validated. For all window sizes, we vary the number of ALUs and memory ports available in the model, and comment how these parameters affect the resulting latency. For a set of benchmarks taken from the PolyBench suite, compiled for the 32-bit MicroBlaze softcore, we have achieved an average iteration speedup of 5.10x for a basic block repeated 5 times and scheduled with 8 ALUs and memory ports, and an average speedup of 5.46x when not considering resource constraints. We also identify which benchmarks contribute to the difference between these two speedups, and breakdown their limiting factors. Finally, we reflect on the impact memory dependencies have on scheduling.

关键词： Ports (computers) Schedules Runtime Reduced instruction set computing Limiting Processor scheduling Memory management

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MobileNetV2 Accelerator for Power and Speed Balanced Embedded applications 2

MobileNetV2 Accelerator for Power and Speed Balanced Embedde...

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2nd IEEE International conference on Data Science and Computer Application, ICDSCA 2022

作者： Xie, Xiaofei Zhao, Guodong Wei, Wei Huang, Wei College of Electronic and Information Engineering Inner Mongolia University Hohhot China

ISBN: (数字)9781665472005

ISBN: (纸本)9781665472005

With the development of AI technology, image classification or recognition by Convolutional Neural Networks (CNN) can achieve higher accuracy than traditional image processing algorithms, and even exceed human-level classification performance. However, in order to obtain higher model accuracy, larger and deeper network structures need to be introduced, and the computational cost and memory requirements increase with the model size and number of parameters, which make them difficult to deploy in resource-constrained embedded devices. This paper optimizes the lightweight neural network model MobileNetV2, and designs an accelerator inference architecture that is configurable, low-power, and low-resource by combining the idea of software and hardware co-design. The architecture is based on the Zynq-7020 SOC FPGA heterogeneous platform and uses four configurable hardware computing engines for inference. At a frequency of 100 MHz, the processing speed reaches 16 FPS. In addition, it reaches 86.03% verification accuracy rate on the CIFAR-10 dataset. The overall power consumption of the system is 2.741 W, and the logic and algorithm resources occupied are also lower than other MobileNetV2 hardware accelerators. Since the basic structure of MobileNetV2 can also be used to build higher performance networks, the research in this paper is still applicable when higher prediction accuracy is required. © 2022 IEEE.

关键词： Field programmable gate arrays (FPGA)

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