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检索条件"任意字段=Conference on Configurable Computing - Technology and Applications"

共 333 条记录，以下是11-20 订阅

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Comparing computing machines

Comparing computing machines

引用

conference on configurable computing - technology and applications

作者： DeHon, A Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)0819429872

Reconfigurable computing devices are emerging as a viable alternative to fixed-function components and programmable processors. To expand our knowledge of the role and optimization of these devices, it is increasingly imperative for us to compare implementations of tasks and subroutines across this wide spectrum of implementation options. The fact Chat most processors, FPGAs, ASICs, and memories are fabricated in a uniform technology medium, CMOS VLSI, where area scaling is moderately well understood eases our comparison task. Nonetheless, the rapid pace of technology, limited device size selection, and economic artifacts complicate the picture. In this paper, we look at the task of comparing computing machines, reviewing normalization techniques and many important issues which arise during comparisons. This paper includes examples intended to underscore the methodology and comparison issues, but does not attempt to make definitive conclusions about the merits of the technology alternatives from the small sample set. The immediate intent of this work is to help designers faced with tradeoffs between technological alternatives. The longer term intent is to help the community collect and analyze the broad-based data. needed to Better understand the range of available computing options.

关键词： configurable computing FPGA programmable architectures performance comparison computational density

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Computer vision application on RIPP10 configurable platform using DIPSA modular architecture

Computer vision application on RIPP10 configurable platform ...

引用

conference on configurable computing - technology and applications

作者： Benitez, D Univ Las Palmas GC Dpto Informat & Sistemas Las Palmas Gran Canaria 35017 Spain

ISBN: (纸本)0819429872

Many vision tasks have stringent latency, throughput requirements, and real-time processing demand for greater parallelism. This paper describes a real-time Computer-Vision application that has been developed on a reconfigurable platform called RIPP10 from Altera. We use our simple, modular, reconfigurable and parallel specialized architecture called DIPSA. We analyze and quantify performance requirements demanded by an Automatic Target Recognition and Tracking algorithm and then propose a partitioning of the algorithm into DIPSA modules to achieve frame rate processing. Results of this implementation are used for addressing some issues that benefit and limit configurable computing systems.

关键词： computer architecture FPGA/CPLD real-time imaging computer vision

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Whither configurable computing?

Whither configurable computing?

引用

30th Hawaii International conference on System Sciences (HICSS 30)

作者： Ebeling, C Univ Washington Dept Comp Engn & Sci Seattle WA 98195 USA

ISBN: (纸本)0818677430

configurable computing has captured the imagination of many architects who want the performance of application-specific hardware combined with the flexibility of general-purpose computers. Despite the efforts of many research groups over the past decade, successes have been rare because the configurable computers, so far, exhibit poor cost performance for most applications. And they are also notoriously hard to program. Future progress in configurable computers will result not from continued research along the same field programmable gate array-based path, but from a diversity of approaches including more coarse-grained configurable architectures and constrained programming models that allow more powerful compilation techniques.

关键词： Computer architecture

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UNIX-Like Operating System Extension for Real-Time FPGA-Based SCCS Support 9

UNIX-Like Operating System Extension for Real-Time FPGA-Base...

引用

9th IEEE International conference on Intelligent Data Acquisition and Advanced computing Systems - technology and applications (IDAACS)

作者： Melnyk, Anatoliy Melnyk, Viktor Kit, Andriy John Paul II Catholic Univ Lublin Ul Konstantynow 1H P 313 PL-20708 Lublin Poland Lviv Polytech Natl Univ Bandery Str 12 UA-79013 Lvov Ukraine Ostware Serv Ltd Naukova Str 7b-801-802 UA-79060 Lvov Ukraine

ISBN: (纸本)9781538606971

The questions of further implementation of the operating system software means for the real-time FPGA-based self-configurable computer systems support will be discussed in the paper. These computer systems compete with other types of high-performance computer systems due to high speed characteristics of modern field-programmable gate arrays (FPGAs) - hardware base of reconfigurable computing environment (RCE), and due to advances in design technology of application-specific processors to be synthesized in RCE. Moreover, in the self-configurable computer systems (SCCS) the labor-intensive and time-consuming works of tasks distribution between the processing units and development of the IP cores required for implementation in the RCE, are fully automated and replaced from the operator to the computer system. Taking into account the necessity of further improvement of computer means performance and expansion of reconfigurable devices application in the Cloud computing and Cyber-Physical Systems (CPS), further development in the field of self-configurable computer systems is a topical challenge of scientific research and engineering.

关键词： self-configurable computer system operating system reconfigurable computing cloud computing cyber-physical system

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Rapid implementation of mathematical and DSP algorithms in configurable computing devices

Rapid implementation of mathematical and DSP algorithms in c...

引用

conference on configurable computing - technology and applications

作者： Fiore, PD Myers, CS Smith, JM Pauer, EK Lockheed Martin Co Sanders Nashua NH USA

ISBN: (纸本)0819429872

Many real-time DSP applications can benefit from the use of FPGA or adaptive computing devices because these devices provide very high throughput for a small hardware cost. This efficiency comes with a price: it is very time consuming to actually program complicated algorithms in these devices. We have developed a new method of performing this implementation process, providing for an order of magnitude reduction in design time. Our approach consists of an interactive algorithm development tool closely coupled to a set of FPGA devices. From an algorithm script, the tool derives a hardware design, which includes the data path, host interlace, custom sequencer, and address generators. The design is loaded and executed in the FPGA whenever a call far the function is encountered in the algorithm script. Pieces of the algorithm may he ported incrementally;the algorithm will always execute properly, regardless of the state of porting from software to hardware. This approach is optimized to allow mathematicians, generally unskilled in efficient hardware algorithm design. to directly implement algorithms in FPGAs. This enables designers to quickly sec the effect of algorithmic changes and approximations on hardware efficiency, reducing the number and time of design iterations. We are currently porting our approach to the publicly available Ptolemy environment, which will facilitate the transfer of this methodology to the adaptive computing community.

关键词： FPGA DSP adaptive computing configurable computing rapid development Ptolemy

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Design, debug, deploy: The creation of configurable computing applications

Design, debug, deploy: The creation of configurable computin...

引用

17th IEEE International conference on Application-Specific Systems, Architectures and Processors

作者： Nelson, Brent E. Hutchings, Brad L. Wirthlin, Michael J. Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA

configurable computing Machines (CCMs) are computing machines based on reconfigurable circuit technology such as field programmable gate-arrays. Early researchers recognized CCMs as a new, flexible, and powerful class of computer. The earliest CCMs featured rudimentary but significant integrated design, debug, and deployment (runtime) environments. This paper reviews those environments and the contributions they made and considers the progress made over the past 20 years in providing support for the "3 D's" of configurable computing application development: design, debug, and deployment. It then introduces an integrated CAD framework for the creation of CCM CAD tools and describes a series of experiments in creating such a CAD tool suite - the JHDL system. The paper reviews lessons learned from that work and concludes by discussing the role integrated design, debug, and runtime environments will play in future CCM-based systems.

关键词： configurable computing FPGA CAD for configurable computing design environments

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Hardware/software codesign of a Fuzzy ART neural clusterer: the benefits of configurable computing

Hardware/software codesign of a Fuzzy ART neural clusterer: ...

引用

conference on configurable computing - technology and applications

作者： Poire, P Savaria, Y Daniel, W Cantin, MA Blaquiere, Y Ecole Polytech Dept Elect & Comp Engn Montreal PQ H3C 3A7 Canada

ISBN: (纸本)0819429872

This paper analyzes the performance differences found between software and hardware/sofware implementations of a reformulated Fuzzy ART neural network algorithm. This reformulated algorithm is a solution for a real time radar signal clustering problem. The software implementations run on a 50MHz TMS320C40 DSP, and the hardware/sofware implementation runs on the same DSP for its software part, whereas the FPGA based application specific hardware accelerator is realized on the MiroTech's X-CIM TIM40 module. This investigation of FPGA based acceleration gave excellent re suits for our application: acceleration factors up to 68.9 have been reached.

关键词： neural network clusterer fuzzy ART codesign FPGA

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An Ultra Low Power, configurable Intelligent Biasing Calibration for Medical Sensor applications in 130 nm CMOS technology

An Ultra Low Power, Configurable Intelligent Biasing Calibra...

引用

IEEE International conference on Big Data and Smart computing (BigComp)

作者： Ali, Imran Yingge, Huo Asif, Muhammad Lee, Kang-Yoon Sungkyunkwan Univ Dept Elect & Comp Engn Suwon South Korea

ISBN: (纸本)9781728160344

In this paper, a configurable intelligent biasing calibration methodology is presented for medical sensor applications. The proposed biasing calibration algorithm is applicable for single as well as an array of nanopore sensors in a medical device. This technique compensates the variation among different nanopore sensors by calibrating the gate biasing voltages and improves accuracy and enhances reliability. It also identifies the faulty nanopore sensors. The presented biasing calibration controller is fully synthesizable and it needs only 1.184 K gates for its implementation. It draws only 76.3 nA current from 1.2 V supply its power consumption is only 91.56 nW. The proposed intelligent biasing calibration controller is integrated into a medical sensing system and it is implemented in a 130 nm CMOS process.

关键词： Nanopore calibration digital controller CMOS analog front end

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Framework for architecture-independent run-time reconfigurable applications

Framework for architecture-independent run-time reconfigurab...

引用

conference on Reconfigurable technology: FPGAs for computing and applications II

作者： Lehn, DI Hudson, RD Athanas, PM Virginia Tech Bradley Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)0819438774

configurable computing Machines (CCMs) have emerged as a technology with the computational benefits of custom ASICs as well as the flexibility and reconfigurability of general-purpose microprocessors. Significant effort from the research community has focused on techniques to move this reconfigurability from a rapid application development tool to a run-time tool. This requires the ability to change the hardware design while the application is executing and is known as Run-Time Reconfiguration (RTR). Widespread acceptance of run-time reconfigurable custom computing depends upon the existence of high-level automated design tools. Such tools must reduce the designers effort to port applications between different platforms as the architecture, hardware, and software evolves. A Java implementation of a high-level application framework, called Janus, is presented here. In this environment, developers create Java classes that describe the structural behavior of an application. The framework allows hardware and software modules to be freely mixed and interchanged. A compilation phase of the development process analyzes the structure of the application and adapts it to the target platform. Janus is capable of structuring the run-time behavior of an application to take advantage of the memory and computational resources available.

关键词： RTR run-time reconfiguration CCM configurable computing FPGA automated design

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Using the KressArray for reconfigurable computing

Using the KressArray for reconfigurable computing

引用

conference on configurable computing - technology and applications

作者： Hartenstein, R Herz, M Hoffmann, T Nageldinger, U Univ Kaiserslautern D-67663 Kaiserslautern Germany

ISBN: (纸本)0819429872

Multimedia applications commonly require high computation power mostly in conjunction with high data throughput. As an additional challenge, such applications are increasingly used in handheld devices, where also small package outlines and low power aspects are important. Many research approaches have shown, that accelerators based on reconfigurable hardware can satisfy those performance demands. Most of these approaches use commercial fine-grained FPGAs to implement reconfigurable accelerators. However, it has shown, that these devices are not always well suited for reconfigurable computing. The drawbacks here are the area-inefficiency and the insufficiency of the available design-tools. Besides the fine-grained FPGAs, coarse-grained reconfigurable architectures have been developed, which are more area efficient and better suited for computational purposes. In this paper, an implementation of such an architecture, the KressArray, is introduced and its use in the Map-oriented Machine with Parallel Data Access (MoM-PDA) is shown. The MoM-PDA is an FPGA-based custom computing machine, which is able to perform concurrent memory accesses by means of a dedicated memory organization scheme. The benefits of this architecture are illustrated by an application example.

关键词： reconfigurable computing parallel data access coarse grained reconfigurable architectures KressArray accelerators Xputer image processing

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