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Generating Business Events in an RFID network

Generating Business Events in an RFID network

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2011 2nd IEEE RFID Technologies and applications conference, RFID-TA 2011, Collocated with the 2011 IEEE MTT-S International Microwave Workshop Series on Millimeter Wave Integration Technologies, IMWS 2011

作者： Kefalakis, Nikos Soldatos, John Mertikas, Efstathios Prasad, Neeli R. Aalborg University Aalborg Denmark Autonomic and Grid Computing Athens Information Technology Peania Greece

ISBN: (纸本)9781457700279

Radio Frequency Identification (RFID) has been promoted, as the solution to the identification and tracking of objects, without any means of wires or human intervention. RFID middleware is a prominent component of any non-trivial RFID deployment. EPCglobal has been actively working towards a set of middleware standards for large scale interoperable RFID deployments (such as the Electronic Product Code Application Level Events (EPC-ALE) and Information Sharing (EPCIS) standards), while several middleware projects have concentrated in the implementation of these standards. However, there is still a clear need for middleware modules that map low-level tag streams (e.g., stemming from EPC-ALE modules) to Business Events (e.g., events formulated according to the EPCIS standard). In this paper, we introduce a middleware module for bridging EPC-ALE reports with EPCIS repositories based on automated generation of business events subject to Master Data and context pertaining to a particular business case. We call the respective middleware module Business Event Generator (BEG). BEG is a configurable engine that can automatically create business events from a set of low-level tag streams. In addition to the BEG module, we introduce tools and techniques for configuring the BEG engine. We illustrate the use of the above middleware and tools based on a set of indicative use cases in the area of logistics and supply chain management. © 2011 IEEE.

关键词： Supply chain management

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5th International conference on Parallel Processing and Applied Mathematics, PPAM 2003

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5th International conference on Parallel Processing and Applied Mathematics, PPAM 2003

ISBN: (纸本)3540219463

The proceedings contain 149 papers. The special focus in this conference is on Parallel, Distributed Architectures, Scheduling and Load Balancing. The topics include: Session guarantees to achieve pram consistency of replicated shared objects;an extended atomic consistency protocol for recoverable DSM systems;hyper-threading technology speeds clusters;configurable microprocessor array for DSP applications;on generalized moore digraphs;RDMA communication based on rotating buffers for efficient parallel fine-grain computations;communication on the fly in dynamic SMP clusters;accelerated diffusion algorithms on general dynamic networks;suitability of load scheduling algorithms to workload characteristics;minimizing time-dependent total completion time on parallel identical machines;diffusion based scheduling in the agent-oriented computing system;approximation algorithms for scheduling jobs with chain precedence constraints;combining vector quantization and ant-colony algorithm for mesh-partitioning;wavelet-neuronal resource load prediction for multiprocessor environment;fault-tolerant scheduling in distributed real-time systems;online scheduling of multiprocessor jobs with idle regulation;predicting the response time of a new task on a beowulf cluster;space decomposition solvers and their performance in pc-based parallel computing environments;evaluation of execution time of mathematical library functions based on historical performance information;empirical modelling of parallel linear algebra routines;efficiency of divisible load processing;gray box based data access time estimation for tertiary storage in grid environment;performance modeling of parallel fem computations on clusters;asymptotical behaviour of the communication complexity of one parallel algorithm and analytical modeling of optimized sparse linear code.

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FPGA Performance Optimization Plan for High Power Conversion 1

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2nd International conference on Soft computing Systems (ICSCS)

作者： Muthukumar, P. Kanthan, Padma Suresh Lekshmi Immanuel, T. Baldwin Eswaramoorthy, K. PVP Siddhartha Inst Technol Dept Elect & Elect Engn Vijayawada 520007 India Baselios Mathew II Coll Engn Dept Elect & Elect Engn Sasthamkotta 690521 Kerala India AMET Deemed Univ Dept Elect & Elect Engn Chennai 603112 Tamil Nadu India Anna Univ Dept Elect & Elect Engn Chennai 600025 Tamil Nadu India

ISBN: (数字)9789811319365

ISBN: (纸本)9789811319365;9789811319358

One of the major part of any power converter system is a blistering implementation of PWM algorithm for high power conversion. It must fulfil both requirements of power converter hardware topology and computing power necessary for control algorithm implementation. The emergence of multi-million-gate FPGAs with large on-chip RAMs and a processor cores sets a new trend in the design of FPGAs which are exceedingly used to generate the PWM in the area of power electronics. Of late, more and more large complex designs are getting realized using FPGAs, because of less NRE cost and shorter development time. The share of Programmable Logic Devices (PLD), especially FPGAs, in the semiconductor logic market is tremendously growing year-on-year. This calls for an increased controllability of designs, in terms of meeting both area and timing performance, to really derive the perceived benefits. The recent strides in FPGA technology favour the realization of large high-speed designs, which were only possible in an ASIC, in FPGA now. However the routing delay being still unpredictable and the pronounced nature of routing delay over logic delay, in today's FPGAs impedes the goal of early timing convergence. This paper introduces the few techniques for controlling the design area/ time right from architecture stage and the technique can adopt for any FPGA based design applications including the high power conversion. This paper also describes the trade off between Area, speed and power of the optimization techniques.

关键词： Field Programmable Gate Array Programmable Logic Devices Application specific integrated circuits Flip flops Optimization Register transfer logic Block ram Embedded array block configurable logic blocks

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ILI: an adaptive infrastructure for dynamic interactive distributed applications

ILI: an adaptive infrastructure for dynamic interactive dist...

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Proceedings of International Workshop on configurable Distributed Systems

作者： V. Martin K. Schwan College of Computing Georgia Institute of Technology Atlanta GA USA

Addresses the middleware that is necessary to realize the construction of distributed laboratories in which scientists can construct and use complex computations and then analyze and share their results across geographically separated collaborations. We present a model of such middleware for heterogeneous distributed computing platforms and also show how middleware can dynamically adapt to changes in the behavior of instruments and end users. To address the demands of applications executing in a distributed laboratory, we have developed an infrastructure, called ILI (Interactivity Layer Infrastructure), that can dynamically adapt to changes in the behavior of the computational instruments and end users across a shared and dynamically changing set of computational nodes and networks.

关键词： Laboratories Instruments Microwave integrated circuits Computer networks Atmospheric modeling Engines Educational institutions Postal services Electronic switching systems Reactive power

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StressBench: A configurable Full System Network and I/O Benchmark Framework

StressBench: A Configurable Full System Network and I/O Benc...

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2021 IEEE High Performance Extreme computing conference, HPEC 2021

作者： Chester, Dean G. Groves, Taylor Hammond, Simond D. Law, Tim Wright, Steven A. Smedley-Stevenson, Richard Fahmy, Suhaib A. Mudalidge, Gihan R. Jarvis, Stephen A. University of Warwick Department of Computer Science Coventry United Kingdom Advanced Technologies Group NERSC Berkeley United States Sandia National Laboratories Albuquerque United States AWE PLC Aldermastion United Kingdom University of York York United Kingdom School of Engineering University of Warwick Coventry United Kingdom University of Birmingham Birmingham United Kingdom

ISBN: (纸本)9781665423694

We present StressBench, a network benchmarking framework written for testing MPI operations and file I/O concurrently. It is designed specifically to execute MPI communication and file access patterns that are representative of real-world scientific applications. Existing tools consider either the worst case congestion with small abstract patterns or peak performance with simplistic patterns. StressBench allows for a richer study of congestion by allowing orchestration of network load scenarios that are representative of those typically seen at HPC centres, something that is difficult to achieve with existing tools. We demonstrate the versatility of the framework from micro benchmarks through to finely controlled congested runs across a cluster. Validation of the results using four proxy application communication schemes within StressBench against parent applications shows a maximum difference of 15%. Using the I/O modeling capabilities of StressBench, we are able to quantify the impact of file I/O on application traffic showing how it can be used in procurement and performance studies. © 2021 IEEE.

关键词： Benchmarking

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A configurable FPGA Implementation of PEG-based PS-LDPC Decoder

A Configurable FPGA Implementation of PEG-based PS-LDPC Deco...

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International conference on Pervasive computing Signal Processing and applications (PCSPA)

作者： Kun Wang Ning-qing Liu Bin Sun Hao-wei Sun Communication Research Center Harbin Institute of Technology Harbin China School of Mechanical Science and Engineering Daqing Petroleum Institute Daqing China

Low-density parity-check (LDPC) codes form an important subclass of error correcting coding techniques, and its implementation has been hot spot of domains such as signal process, magnetic recording or next generation communication for years. This paper proposes a configurable FPGA implementation of Partition-and-Shift LDPC decoder based on Min-Sum algorithm. An MPEG algorithm is introduced to reduce the complexity of searching for closed paths in shift matrix. And a routing paths switch concept is proposed to realize the expected configurability. Benefits of the proposed technique are demonstrated with FPGA design for differently configured PS-LDPC decoders which all achieve a Gbps throughput, low hardware cost and excellent BER performance at 16 iterations.

关键词： Decoding Parity check codes Algorithm design and analysis Throughput Niobium Routing Hardware

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An Intuitive Extensible Framework for Implementing Cloud Broker Architectures 2nd

An Intuitive Extensible Framework for Implementing Cloud Bro...

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2nd International conference on Emerging Trends and Advances in Electrical Engineering and Renewable Energy, ETAEERE 2020

作者： Ponraj, Anitha Jaswanth, D.C. Praneeth, D. Roobini, M.S. Marry Valantina, G. School of Computing Sathyabama Institute of Science and Technology Chennai India

ISBN: (纸本)9789811587511

Cloud computing is broadly received gratitude to the high business spryness;it assurances to its shoppers. Cloud administrations arrangement in the commercial center is an essential undertaking for both cloud customer and cloud supplier principally if the cloud buyer asks explicit properties for its applications. In this manner, this undertaking is designated to a third part which is the cloud intermediary. The proposed framework a cloud asset dealer is suggested that will administer the task of suppliers’ assets to purchaser progressively. The proposed representative uses different prerequisites and imperatives determined by the shopper in the necessity depiction format as contribution, to figure amassed necessities, utilizing an accumulation calculation. Further, the administration planning calculation is characterized to discover a streamlined match between the accumulated necessities with the suppliers contributions. From that point, this calculation is executed regularly, in view of a procedure for dynamic planning to profit customers by virtue of presentation of new supplier or some great contributions. Results demonstrate that the arrangement gave by agent ends up being a success win circumstance for the customer concerning cost just as execution. We propose a monetarily roused pay way to deal with increment the granularity and utility of saved calculation and capacity administrations. The result is a profoundly virtualization of cloud asset intermediary. It comprises of a guardian asset administration commercial center and a shopper configurable virtual machine for asset sharing. The framework bolsters progressively settled virtualization with powerfully customizable asset limits for fine-grained auxiliary, worldly, and vertical–spatial versatility. © 2021, Springer Nature Singapore Pte Ltd.

关键词： Cloud computing

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The Smart Workflow Analysis Framework For Channel Allocation In Ultra Dense Cloud computing

The Smart Workflow Analysis Framework For Channel Allocation...

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Innovation in technology (INOCON), IEEE International conference for

作者： J Angelin Blessy Dileep Kumar Kushwaha Department of Computer Applications Galgotias University Greater Noida Uttar Pradesh India Department of Informationm Technology Noida Institute of Engineering and Technology Greater Noida Uttar Pradesh India

Cloud computing is a type of computing that relies on sharing computing resources rather than having local servers or personal devices to handle applications. Cloud computing is a model for enabling ubiquitous, convenient, on-demand network access to a shared pool of configurable computing resources that can be rapidly provisioned and released with minimal management effort or service provider interaction. In cloud computing, resources such as networks, servers, services, and applications are all provided over the Internet. In this paper, a smart workflow analysis framework has proposed for channel allocation in ultra dense cloud computing. The Smart Workflow Analysis Framework for Channel Allocation in Ultra Dense Cloud computing is a highly advanced system to optimize wireless resource allocation. It employs a combination of cognitive radio networks, graph convolutional networks, reinforcement learning approaches and neural networks to allocate channels in an optimal way. By using deep reinforcement learning, the framework is able to make decisions based on real-time edge network data.

关键词： Cloud computing Technological innovation Organizations Reinforcement learning Computer architecture Channel allocation Real-time systems

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A configurable context-aware simulator for smart home systems

A configurable context-aware simulator for smart home system...

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International conference on Pervasive computing and applications (ICPCA)

作者： Qiang Fu Ping Li Cai Chen Lanlan Qi Yongqiang Lu Chen Yu Beijing University of Technology Beijing P.R.China South Lishilu Clinic of PLA Second Artillery Beijing P.R. China

ISBN: (纸本)9781457702099

The development of distributed smart homes is accelerating with the approach of the Pervasive computing era. Heterogeneous devices and network is a significant feature in these smart homes. However, the realization of a real environment is difficult and always takes a long time. It is unrealistic to verify the availability of the entire system and make sure that all devices and applications can work together after finishing the development. In this paper we present a configurable context-aware simulator for distributed smart homes. XML configuration files are used to save information for constructing the home environment, virtual devices and services, simulating context information and testing the OSGi event interaction between devices. This makes the simulator can work under different smart home environment which based on the OSGi framework without modifying any code. And the simulated virtual devices can work with real devices with the help of the simulator. It is easier to provide a complete simulation environment for a device to test and verify during the development process.

关键词： Context Context modeling XML TV Atmospheric modeling Context-aware services Humans

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ABIDES: Towards High-Fidelity Multi-Agent Market Simulation 20

ABIDES: Towards High-Fidelity Multi-Agent Market Simulation

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2020 ACM SIGSIM conference on Principles of Advanced Discrete Simulation, SIGSIM-PADS 2020

作者： Byrd, David Hybinette, Maria Balch, Tucker Hybinette School of Interactive Computing Georgia Institute of Technology Atlanta United States Department of Computer Science University of Georgia Athens United States J.P. Morgan AI Research New York United States

ISBN: (纸本)9781450375924

We introduce ABIDES, an open source Agent-Based Interactive Discrete Event Simulation environment. ABIDES is designed from the ground up to support agent-based research in market applications. While proprietary simulations are available within trading firms, there are no broadly available high-fidelity market simulation environments. ABIDES enables the simulation of tens of thousands of trading agents interacting with an exchange agent to facilitate transactions. It supports configurable pairwise noisy network latency between each individual agent as well as the exchange. Our simulator's message-based design is modeled after NASDAQ's published equity trading protocols ITCH and OUCH. We introduce the design of the simulator and illustrate its use and configuration with sample code, validating the environment with example trading scenarios. The utility of ABIDES for financial research is illustrated through experiments to develop a market impact model. The core of ABIDES is a general-purpose discrete event simulation, and we demonstrate its breadth of application with a non-finance work-in-progress simulating secure multiparty federated learning. We close with discussion of additional experimental problems it can be, or is being, used to explore, such as the development of machine learning trading algorithms. We hope that the availability of such a platform will facilitate research in this important area. © 2020 Association for computing Machinery.

关键词： Discrete event simulation

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