检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

329 篇 会议
4 篇 期刊文献

馆藏范围

333 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

199 篇 工学
- 169 篇 计算机科学与技术...
- 94 篇 软件工程
- 42 篇 电气工程
- 36 篇 信息与通信工程
- 22 篇 电子科学与技术（可...
- 18 篇 控制科学与工程
- 12 篇 生物工程
- 6 篇 机械工程
- 6 篇 动力工程及工程热...
- 6 篇 网络空间安全
- 5 篇 仪器科学与技术
- 5 篇 建筑学
- 3 篇 土木工程
- 3 篇 生物医学工程（可授...
- 2 篇 力学（可授工学、理...
- 2 篇 光学工程
- 2 篇 材料科学与工程（可...
- 2 篇 交通运输工程
39 篇 理学
- 18 篇 数学
- 12 篇 物理学
- 12 篇 生物学
- 4 篇 系统科学
- 2 篇 统计学（可授理学、...
23 篇 管理学
- 14 篇 管理科学与工程(可...
- 10 篇 图书情报与档案管...
- 5 篇 工商管理
5 篇 医学
- 4 篇 临床医学
4 篇 教育学
- 4 篇 教育学
3 篇 经济学
- 3 篇 应用经济学
3 篇 法学
- 3 篇 社会学
1 篇 文学
1 篇 艺术学

主题

47 篇 cloud computing
35 篇 computer archite...
22 篇 hardware
16 篇 field programmab...
13 篇 fpga
13 篇 energy efficienc...
12 篇 application soft...
11 篇 computational mo...
11 篇 distributed comp...
10 篇 internet of thin...
10 篇 protocols
9 篇 image processing
9 篇 computer network...
8 篇 runtime
8 篇 reduced instruct...
8 篇 servers
8 篇 security
7 篇 configurable com...
7 篇 throughput
7 篇 energy consumpti...

机构

5 篇 university of ch...
3 篇 college of compu...
3 篇 institute of com...
2 篇 computing depart...
2 篇 centre for asses...
2 篇 department of cs...
2 篇 tsinghua univers...
2 篇 brigham young un...
2 篇 school of comput...
2 篇 school of electr...
2 篇 university of el...
2 篇 university of ce...
2 篇 univ aveiro dept...
2 篇 university insti...
2 篇 center for excel...
2 篇 semiconductor ne...
2 篇 univ bologna arc...
2 篇 nanjing houmo ai...
2 篇 department of in...
2 篇 college of compu...

作者

5 篇 k. schwan
2 篇 martonosi m
2 篇 g.s. blair
2 篇 cappelli a
2 篇 guerrieri r
2 篇 lodi a
2 篇 hutchings brad l...
2 篇 canegallo r
2 篇 toma m
2 篇 sklyarov valery
2 篇 wirthlin michael...
2 篇 xiaowei li
2 篇 nelson brent e.
2 篇 hudson rd
2 篇 xiaohui wei
2 篇 peter athanas
2 篇 campi f
1 篇 akbari omid
1 篇 asif muhammad
1 篇 itisha nowrin

语言

328 篇 英文
3 篇 其他
1 篇 土耳其文
1 篇 中文

检索条件"任意字段=Conference on Configurable Computing - Technology and Applications"

共 333 条记录，以下是251-260 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip

Metawire: Using FPGA configuration circuitry to emulate a Ne...

引用

International conference on Field Programmable Logic and applications

作者： M. Shelburne C. Patterson P. Athanas M. Jones B. Martin R. Fong Bradley Department of Electrical & Computer Engineering Configurable Computing Laboratory Virginia Technology Blacksburg VA USA

ISBN: (纸本)9781424419606

While there have been many reported implementations of networks-on-chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on an FPGA is already costly due to the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. There is, however, already a largely unused, global network available in FPGAs. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port (ICAP) and is shown to provide a bandwidth exceeding 200 MBytes/sec.

关键词： Field programmable gate arrays Magnetic cores Throughput Bandwidth Random access memory Routing Wires

来源：评论

学校读者我要写书评

暂无评论

The architecture and development flow of the S5 software configurable processor

The architecture and development flow of the S5 software con...

引用

4th IEEE International conference on Field Programmable technology

作者： Arnold, Jeffrey M. Stretch Inc Sunnyvale CA USA

A software configurable processor (SCP) is a hybrid device that couples a conventional processor datapath with programmable logic to allow application programs to dynamically customize the instruction set. SCP architectures can offer significant performance gains by exploiting data parallelism, operator specialization and deep pipelines. The S5000 is a family of high performance software configurable processors for embedded applications. The S5000 consists of a conventional 32-bit RISC processor coupled with a programmable Instruction Set Extension Fabric (ISEF). To develop an application for the S5 the programmer identifies critical sections to be accelerated, writes one or more extension instructions as functions in a variant of the C programming language, and accesses those functions from the application program. Performance gains of more than an order of magnitude over the unaccelerated processor can be achieved.

关键词： reconfigurable architectures software configurable processor instruction set extension embedded computing

来源：评论

学校读者我要写书评

暂无评论

Development of a GT4-Based resource broker service: An application to on-demand weather and marine forecasting 1

引用

2nd International conference on Grid and Pervasive computing

作者： Montella, R. Univ Naples Parthenope Dept Appl Sci Naples Italy

ISBN: (数字)9783540723608

ISBN: (纸本)9783540723592

The discovery and selection of needed resources, taking into account optimization criteria, local policies, computing and storage availability, resource reservations, and grid dynamics, is a technological challenge in the emerging technology of grid computing. The Condor Project's ClassAd language is commonly adopted as a "lingua franca" for describing grid resources, but Condor itself does not make extensive use of Web Services. In contrast, the strongly service-oriented Globus Toolkit is implemented using the web services resource framework, and offers basic services for job submission, data replica and location, reliable file transfers and resource indexing, but does not provide a resource broker and matchmaking service. In this paper we describe the development of a Resource Broker Service based on the Web Services technology offered by the Globus Toolkit version 4 (GT4). We implement a fully configurable and customizable matchmaking algorithm within a framework that allows users to direct complex queries to the GT4 index service and thus discover any published resource. The matchmaking algorithm supports both the native simple query form and the Condor ClassAd notation. We achieve this flexibility via a matchmaking API java class framework implemented on the extensible GT4 index service, which maps queries over ClassAds in a customizable fashion. We show an example of the proposed grid application, namely an on demand weather and marine forecasting system. This system implements a Job How Scheduler and a Job Flow Description Language in order to access and exploit shared and distributed observations, model software, and 2D/3D graphical rendering resources. The system combines GT4 components and our Job Flow Scheduler and Resource Broker services to provide a fully grid-aware system.

关键词： Marine applications

来源：评论

学校读者我要写书评

暂无评论

Effective memory protection using dynamic tainting

Effective memory protection using dynamic tainting

引用

22nd IEEE/ACM International conference on Automated Software Engineering, ASE'07

作者： Clause, James Doudalis, Ioannis Orso, Alessandro Prvulovic, Milos College of Computing Georgia Institute of Technology United States

ISBN: (纸本)9781595938824

Programs written in languages that provide direct access tomemory through pointers often contain memory-related faults, which may cause non-deterministic failures and even security vulnerabilities. In this paper, we present a new technique based on dynamic tainting for protecting programs from illegal memory accesses. When memory is allocated, at runtime, our technique taints both the memory and the corresponding pointer using the same taint mark. Taint marks are then suitably propagated while the program executes and are checked every time a memory address m is accessed through a pointer p;if the taint marks associated with mand p differ, the execution is stopped and the illegalaccess is reported. To allow for a low-overhead, hardware-assisted implementation of the approach, we make several key technical and engineering decisions in the definition of our technique. In particular, we use a configurable, low number of reusable taint marks instead of a unique mark for each area of memory allocated, which reduces the overhead of the approach without limiting its flexibility and ability to target most memory-related faults and attacks known to date. We also define the technique at the binary level, which lets us handle the (very) common case of applications that use third-party libraries whose source code is unavailable. To investigate the effectiveness and practicality of our approach, we implemented it for heap-allocated memory and performed a preliminary empirical study on a set of programs. Our results show that (1) our technique can identify a large class of memory-related faults, even when using only two unique taint marks, and (2)a hardware-assisted implementation of the technique could achieve overhead in the single digits. Copyright 2007 ACM.

关键词： Crime

来源：评论

学校读者我要写书评

暂无评论

A resource optimized SoC Kit for FPGAs

A resource optimized SoC Kit for FPGAs

引用

International conference on Field Programmable Logic and applications

作者： Gerald Hempel Christian Hochberger Chair for Embedded Systems Dresden University of Technology Dresden Germany

Modern FPGAs have become so affordable that they can be used to substitute ASICs in mass produced devices. A key component of such configurable system on a chip (CSoC) is the processor core. Available and usable cores are either 32 or 8 bit wide. Thus, there is a gap between these two extremes, which we want to fill with our SoC kit. In this contribution we elaborate on our SoC kit and its components and compare it to other SoC design environments.

关键词： Field programmable gate arrays System-on-a-chip Process design Computer architecture Embedded system Reduced instruction set computing Manufacturing processes Costs Fitting Availability

来源：评论

学校读者我要写书评

暂无评论

A Case for Soft Vector Processors in FPGAs

A Case for Soft Vector Processors in FPGAs

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： Jason Yu Guy Lemieux Department of Electrical and Computer Engineering University of British Columbia Vancouver Canada

Embedded applications today require high computational power that is not met by current FPGA-based soft processors. Although performance of data-parallel applications can be addressed by custom-designed hardware accelerators, such an approach is difficult for embedded software developers with little hardware design experience. Instead, vector processing can be used to speed up these same data-parallel applications. The vector programming model is easy to understand by software developers, making it easier for them to extract the parallelism without any hardware design knowledge. This paper proposes a soft vector processor for the Stratix III FPGA that can be scaled to different levels of performance and resource utilization. It has several configurable features that can be included or excluded to optimize the soft processor for a given application. Performance estimates of the soft vector processor using three embedded benchmark kernels show speedup of up to 16.6 x over an idealized Nios II processor while using 10.9 x the area.

关键词： Vector processors Field programmable gate arrays Application software Hardware Embedded computing Embedded software Parallel programming Parallel processing Resource management Kernel

来源：评论

学校读者我要写书评

暂无评论

pDomus: a prototype for Cluster-oriented Distributed Hash Tables

pDomus: a prototype for Cluster-oriented Distributed Hash Ta...

引用

Euromicro conference on Parallel, Distributed and Network-Based Processing

作者： Jose Rufino Albano Alves Jose Exposto Antonio Pina Polytechnic Institute of Bragança Braganca Portugal University of Minho Braga Portugal

The Domus architecture for distributed hash tables (DHTs) is specially designed to support the concurrent deployment of multiple and heterogeneous DHTs, in a dynamic shared-all cluster environment. The execution model is compatible with the simultaneous access of several distributed/parallel client applications to the same or different running DHTs. Support to distributed routing and storage is dynamically configurable per node, as a function of applications requirements, node base resources and the overall cluster communication, memory and storage usage. pDomus is a prototype of Domus that creates an environment where to evaluate the model embedded concepts and planned features. In this paper, we present a series of experiments conduced to obtain figures of merit i) for the performance of basic dictionary operations, and ii) for the storage overhead resulting from several storage technologies. We also formulate a ranking formula that takes into account access patterns of clients to DHTs, to objectively select the most adequate storage technology, as a valuable metric for a wide range of application scenarios. Finally, we also evaluate client applications and services scalability, for a select dictionary operation. Results of the overall evaluation are promising and a motivation for further work

关键词： Prototypes Dictionaries Routing Peer to peer computing Scalability Partitioning algorithms Computer applications Distributed computing Workstations Large scale integration

来源：评论

学校读者我要写书评

暂无评论

A Coarse-Grained Dynamically Reconfigurable Processing Array (RPA) for Multimedia Application

A Coarse-Grained Dynamically Reconfigurable Processing Array...

引用

International conference on Natural Computation (ICNC)

作者： Guochang Zhou Xubang Shen School of Computer Northwestern Polytechnical University Xi'an China Xi''an Institute of Microelectronic Technology Xi'an China

The accelerating need for higher performance, due to complex and real-time applications, has made reconfigurable architectures the best platform for solving such problems. A novel dynamically reconfigurable processing array (RPA) is proposed in this paper. The interconnection network and reconfigurable processing units(RPUs) of RPA can be dynamically reconfigured to arrange different interconnection networks and support different arithmetic representations and bits wide by the configurable word. The RPA with 8times8 coarse-grained RPUs matrix can be organized as SIMD architecture, as well as MIMD architecture. Through the results of the DCT transform and FIR filter algorithms mapping into RPA, RPA performs the multimedia related operations efficiently Based on Charter 0.25 um process standard cell library, the area of RPA is 7times7 mm 2 and the critical path delay is 16 ns.

关键词： Multiprocessor interconnection networks Registers Reconfigurable architectures Computer architecture Application software Acceleration Application specific integrated circuits Multiplexing High performance computing Arithmetic

来源：评论

学校读者我要写书评

暂无评论

Optimizing the design of a configurable digital signal processor for accelerated execution of the 2-D discrete cosine transform

Optimizing the design of a configurable digital signal proce...

引用

39th Annual Hawaii International conference on System Sciences, HICSS'06

作者： Gloster Jr., Clay Gay, Wanda Amoo, Michaela Chouikha, Mohamed Department of Electrical and Computer Engineering Howard University Washington DC 20059

ISBN: (纸本)0769525075

The advance of mobile electronics technology has produced handheld appliances allowing both wireless voice and data communications. As data communications become increasingly important in mobile computing applications, traditional microprocessors and the accompanying software are increasingly less able to meet the size constraints of these applications while delivering increased performance. One of the most important operations in the realm of digital signal and image processing is the 2-D Discrete Cosine Transform, used to compress both still images and streaming video. The BISON configurable Digital Signal Processor(BCDSP) architecture detailed here uses multiple memories, few instructions, and a special pipelined floating point arithmetic function core to run on a commercially available Field Programmable Gate Array(FPGA) board. The results demonstrate that although the clock speed of the FPGA board was 2 orders of magnitude slower than the microprocessor used in this study, the BCDSP implementation was still significantly faster. © 2006 IEEE.

关键词： Digital signal processing

来源：评论

学校读者我要写书评

暂无评论

Runtime metrics collection for middleware supported adaptation of mobile applications

Runtime metrics collection for middleware supported adaptati...

引用

5th Workshop on Adaptive and Reflective Middleware held at the ACM/IFIP/USENIX International Middleware conference, ARM '06

作者： Gani, Hendrik Ryan, Caspar Rossi, Pablo School of Computer Science and Information Technology RMIT University Melbourne Australia

ISBN: (纸本)1595934197

This paper proposes, implements, and evaluates in terms of worst case performance, an online metrics collection strategy to facilitate application adaptation via object mobility using a mobile object framework and supporting middleware. The solution is based upon an abstract representation of the mobile object system, which holds containers aggregating metrics for each specific component including host managers, runtimes and mobile objects. A key feature of the solution is the specification of multiple configurable criteria to control the measurement and propagation of metrics through the system. The MobJeX platform was used as the basis for implementation and testing with a number of laboratory tests conducted to measure scalability, efficiency and the application of simple measurement and propagation criteria to reduce collection overhead. Copyright 2006 ACM.

关键词： Adaptive systems

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共34页 << < 22 23 24 25 26 27 28 29 30 31 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：